Patch "bgmac: stop clearing DMA receive control register right after it is set" has been added to the 4.4-stable tree

This is a note to let you know that I've just added the patch titled

bgmac: stop clearing DMA receive control register right after it is set

to the 4.4-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
bgmac-stop-clearing-dma-receive-control-register-right-after-it-is-set.patch
and it can be found in the queue-4.4 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Andy Gospodarek <[email protected]>
Date: Mon, 31 Oct 2016 13:32:03 -0400
Subject: bgmac: stop clearing DMA receive control register right after it is set

From: Andy Gospodarek <[email protected]>

[ Upstream commit fcdefccac976ee51dd6071832b842d8fb41c479c ]

Current bgmac code initializes some DMA settings in the receive control register for some hardware and then immediately clears those settings. Not clearing those settings results in ~420Mbps *improvement* in throughput; this system can now receive frames at line-rate on Broadcom 5871x hardware compared to ~520Mbps today. I also tested a few other values but found there to be no discernible difference in CPU utilization even if burst size and prefetching values are different.

On the hardware tested there was no need to keep the code that cleared all but bits 16-17, but since there is a wide variety of hardware that used this driver (I did not look at all hardware docs for hardware using this IP block), I find it wise to move this call up and clear bits just after reading the default value from the hardware rather than completely removing it.

This is a good candidate for -stable >=3.14 since that is when the code that was supposed to improve performance (but did not) was introduced.

---
 drivers/net/ethernet/broadcom/bgmac.c |    5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

@@ -314,6 +314,10 @@ static void bgmac_dma_rx_enable(struct b
 	u32 ctl;
 
 	ctl = bgmac_read(bgmac, ring->mmio_base + BGMAC_DMA_RX_CTL);
+
+	/* preserve ONLY bits 16-17 from current hardware value */
+	ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
+
 	if (bgmac->core->id.rev >= 4) {
 		ctl &= ~BGMAC_DMA_RX_BL_MASK;
 		ctl |= BGMAC_DMA_RX_BL_128 << BGMAC_DMA_RX_BL_SHIFT;

@@ -324,7 +328,6 @@ static void bgmac_dma_rx_enable(struct b
 		ctl &= ~BGMAC_DMA_RX_PT_MASK;
 		ctl |= BGMAC_DMA_RX_PT_1 << BGMAC_DMA_RX_PT_SHIFT;
 	}
-	ctl &= BGMAC_DMA_RX_ADDREXT_MASK;
 	ctl |= BGMAC_DMA_RX_ENABLE;
 	ctl |= BGMAC_DMA_RX_PARITY_DISABLE;
 	ctl |= BGMAC_DMA_RX_OVERFLOW_CONT;

Patches currently in stable-queue which might be from [email protected] are

queue-4.4/bgmac-stop-clearing-dma-receive-control-register-right-after-it-is-set.patch