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powerpc: Set missing wakeup bit in LPCR on POWER9

PATCH Applied Benjamin Herrenschmidt 3 participants 3 messages Nov 21, 2016 – Nov 24, 2016 PowerPC

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Benjamin Herrenschmidt

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PATCH 1/1 powerpc: Set missing wakeup bit in LPCR on POWER9

There is a new bit, LPCR_PECEu0, which controls wakeup from STOP states on Hypervisor Virtualization Interrupts (which happen to also be all external interrupts in host or bare metal mode).

It needs to be set or we will miss wakeups.

Signed-off-by Benjamin Herrenschmidt <[email protected]>

---

Paul, I haven't fixed KVM. You probably should include such a fix as part of your KVM-on-power9 series.

Michael: That should probably go to -stable as far as P9 support goes.

 arch/powerpc/include/asm/reg.h        | 2 ++
 arch/powerpc/kernel/cpu_setup_power.S | 8 ++++----
 2 files changed, 6 insertions(+), 4 deletions(-)
arch/powerpc/include/asm/reg.h +2 -0
index 9cd4e8c..decef22 100644
@@ -341,6 +341,8 @@
 #define   LPCR_VRMA_L		ASM_CONST(0x0008000000000000)
 #define   LPCR_VRMA_LP0		ASM_CONST(0x0001000000000000)
 #define   LPCR_VRMA_LP1		ASM_CONST(0x0000800000000000)
+#define   LPCR_PECEu		ASM_CONST(0x0000700000000000)   /* P9 PECE "upper" */
+#define   LPCR_PECEu0		ASM_CONST(0x0000400000000000)   /* P9 Wakeup on HV interrupts" */
 #define   LPCR_RMLS		0x1C000000	/* Implementation dependent RMO limit sel */
 #define   LPCR_RMLS_SH		26
 #define   LPCR_ILE		ASM_CONST(0x0000000002000000)   /* !HV irqs set MSR:LE */
arch/powerpc/kernel/cpu_setup_power.S +4 -4
index 52ff3f0..cbf3375 100644
@@ -98,8 +98,8 @@ _GLOBAL(__setup_cpu_power9)
 	li	r0,0
 	mtspr	SPRN_LPID,r0
 	mfspr	r3,SPRN_LPCR
-	ori	r3, r3, LPCR_PECEDH
-	ori	r3, r3, LPCR_HVICE
+	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECEu0 | LPCR_HVICE)
+	or	r3, r3, r4
 	bl	__init_LPCR
 	bl	__init_HFSCR
 	bl	__init_tlb_power9

@@ -118,8 +118,8 @@ _GLOBAL(__restore_cpu_power9)
 	li	r0,0
 	mtspr	SPRN_LPID,r0
 	mfspr   r3,SPRN_LPCR
-	ori	r3, r3, LPCR_PECEDH
-	ori	r3, r3, LPCR_HVICE
+	LOAD_REG_IMMEDIATE(r4, LPCR_PECEDH | LPCR_PECEu0 | LPCR_HVICE)
+	or	r3, r3, r4
 	bl	__init_LPCR
 	bl	__init_HFSCR
 	bl	__init_tlb_power9
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#1 lore raw
Quoted 6 lines · Benjamin Herrenschmidt

There is a new bit, LPCR_PECEu0, which controls wakeup from STOP states on Hypervisor Virtualization Interrupts (which happen to also be all external interrupts in host or bare metal mode).

It needs to be set or we will miss wakeups.

Quoted 7 lines
Signed-off-by Benjamin Herrenschmidt <[email protected]>

---

Paul, I haven't fixed KVM. You probably should include such a fix as part of your KVM-on-power9 series.

Michael: That should probably go to -stable as far as P9 support goes.

I ended up with:

powerpc: Set missing wakeup bit in LPCR on POWER9

There is a new bit, LPCR_PECE_HVEE (Hypervisor Virtualization Exit Enable), which controls wakeup from STOP states on Hypervisor Virtualization Interrupts (which happen to also be all external interrupts in host or bare metal mode).

It needs to be set or we will miss wakeups.

Fixes 9baaef0a22c8 ("powerpc/irq: Add support for HV virtualization interrupts")
Cc [email protected] # v4.8+
Signed-off-by Benjamin Herrenschmidt <[email protected]>
[mpe: Rename it to HVEE to match the name in the ISA]
Signed-off-by Michael Ellerman <[email protected]>

cheers

Applied
#2 lore raw
In reply to Benjamin Herrenschmidt
Quoted 7 lines · Benjamin Herrenschmidt

There is a new bit, LPCR_PECEu0, which controls wakeup from STOP states on Hypervisor Virtualization Interrupts (which happen to also be all external interrupts in host or bare metal mode).

It needs to be set or we will miss wakeups.

Signed-off-by Benjamin Herrenschmidt <[email protected]>

Applied to powerpc fixes, thanks.

https://git.kernel.org/powerpc/c/7a43906f5cbfb74712af168988455e

cheers