sim: port for OpenRISC

index afbca6d..d7124fe 100644
@@ -93,6 +93,25 @@ divsf (CGEN_FPU* fpu, SF x, SF y)
 }
 
 static SF
+remsf (CGEN_FPU* fpu, SF x, SF y)
+{
+  sim_fpu op1;
+  sim_fpu op2;
+  sim_fpu ans;
+  unsigned32 res;
+  sim_fpu_status status;
+
+  sim_fpu_32to (&op1, x);
+  sim_fpu_32to (&op2, y);
+  status = sim_fpu_rem (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
+  sim_fpu_to32 (&res, &ans);
+
+  return res;
+}
+
+static SF
 negsf (CGEN_FPU* fpu, SF x)
 {
   sim_fpu op1;

@@ -452,6 +471,25 @@ divdf (CGEN_FPU* fpu, DF x, DF y)
   return res;
 }
 
+static SF
+remdf (CGEN_FPU* fpu, DF x, DF y)
+{
+  sim_fpu op1;
+  sim_fpu op2;
+  sim_fpu ans;
+  unsigned64 res;
+  sim_fpu_status status;
+
+  sim_fpu_64to (&op1, x);
+  sim_fpu_64to (&op2, y);
+  status = sim_fpu_rem (&ans, &op1, &op2);
+  if (status != 0)
+    (*fpu->ops->error) (fpu, status);
+  sim_fpu_to64(&res, &ans);
+
+  return res;
+}
+
 static DF
 negdf (CGEN_FPU* fpu, DF x)
 {

@@ -664,6 +702,7 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
   o->subsf = subsf;
   o->mulsf = mulsf;
   o->divsf = divsf;
+  o->remsf = remsf;
   o->negsf = negsf;
   o->abssf = abssf;
   o->sqrtsf = sqrtsf;

@@ -682,6 +721,7 @@ cgen_init_accurate_fpu (SIM_CPU* cpu, CGEN_FPU* fpu, CGEN_FPU_ERROR_FN* error)
   o->subdf = subdf;
   o->muldf = muldf;
   o->divdf = divdf;
+  o->remdf = remdf;
   o->negdf = negdf;
   o->absdf = absdf;
   o->sqrtdf = sqrtdf;

index 134b4d0..5f9b55d 100644
@@ -69,6 +69,7 @@ struct cgen_fp_ops {
   SF (*subsf) (CGEN_FPU*, SF, SF);
   SF (*mulsf) (CGEN_FPU*, SF, SF);
   SF (*divsf) (CGEN_FPU*, SF, SF);
+  SF (*remsf) (CGEN_FPU*, SF, SF);
   SF (*negsf) (CGEN_FPU*, SF);
   SF (*abssf) (CGEN_FPU*, SF);
   SF (*sqrtsf) (CGEN_FPU*, SF);

@@ -93,6 +94,7 @@ struct cgen_fp_ops {
   DF (*subdf) (CGEN_FPU*, DF, DF);
   DF (*muldf) (CGEN_FPU*, DF, DF);
   DF (*divdf) (CGEN_FPU*, DF, DF);
+  DF (*remdf) (CGEN_FPU*, DF, DF);
   DF (*negdf) (CGEN_FPU*, DF);
   DF (*absdf) (CGEN_FPU*, DF);
   DF (*sqrtdf) (CGEN_FPU*, DF);

@@ -142,6 +144,7 @@ struct cgen_fp_ops {
   XF (*subxf) (CGEN_FPU*, XF, XF);
   XF (*mulxf) (CGEN_FPU*, XF, XF);
   XF (*divxf) (CGEN_FPU*, XF, XF);
+  XF (*remxf) (CGEN_FPU*, XF, XF);
   XF (*negxf) (CGEN_FPU*, XF);
   XF (*absxf) (CGEN_FPU*, XF);
   XF (*sqrtxf) (CGEN_FPU*, XF);

@@ -180,6 +183,7 @@ struct cgen_fp_ops {
   TF (*subtf) (CGEN_FPU*, TF, TF);
   TF (*multf) (CGEN_FPU*, TF, TF);
   TF (*divtf) (CGEN_FPU*, TF, TF);
+  TF (*remtf) (CGEN_FPU*, TF, TF);
   TF (*negtf) (CGEN_FPU*, TF);
   TF (*abstf) (CGEN_FPU*, TF);
   TF (*sqrttf) (CGEN_FPU*, TF);

78 lines not on this page · raw message

index eb00beb..2b1c9fe 100644
@@ -151,6 +151,7 @@ typedef enum
   sim_fpu_status_overflow = 4096,
   sim_fpu_status_underflow = 8192,
   sim_fpu_status_denorm = 16384,
+  sim_fpu_status_invalid_irx = 32768, /* (inf % X) */
 } sim_fpu_status;
 
 

@@ -230,6 +231,8 @@ INLINE_SIM_FPU (int) sim_fpu_mul (sim_fpu *f,
 				  const sim_fpu *l, const sim_fpu *r);
 INLINE_SIM_FPU (int) sim_fpu_div (sim_fpu *f,
 				  const sim_fpu *l, const sim_fpu *r);
+INLINE_SIM_FPU (int) sim_fpu_rem (sim_fpu *f,
+				  const sim_fpu *l, const sim_fpu *r);
 INLINE_SIM_FPU (int) sim_fpu_max (sim_fpu *f,
 				  const sim_fpu *l, const sim_fpu *r);
 INLINE_SIM_FPU (int) sim_fpu_min (sim_fpu *f,

index 7ff1b4d..81ba02c 100644
@@ -631,6 +631,22 @@ SUBOFQI (QI a, QI b, BI c)
   return res;
 }
 
+SEMOPS_INLINE BI
+MUL2OFSI (SI a, SI b)
+{
+  DI tmp = MULDI (EXTSIDI(a), EXTSIDI(b));
+  BI res = tmp < -0x80000000LL || tmp > 0x7fffffffLL;
+  return res;
+}
+
+SEMOPS_INLINE BI
+MUL1OFSI (USI a, USI b)
+{
+  UDI tmp = MULDI (ZEXTSIDI(a), ZEXTSIDI(b));
+  BI res = (tmp > 0xFFFFFFFFULL);
+  return res;
+}
+
 #else
 
 SI ADDCSI (SI, SI, BI);

@@ -651,6 +667,8 @@ UBI ADDOFQI (QI, QI, BI);
 QI SUBCQI (QI, QI, BI);
 UBI SUBCFQI (QI, QI, BI);
 UBI SUBOFQI (QI, QI, BI);
+BI MUL1OFSI (SI a, SI b);
+BI MUL2OFSI (SI a, SI b);
 
 #endif
 

new file mode 100644
index 0000000..88202a2
@@ -0,0 +1,5 @@
+#ifndef WANT_OR1K64
+#include "arch32.h"
+#else
+#include "arch64.h"
+#endif

new file mode 100644
index 0000000..769f54c
@@ -0,0 +1,38 @@
+/* Simulator support for or1k.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_OR1K32BF
+  & or32_mach,
+#endif
+#ifdef HAVE_CPU_OR1K32BF
+  & or32nd_mach,
+#endif
+  0
+};
+

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new file mode 100644
index 0000000..e73f37b
@@ -0,0 +1,38 @@
+/* Simulator support for or1k.
+
+THIS FILE IS MACHINE GENERATED WITH CGEN.
+
+Copyright 1996-2010 Free Software Foundation, Inc.
+
+This file is part of the GNU simulators.
+
+   This file is free software; you can redistribute it and/or modify
+   it under the terms of the GNU General Public License as published by
+   the Free Software Foundation; either version 3, or (at your option)
+   any later version.
+
+   It is distributed in the hope that it will be useful, but WITHOUT
+   ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+   or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
+   License for more details.
+
+   You should have received a copy of the GNU General Public License along
+   with this program; if not, write to the Free Software Foundation, Inc.,
+   51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
+
+*/
+
+#include "sim-main.h"
+#include "bfd.h"
+
+const MACH *sim_machs[] =
+{
+#ifdef HAVE_CPU_OR1K64BF
+  & or64_mach,
+#endif
+#ifdef HAVE_CPU_OR1K64BF
+  & or64nd_mach,
+#endif
+  0
+};
+

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index 9f6e207..aca7333 100644
@@ -136,6 +136,9 @@ void or1k32bf_nop (sim_cpu *current_cpu, USI uimm16)
     break;
     
   case NOP_EXIT:
+    sim_io_printf (CPU_STATE(current_cpu), "exit(%d)\n", GET_H_GPR(3));
+    /* fall through */
+  case NOP_EXIT_SILENT:
     sim_engine_halt (sd, current_cpu, NULL, CPU_PC_GET (current_cpu), sim_exited, GET_H_GPR (3));
     break;
 

index 513c946..f1c9b73 100644
@@ -1,17 +1,18 @@
 #ifndef OR1K_H
 #define OR1K_H
 
-#define NOP_NOP       0x0
-#define NOP_EXIT      0x1
-#define NOP_REPORT    0x2
-#define NOP_PUTC      0x4
-#define NOP_CNT_RESET 0x5
-#define NOP_GET_TICKS 0x6
-#define NOP_GET_PS    0x7
-#define NOP_TRACE_ON  0x8
-#define NOP_TRACE_OFF 0x9
-#define NOP_RANDOM    0xa
-#define NOP_OR1KSIM   0xb
+#define NOP_NOP         0x0
+#define NOP_EXIT        0x1
+#define NOP_REPORT      0x2
+#define NOP_PUTC        0x4
+#define NOP_CNT_RESET   0x5
+#define NOP_GET_TICKS   0x6
+#define NOP_GET_PS      0x7
+#define NOP_TRACE_ON    0x8
+#define NOP_TRACE_OFF   0x9
+#define NOP_RANDOM      0xa
+#define NOP_OR1KSIM     0xb
+#define NOP_EXIT_SILENT 0xc
 
 #define NUM_SPR 0x20000
 #define SPR_GROUP_SHIFT 11

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index f1c9b73..e71a845 100644
@@ -19,12 +19,20 @@
 #define SPR_GROUP_FIRST(group) (((UWI) SPR_GROUP_##group) << SPR_GROUP_SHIFT)
 #define SPR_GROUP_LAST(group) (SPR_GROUP_FIRST | (((UWI) 1 << SPR_GROUP_SHIFT) - 1))
 #define SPR_ADDR(group,index) (SPR_GROUP_FIRST(group) | ((UWI) SPR_INDEX_##group##_##index))
+#define SPR_ADDR_GROUP(addr) (((UWI) (addr)) >> SPR_GROUP_SHIFT)
+#define SPR_INDEX_MASK (~(~((UWI) 0) << SPR_GROUP_SHIFT))
+#define SPR_ADDR_INDEX(addr) (((UWI) (addr)) && SPR_INDEX_MASK)
 #define SPR_FIELD(group,index,field,val) ((SPR_FIELD_MASK_##group##_##index##_##field & (val)) >> SPR_FIELD_LSB_##group##_##index##_##field)
 
 #ifdef WANT_CPU_OR1K32BF
 void or1k32bf_cpu_init (SIM_DESC sd, sim_cpu *current_cpu);
-void or1k32bf_insn_before (sim_cpu *current_cpu, SEM_PC vpc);
-SEM_PC or1k32bf_insn_after (sim_cpu *current_cpu, SEM_PC vpc);
+void or1k32bf_insn_before (sim_cpu *current_cpu, SEM_PC vpc, IDESC *idesc);
+void or1k32bf_insn_after (sim_cpu *current_cpu, SEM_PC vpc, IDESC *idesc);
+void or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum);
+void or1k32bf_rfe (sim_cpu *current_cpu);
+void or1k32bf_nop (sim_cpu *current_cpu, USI uimm16);
+USI or1k32bf_mfspr (sim_cpu *current_cpu, USI addr);
+void or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val);
 #endif
 
 #endif

index 8b27906..d26d616 100644
@@ -44,6 +44,11 @@ struct _sim_cpu {
      go after here.  Oh for a better language.  */
   UWI spr[NUM_SPR];
 
+  /* next instruction will be in delay slot */
+  BI next_delay_slot;
+  /* currently in delay slot */
+  BI delay_slot;
+
 #ifdef WANT_CPU_OR1K32BF
   OR1K32BF_CPU_DATA cpu_data;
 #endif

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index 45147d2..776e720 100644
@@ -187,11 +187,6 @@ USI or1k32bf_make_load_store_addr (sim_cpu *current_cpu, USI base, SI offset, in
 {
   SIM_DESC sd = CPU_STATE(current_cpu);
 
-  if (!GET_H_SYS_SR_SM ()) {
-    sim_io_eprintf(sd, "WARNING: l.mfspr in user mode\n");
-    return;
-  }
-  
   USI addr = base + offset;
   
   if (GET_H_SYS_SR_LEE ()) {

index 776e720..98225ab 100644
@@ -225,8 +225,8 @@ USI or1k32bf_fl1 (sim_cpu *current_cpu, USI val)
 {
   USI bit;
   USI ret;
-  for (bit = 1, ret = 1; bit; bit <<= 1, ret++) {
-    if (!(val & bit))
+  for (bit = 1 << 31, ret = 32; bit; bit >>= 1, ret--) {
+    if (val & bit)
       return ret;
   }
   return 0;

index d503534..36b4040 100644
@@ -9292,6 +9292,22 @@ or1k32bf_h_mac_machi_set (SIM_CPU *current_cpu, USI newval)
   SET_H_MAC_MACHI (newval);
 }
 
+/* Get the value of h-tick-ttmr.  */
+
+USI
+or1k32bf_h_tick_ttmr_get (SIM_CPU *current_cpu)
+{
+  return GET_H_TICK_TTMR ();
+}
+
+/* Set a value for h-tick-ttmr.  */
+
+void
+or1k32bf_h_tick_ttmr_set (SIM_CPU *current_cpu, USI newval)
+{
+  SET_H_TICK_TTMR (newval);
+}
+
 /* Get the value of h-sys-vr-rev.  */
 
 USI

index e3a8276..a31a935 100644
@@ -2944,6 +2944,11 @@ SET_H_SPR (ORSI (SLLSI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACLO), (x));\
 do { \
 SET_H_SPR (ORSI (SLLSI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACHI), (x));\
 ;} while (0)
+#define GET_H_TICK_TTMR() GET_H_SPR (ORSI (SLLSI (SPR_GROUP_TICK, 11), SPR_INDEX_TICK_TTMR))
+#define SET_H_TICK_TTMR(x) \
+do { \
+SET_H_SPR (ORSI (SLLSI (SPR_GROUP_TICK, 11), SPR_INDEX_TICK_TTMR), (x));\
+;} while (0)
 #define GET_H_SYS_VR_REV() or1k32bf_h_spr_field_get_raw (current_cpu, ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), 5, 0)
 #define SET_H_SYS_VR_REV(x) \
 do { \

@@ -4364,6 +4369,8 @@ USI or1k32bf_h_mac_maclo_get (SIM_CPU *);
 void or1k32bf_h_mac_maclo_set (SIM_CPU *, USI);
 USI or1k32bf_h_mac_machi_get (SIM_CPU *);
 void or1k32bf_h_mac_machi_set (SIM_CPU *, USI);
+USI or1k32bf_h_tick_ttmr_get (SIM_CPU *);
+void or1k32bf_h_tick_ttmr_set (SIM_CPU *, USI);
 USI or1k32bf_h_sys_vr_rev_get (SIM_CPU *);
 void or1k32bf_h_sys_vr_rev_set (SIM_CPU *, USI);
 USI or1k32bf_h_sys_vr_cfg_get (SIM_CPU *);

@@ -4822,14 +4829,14 @@ struct scache {
   f_resv_7_4 = EXTRACT_LSB0_UINT (insn, 32, 7, 4); \
   f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
 
-#define EXTRACT_IFMT_L_SFGTU_VARS \
+#define EXTRACT_IFMT_L_SFGTS_VARS \
   UINT f_opcode; \
   UINT f_op_25_5; \
   UINT f_r2; \
   UINT f_r3; \
   UINT f_resv_10_11; \
   unsigned int length;
-#define EXTRACT_IFMT_L_SFGTU_CODE \
+#define EXTRACT_IFMT_L_SFGTS_CODE \
   length = 4; \
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
   f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \

@@ -4837,19 +4844,6 @@ struct scache {
   f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
   f_resv_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
 
-#define EXTRACT_IFMT_L_SFGTUI_VARS \
-  UINT f_opcode; \
-  UINT f_op_25_5; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_L_SFGTUI_CODE \
-  length = 4; \
-  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
-  f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
-  f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
-
 #define EXTRACT_IFMT_L_SFGTSI_VARS \
   UINT f_opcode; \
   UINT f_op_25_5; \

@@ -4882,20 +4876,16 @@ struct scache {
 
 #define EXTRACT_IFMT_L_MACI_VARS \
   UINT f_opcode; \
-  UINT f_resv_20_5; \
+  UINT f_resv_25_5; \
   UINT f_r2; \
-  UINT f_imm16_25_5; \
-  UINT f_imm16_10_11; \
-  INT f_simm16_split; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_IFMT_L_MACI_CODE \
   length = 4; \
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_resv_20_5 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
   f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
-  f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
-  f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
-  f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));\
+  f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
 
 #define EXTRACT_IFMT_LF_ADD_S_VARS \
   UINT f_opcode; \

index 1cb4487..cd25e89 100644
@@ -9308,6 +9308,22 @@ or1k64bf_h_mac_machi_set (SIM_CPU *current_cpu, UDI newval)
   SET_H_MAC_MACHI (newval);
 }
 
+/* Get the value of h-tick-ttmr.  */
+
+UDI
+or1k64bf_h_tick_ttmr_get (SIM_CPU *current_cpu)
+{
+  return GET_H_TICK_TTMR ();
+}
+
+/* Set a value for h-tick-ttmr.  */
+
+void
+or1k64bf_h_tick_ttmr_set (SIM_CPU *current_cpu, UDI newval)
+{
+  SET_H_TICK_TTMR (newval);
+}
+
 /* Get the value of h-sys-vr-rev.  */
 
 UDI

index c17c960..5bfbf9e 100644
@@ -2949,6 +2949,11 @@ SET_H_SPR (ORDI (SLLDI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACLO), (x));\
 do { \
 SET_H_SPR (ORDI (SLLDI (SPR_GROUP_MAC, 11), SPR_INDEX_MAC_MACHI), (x));\
 ;} while (0)
+#define GET_H_TICK_TTMR() GET_H_SPR (ORDI (SLLDI (SPR_GROUP_TICK, 11), SPR_INDEX_TICK_TTMR))
+#define SET_H_TICK_TTMR(x) \
+do { \
+SET_H_SPR (ORDI (SLLDI (SPR_GROUP_TICK, 11), SPR_INDEX_TICK_TTMR), (x));\
+;} while (0)
 #define GET_H_SYS_VR_REV() or1k64bf_h_spr_field_get_raw (current_cpu, ORDI (SLLDI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_VR), 5, 0)
 #define SET_H_SYS_VR_REV(x) \
 do { \

@@ -4371,6 +4376,8 @@ UDI or1k64bf_h_mac_maclo_get (SIM_CPU *);
 void or1k64bf_h_mac_maclo_set (SIM_CPU *, UDI);
 UDI or1k64bf_h_mac_machi_get (SIM_CPU *);
 void or1k64bf_h_mac_machi_set (SIM_CPU *, UDI);
+UDI or1k64bf_h_tick_ttmr_get (SIM_CPU *);
+void or1k64bf_h_tick_ttmr_set (SIM_CPU *, UDI);
 UDI or1k64bf_h_sys_vr_rev_get (SIM_CPU *);
 void or1k64bf_h_sys_vr_rev_set (SIM_CPU *, UDI);
 UDI or1k64bf_h_sys_vr_cfg_get (SIM_CPU *);

@@ -4821,14 +4828,14 @@ struct scache {
   f_resv_7_4 = EXTRACT_LSB0_UINT (insn, 32, 7, 4); \
   f_op_3_4 = EXTRACT_LSB0_UINT (insn, 32, 3, 4); \
 
-#define EXTRACT_IFMT_L_SFGTU_VARS \
+#define EXTRACT_IFMT_L_SFGTS_VARS \
   UINT f_opcode; \
   UINT f_op_25_5; \
   UINT f_r2; \
   UINT f_r3; \
   UINT f_resv_10_11; \
   unsigned int length;
-#define EXTRACT_IFMT_L_SFGTU_CODE \
+#define EXTRACT_IFMT_L_SFGTS_CODE \
   length = 4; \
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
   f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \

@@ -4836,19 +4843,6 @@ struct scache {
   f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
   f_resv_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
 
-#define EXTRACT_IFMT_L_SFGTUI_VARS \
-  UINT f_opcode; \
-  UINT f_op_25_5; \
-  UINT f_r2; \
-  UINT f_uimm16; \
-  unsigned int length;
-#define EXTRACT_IFMT_L_SFGTUI_CODE \
-  length = 4; \
-  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
-  f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
-  f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
-
 #define EXTRACT_IFMT_L_SFGTSI_VARS \
   UINT f_opcode; \
   UINT f_op_25_5; \

@@ -4881,20 +4875,16 @@ struct scache {
 
 #define EXTRACT_IFMT_L_MACI_VARS \
   UINT f_opcode; \
-  UINT f_resv_20_5; \
+  UINT f_resv_25_5; \
   UINT f_r2; \
-  UINT f_imm16_25_5; \
-  UINT f_imm16_10_11; \
-  INT f_simm16_split; \
+  INT f_simm16; \
   unsigned int length;
 #define EXTRACT_IFMT_L_MACI_CODE \
   length = 4; \
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_resv_20_5 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_resv_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
   f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
-  f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
-  f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
-  f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));\
+  f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
 
 #define EXTRACT_IFMT_LF_ADD_S_VARS \
   UINT f_opcode; \

380 lines not on this page · raw message

index 56f4669..a854856 100644
@@ -49,11 +49,11 @@ typedef enum or1k32bf_insn_type {
  , OR1K32BF_INSN_L_FL1, OR1K32BF_INSN_L_ANDI, OR1K32BF_INSN_L_ORI, OR1K32BF_INSN_L_XORI
  , OR1K32BF_INSN_L_ADDI, OR1K32BF_INSN_L_ADDIC, OR1K32BF_INSN_L_MULI, OR1K32BF_INSN_L_EXTHS
  , OR1K32BF_INSN_L_EXTBS, OR1K32BF_INSN_L_EXTHZ, OR1K32BF_INSN_L_EXTBZ, OR1K32BF_INSN_L_EXTWS
- , OR1K32BF_INSN_L_EXTWZ, OR1K32BF_INSN_L_CMOV, OR1K32BF_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGEU
- , OR1K32BF_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLEU, OR1K32BF_INSN_L_SFGTS, OR1K32BF_INSN_L_SFGES
- , OR1K32BF_INSN_L_SFLTS, OR1K32BF_INSN_L_SFLES, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGEUI
- , OR1K32BF_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFGTSI, OR1K32BF_INSN_L_SFGESI
- , OR1K32BF_INSN_L_SFLTSI, OR1K32BF_INSN_L_SFLESI, OR1K32BF_INSN_L_SFEQ, OR1K32BF_INSN_L_SFEQI
+ , OR1K32BF_INSN_L_EXTWZ, OR1K32BF_INSN_L_CMOV, OR1K32BF_INSN_L_SFGTS, OR1K32BF_INSN_L_SFGTSI
+ , OR1K32BF_INSN_L_SFGTU, OR1K32BF_INSN_L_SFGTUI, OR1K32BF_INSN_L_SFGES, OR1K32BF_INSN_L_SFGESI
+ , OR1K32BF_INSN_L_SFGEU, OR1K32BF_INSN_L_SFGEUI, OR1K32BF_INSN_L_SFLTS, OR1K32BF_INSN_L_SFLTSI
+ , OR1K32BF_INSN_L_SFLTU, OR1K32BF_INSN_L_SFLTUI, OR1K32BF_INSN_L_SFLES, OR1K32BF_INSN_L_SFLESI
+ , OR1K32BF_INSN_L_SFLEU, OR1K32BF_INSN_L_SFLEUI, OR1K32BF_INSN_L_SFEQ, OR1K32BF_INSN_L_SFEQI
  , OR1K32BF_INSN_L_SFNE, OR1K32BF_INSN_L_SFNEI, OR1K32BF_INSN_L_MAC, OR1K32BF_INSN_L_MSB
  , OR1K32BF_INSN_L_MACI, OR1K32BF_INSN_L_CUST1, OR1K32BF_INSN_L_CUST2, OR1K32BF_INSN_L_CUST3
  , OR1K32BF_INSN_L_CUST4, OR1K32BF_INSN_L_CUST5, OR1K32BF_INSN_L_CUST6, OR1K32BF_INSN_L_CUST7

@@ -67,17 +67,16 @@ typedef enum or1k32bf_insn_type {
 /* Enum declaration for semantic formats in cpu family or1k32bf.  */
 typedef enum or1k32bf_sfmt_type {
   OR1K32BF_SFMT_EMPTY, OR1K32BF_SFMT_L_J, OR1K32BF_SFMT_L_JAL, OR1K32BF_SFMT_L_JR
- , OR1K32BF_SFMT_L_JALR, OR1K32BF_SFMT_L_BNF, OR1K32BF_SFMT_L_TRAP, OR1K32BF_SFMT_L_NOP_IMM
- , OR1K32BF_SFMT_L_MOVHI, OR1K32BF_SFMT_L_MACRC, OR1K32BF_SFMT_L_MFSPR, OR1K32BF_SFMT_L_MTSPR
- , OR1K32BF_SFMT_L_LWZ, OR1K32BF_SFMT_L_LWS, OR1K32BF_SFMT_L_LBZ, OR1K32BF_SFMT_L_LBS
- , OR1K32BF_SFMT_L_LHZ, OR1K32BF_SFMT_L_LHS, OR1K32BF_SFMT_L_SW, OR1K32BF_SFMT_L_SB
- , OR1K32BF_SFMT_L_SH, OR1K32BF_SFMT_L_SLL, OR1K32BF_SFMT_L_SLLI, OR1K32BF_SFMT_L_AND
- , OR1K32BF_SFMT_L_ADD, OR1K32BF_SFMT_L_ADDC, OR1K32BF_SFMT_L_DIV, OR1K32BF_SFMT_L_FF1
- , OR1K32BF_SFMT_L_ANDI, OR1K32BF_SFMT_L_XORI, OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC
- , OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV, OR1K32BF_SFMT_L_SFGTU, OR1K32BF_SFMT_L_SFGTUI
- , OR1K32BF_SFMT_L_SFGTSI, OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI, OR1K32BF_SFMT_L_CUST1
- , OR1K32BF_SFMT_LF_ADD_S, OR1K32BF_SFMT_LF_ITOF_S, OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S
- , OR1K32BF_SFMT_LF_MADD_S
+ , OR1K32BF_SFMT_L_JALR, OR1K32BF_SFMT_L_BNF, OR1K32BF_SFMT_L_TRAP, OR1K32BF_SFMT_L_RFE
+ , OR1K32BF_SFMT_L_NOP_IMM, OR1K32BF_SFMT_L_MOVHI, OR1K32BF_SFMT_L_MACRC, OR1K32BF_SFMT_L_MFSPR
+ , OR1K32BF_SFMT_L_MTSPR, OR1K32BF_SFMT_L_LWZ, OR1K32BF_SFMT_L_LWS, OR1K32BF_SFMT_L_LBZ
+ , OR1K32BF_SFMT_L_LBS, OR1K32BF_SFMT_L_LHZ, OR1K32BF_SFMT_L_LHS, OR1K32BF_SFMT_L_SW
+ , OR1K32BF_SFMT_L_SB, OR1K32BF_SFMT_L_SH, OR1K32BF_SFMT_L_SLL, OR1K32BF_SFMT_L_SLLI
+ , OR1K32BF_SFMT_L_AND, OR1K32BF_SFMT_L_ADD, OR1K32BF_SFMT_L_ADDC, OR1K32BF_SFMT_L_DIV
+ , OR1K32BF_SFMT_L_FF1, OR1K32BF_SFMT_L_XORI, OR1K32BF_SFMT_L_ADDI, OR1K32BF_SFMT_L_ADDIC
+ , OR1K32BF_SFMT_L_EXTHS, OR1K32BF_SFMT_L_CMOV, OR1K32BF_SFMT_L_SFGTS, OR1K32BF_SFMT_L_SFGTSI
+ , OR1K32BF_SFMT_L_MAC, OR1K32BF_SFMT_L_MACI, OR1K32BF_SFMT_LF_ADD_S, OR1K32BF_SFMT_LF_ITOF_S
+ , OR1K32BF_SFMT_LF_FTOI_S, OR1K32BF_SFMT_LF_EQ_S, OR1K32BF_SFMT_LF_MADD_S
 } OR1K32BF_SFMT_TYPE;
 
 /* Function unit handlers (user written).  */

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index a5f5806..db5f56f 100644
@@ -49,11 +49,11 @@ typedef enum or1k64bf_insn_type {
  , OR1K64BF_INSN_L_FL1, OR1K64BF_INSN_L_ANDI, OR1K64BF_INSN_L_ORI, OR1K64BF_INSN_L_XORI
  , OR1K64BF_INSN_L_ADDI, OR1K64BF_INSN_L_ADDIC, OR1K64BF_INSN_L_MULI, OR1K64BF_INSN_L_EXTHS
  , OR1K64BF_INSN_L_EXTBS, OR1K64BF_INSN_L_EXTHZ, OR1K64BF_INSN_L_EXTBZ, OR1K64BF_INSN_L_EXTWS
- , OR1K64BF_INSN_L_EXTWZ, OR1K64BF_INSN_L_CMOV, OR1K64BF_INSN_L_SFGTU, OR1K64BF_INSN_L_SFGEU
- , OR1K64BF_INSN_L_SFLTU, OR1K64BF_INSN_L_SFLEU, OR1K64BF_INSN_L_SFGTS, OR1K64BF_INSN_L_SFGES
- , OR1K64BF_INSN_L_SFLTS, OR1K64BF_INSN_L_SFLES, OR1K64BF_INSN_L_SFGTUI, OR1K64BF_INSN_L_SFGEUI
- , OR1K64BF_INSN_L_SFLTUI, OR1K64BF_INSN_L_SFLEUI, OR1K64BF_INSN_L_SFGTSI, OR1K64BF_INSN_L_SFGESI
- , OR1K64BF_INSN_L_SFLTSI, OR1K64BF_INSN_L_SFLESI, OR1K64BF_INSN_L_SFEQ, OR1K64BF_INSN_L_SFEQI
+ , OR1K64BF_INSN_L_EXTWZ, OR1K64BF_INSN_L_CMOV, OR1K64BF_INSN_L_SFGTS, OR1K64BF_INSN_L_SFGTSI
+ , OR1K64BF_INSN_L_SFGTU, OR1K64BF_INSN_L_SFGTUI, OR1K64BF_INSN_L_SFGES, OR1K64BF_INSN_L_SFGESI
+ , OR1K64BF_INSN_L_SFGEU, OR1K64BF_INSN_L_SFGEUI, OR1K64BF_INSN_L_SFLTS, OR1K64BF_INSN_L_SFLTSI
+ , OR1K64BF_INSN_L_SFLTU, OR1K64BF_INSN_L_SFLTUI, OR1K64BF_INSN_L_SFLES, OR1K64BF_INSN_L_SFLESI
+ , OR1K64BF_INSN_L_SFLEU, OR1K64BF_INSN_L_SFLEUI, OR1K64BF_INSN_L_SFEQ, OR1K64BF_INSN_L_SFEQI
  , OR1K64BF_INSN_L_SFNE, OR1K64BF_INSN_L_SFNEI, OR1K64BF_INSN_L_MAC, OR1K64BF_INSN_L_MSB
  , OR1K64BF_INSN_L_MACI, OR1K64BF_INSN_L_CUST1, OR1K64BF_INSN_L_CUST2, OR1K64BF_INSN_L_CUST3
  , OR1K64BF_INSN_L_CUST4, OR1K64BF_INSN_L_CUST5, OR1K64BF_INSN_L_CUST6, OR1K64BF_INSN_L_CUST7

@@ -70,18 +70,17 @@ typedef enum or1k64bf_insn_type {
 /* Enum declaration for semantic formats in cpu family or1k64bf.  */
 typedef enum or1k64bf_sfmt_type {
   OR1K64BF_SFMT_EMPTY, OR1K64BF_SFMT_L_J, OR1K64BF_SFMT_L_JAL, OR1K64BF_SFMT_L_JR
- , OR1K64BF_SFMT_L_JALR, OR1K64BF_SFMT_L_BNF, OR1K64BF_SFMT_L_TRAP, OR1K64BF_SFMT_L_NOP_IMM
- , OR1K64BF_SFMT_L_MOVHI, OR1K64BF_SFMT_L_MACRC, OR1K64BF_SFMT_L_MFSPR, OR1K64BF_SFMT_L_MTSPR
- , OR1K64BF_SFMT_L_LWZ, OR1K64BF_SFMT_L_LWS, OR1K64BF_SFMT_L_LBZ, OR1K64BF_SFMT_L_LBS
- , OR1K64BF_SFMT_L_LHZ, OR1K64BF_SFMT_L_LHS, OR1K64BF_SFMT_L_SW, OR1K64BF_SFMT_L_SB
- , OR1K64BF_SFMT_L_SH, OR1K64BF_SFMT_L_SLL, OR1K64BF_SFMT_L_SLLI, OR1K64BF_SFMT_L_AND
- , OR1K64BF_SFMT_L_ADD, OR1K64BF_SFMT_L_ADDC, OR1K64BF_SFMT_L_DIV, OR1K64BF_SFMT_L_FF1
- , OR1K64BF_SFMT_L_ANDI, OR1K64BF_SFMT_L_XORI, OR1K64BF_SFMT_L_ADDI, OR1K64BF_SFMT_L_ADDIC
- , OR1K64BF_SFMT_L_EXTHS, OR1K64BF_SFMT_L_CMOV, OR1K64BF_SFMT_L_SFGTU, OR1K64BF_SFMT_L_SFGTUI
- , OR1K64BF_SFMT_L_SFGTSI, OR1K64BF_SFMT_L_MAC, OR1K64BF_SFMT_L_MACI, OR1K64BF_SFMT_L_CUST1
- , OR1K64BF_SFMT_LF_ADD_S, OR1K64BF_SFMT_LF_ADD_D, OR1K64BF_SFMT_LF_ITOF_S, OR1K64BF_SFMT_LF_ITOF_D
- , OR1K64BF_SFMT_LF_FTOI_S, OR1K64BF_SFMT_LF_FTOI_D, OR1K64BF_SFMT_LF_EQ_S, OR1K64BF_SFMT_LF_EQ_D
- , OR1K64BF_SFMT_LF_MADD_S, OR1K64BF_SFMT_LF_MADD_D
+ , OR1K64BF_SFMT_L_JALR, OR1K64BF_SFMT_L_BNF, OR1K64BF_SFMT_L_TRAP, OR1K64BF_SFMT_L_RFE
+ , OR1K64BF_SFMT_L_NOP_IMM, OR1K64BF_SFMT_L_MOVHI, OR1K64BF_SFMT_L_MACRC, OR1K64BF_SFMT_L_MFSPR
+ , OR1K64BF_SFMT_L_MTSPR, OR1K64BF_SFMT_L_LWZ, OR1K64BF_SFMT_L_LWS, OR1K64BF_SFMT_L_LBZ
+ , OR1K64BF_SFMT_L_LBS, OR1K64BF_SFMT_L_LHZ, OR1K64BF_SFMT_L_LHS, OR1K64BF_SFMT_L_SW
+ , OR1K64BF_SFMT_L_SB, OR1K64BF_SFMT_L_SH, OR1K64BF_SFMT_L_SLL, OR1K64BF_SFMT_L_SLLI
+ , OR1K64BF_SFMT_L_AND, OR1K64BF_SFMT_L_ADD, OR1K64BF_SFMT_L_ADDC, OR1K64BF_SFMT_L_DIV
+ , OR1K64BF_SFMT_L_FF1, OR1K64BF_SFMT_L_XORI, OR1K64BF_SFMT_L_ADDI, OR1K64BF_SFMT_L_ADDIC
+ , OR1K64BF_SFMT_L_EXTHS, OR1K64BF_SFMT_L_CMOV, OR1K64BF_SFMT_L_SFGTS, OR1K64BF_SFMT_L_SFGTSI
+ , OR1K64BF_SFMT_L_MAC, OR1K64BF_SFMT_L_MACI, OR1K64BF_SFMT_LF_ADD_S, OR1K64BF_SFMT_LF_ADD_D
+ , OR1K64BF_SFMT_LF_ITOF_S, OR1K64BF_SFMT_LF_ITOF_D, OR1K64BF_SFMT_LF_FTOI_S, OR1K64BF_SFMT_LF_FTOI_D
+ , OR1K64BF_SFMT_LF_EQ_S, OR1K64BF_SFMT_LF_EQ_D, OR1K64BF_SFMT_LF_MADD_S, OR1K64BF_SFMT_LF_MADD_D
 } OR1K64BF_SFMT_TYPE;
 
 /* Function unit handlers (user written).  */

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index 0000000..c328b20

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index c257ae6..23a8a9e 100644
@@ -235,14 +235,6 @@ sim_open (kind, callback, abfd, argv)
       return 0;
     }
 
-  if ((or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) &&
-      (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1knd)) {
-    sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag set, but loading non-or1knd binary\n");
-  } else if (!(or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) &&
-             (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1k)) {
-    sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag not set, but loading non-or1k binary\n");
-  }
-  
   /* Establish any remaining configuration options.  */
   if (sim_config (sd) != SIM_RC_OK)
     {

@@ -255,7 +247,16 @@ sim_open (kind, callback, abfd, argv)
       free_state (sd);
       return 0;
     }
-
+  
+  /* make sure delay slot mode is consistent with the loaded binary */
+  if ((or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) &&
+      (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1knd)) {
+    sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag set, but loading non-or1knd binary\n");
+  } else if (!(or1k_cpucfgr & SPR_FIELD_MASK_SYS_CPUCFGR_ND) &&
+             (STATE_ARCHITECTURE (sd)->mach != bfd_mach_or1k)) {
+    sim_io_eprintf (sd, "WARNING: CPUCFGR ND flag not set, but loading non-or1k binary\n");
+  }
+  
   /* Open a copy of the cpu descriptor table.  */
   {
     CGEN_CPU_DESC cd = or1k_cgen_cpu_open_1 (STATE_ARCHITECTURE (sd)->printable_name,

index 23a8a9e..e643fa1 100644
@@ -174,7 +174,7 @@ sim_open (kind, callback, abfd, argv)
      SIM_OPEN_KIND kind;
      host_callback *callback;
      struct bfd *abfd;
-     char **argv;
+     char * const *argv;
 {
   SIM_DESC sd = sim_state_alloc (kind, callback);
   char c;

@@ -297,21 +297,13 @@ sim_open (kind, callback, abfd, argv)
   return sd;
 }
 
-void
-sim_close (sd, quitting)
-     SIM_DESC sd;
-     int quitting;
-{
-  or1k_cgen_cpu_close (CPU_CPU_DESC (STATE_CPU (sd, 0)));
-  sim_module_uninstall (sd);
-}
 
 SIM_RC
 sim_create_inferior (sd, abfd, argv, envp)
      SIM_DESC sd;
      struct bfd *abfd;
-     char **argv;
-     char **envp;
+     char * const *argv;
+     char * const *envp;
 {
   SIM_CPU *current_cpu = STATE_CPU (sd, 0);
   SIM_ADDR addr;

index d26d616..f0b4e07 100644
@@ -1,6 +1,8 @@
 #ifndef SIM_MAIN_H
 #define SIM_MAIN_H
 
+#define WITH_SCACHE_PBB 1
+
 #include "ansidecl.h"
 #include "or1k-desc.h"
 #include "sim-basics.h"

index 769f54c..83a9815 100644
@@ -25,7 +25,7 @@ This file is part of the GNU simulators.
 #include "sim-main.h"
 #include "bfd.h"
 
-const MACH *sim_machs[] =
+const SIM_MACH *sim_machs[] =
 {
 #ifdef HAVE_CPU_OR1K32BF
   & or32_mach,

index e73f37b..c3f7597 100644
@@ -25,7 +25,7 @@ This file is part of the GNU simulators.
 #include "sim-main.h"
 #include "bfd.h"
 
-const MACH *sim_machs[] =
+const SIM_MACH *sim_machs[] =
 {
 #ifdef HAVE_CPU_OR1K64BF
   & or64_mach,

index 36b4040..14e11ec 100644
@@ -10140,6 +10140,38 @@ or1k32bf_h_sys_fpcsr_dzf_set (SIM_CPU *current_cpu, USI newval)
   SET_H_SYS_FPCSR_DZF (newval);
 }
 
+/* Get the value of h-atomic-reserve.  */
+
+BI
+or1k32bf_h_atomic_reserve_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_atomic_reserve);
+}
+
+/* Set a value for h-atomic-reserve.  */
+
+void
+or1k32bf_h_atomic_reserve_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_atomic_reserve) = newval;
+}
+
+/* Get the value of h-atomic-address.  */
+
+SI
+or1k32bf_h_atomic_address_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_atomic_address);
+}
+
+/* Set a value for h-atomic-address.  */
+
+void
+or1k32bf_h_atomic_address_set (SIM_CPU *current_cpu, SI newval)
+{
+  CPU (h_atomic_address) = newval;
+}
+
 /* Record trace results for INSN.  */
 
 void

index a31a935..771fcdc 100644
@@ -53,6 +53,14 @@ typedef struct {
 do { \
 SET_H_SPR ((((index)) + (ORSI (SLLSI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))), (x));\
 ;} while (0)
+  /* atomic reserve flag */
+  BI h_atomic_reserve;
+#define GET_H_ATOMIC_RESERVE() CPU (h_atomic_reserve)
+#define SET_H_ATOMIC_RESERVE(x) (CPU (h_atomic_reserve) = (x))
+  /* atomic reserve address */
+  SI h_atomic_address;
+#define GET_H_ATOMIC_ADDRESS() CPU (h_atomic_address)
+#define SET_H_ATOMIC_ADDRESS(x) (CPU (h_atomic_address) = (x))
   } hardware;
 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
 } OR1K32BF_CPU_DATA;

@@ -4475,6 +4483,10 @@ USI or1k32bf_h_sys_fpcsr_inf_get (SIM_CPU *);
 void or1k32bf_h_sys_fpcsr_inf_set (SIM_CPU *, USI);
 USI or1k32bf_h_sys_fpcsr_dzf_get (SIM_CPU *);
 void or1k32bf_h_sys_fpcsr_dzf_set (SIM_CPU *, USI);
+BI or1k32bf_h_atomic_reserve_get (SIM_CPU *);
+void or1k32bf_h_atomic_reserve_set (SIM_CPU *, BI);
+SI or1k32bf_h_atomic_address_get (SIM_CPU *);
+void or1k32bf_h_atomic_address_set (SIM_CPU *, SI);
 
 /* These must be hand-written.  */
 extern CPUREG_FETCH_FN or1k32bf_fetch_register;

@@ -4622,6 +4634,17 @@ struct scache {
   f_resv_20_5 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
   f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 
+#define EXTRACT_IFMT_L_MSYNC_VARS \
+  UINT f_opcode; \
+  UINT f_op_25_5; \
+  UINT f_resv_20_21; \
+  unsigned int length;
+#define EXTRACT_IFMT_L_MSYNC_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_resv_20_21 = EXTRACT_LSB0_UINT (insn, 32, 20, 21); \
+
 #define EXTRACT_IFMT_L_RFE_VARS \
   UINT f_opcode; \
   UINT f_resv_25_26; \

@@ -4719,7 +4742,7 @@ struct scache {
 
 #define EXTRACT_IFMT_L_SW_VARS \
   UINT f_opcode; \
-  UINT f_r1; \
+  UINT f_r2; \
   UINT f_r3; \
   UINT f_imm16_25_5; \
   UINT f_imm16_10_11; \

@@ -4728,12 +4751,25 @@ struct scache {
 #define EXTRACT_IFMT_L_SW_CODE \
   length = 4; \
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
   f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
   f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
   f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
   f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));\
 
+#define EXTRACT_IFMT_L_SWA_VARS \
+  UINT f_opcode; \
+  UINT f_r2; \
+  UINT f_r3; \
+  INT f_simm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_L_SWA_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
+
 #define EXTRACT_IFMT_L_SLL_VARS \
   UINT f_opcode; \
   UINT f_r1; \

index cd25e89..5f5d605 100644
@@ -10156,6 +10156,38 @@ or1k64bf_h_sys_fpcsr_dzf_set (SIM_CPU *current_cpu, UDI newval)
   SET_H_SYS_FPCSR_DZF (newval);
 }
 
+/* Get the value of h-atomic-reserve.  */
+
+BI
+or1k64bf_h_atomic_reserve_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_atomic_reserve);
+}
+
+/* Set a value for h-atomic-reserve.  */
+
+void
+or1k64bf_h_atomic_reserve_set (SIM_CPU *current_cpu, BI newval)
+{
+  CPU (h_atomic_reserve) = newval;
+}
+
+/* Get the value of h-atomic-address.  */
+
+SI
+or1k64bf_h_atomic_address_get (SIM_CPU *current_cpu)
+{
+  return CPU (h_atomic_address);
+}
+
+/* Set a value for h-atomic-address.  */
+
+void
+or1k64bf_h_atomic_address_set (SIM_CPU *current_cpu, SI newval)
+{
+  CPU (h_atomic_address) = newval;
+}
+
 /* Record trace results for INSN.  */
 
 void

index 5bfbf9e..d3a93e7 100644
@@ -53,6 +53,14 @@ typedef struct {
 do { \
 SET_H_SPR ((((index)) + (ORDI (SLLDI (SPR_GROUP_SYS, 11), SPR_INDEX_SYS_GPR0))), (x));\
 ;} while (0)
+  /* atomic reserve flag */
+  BI h_atomic_reserve;
+#define GET_H_ATOMIC_RESERVE() CPU (h_atomic_reserve)
+#define SET_H_ATOMIC_RESERVE(x) (CPU (h_atomic_reserve) = (x))
+  /* atomic reserve address */
+  SI h_atomic_address;
+#define GET_H_ATOMIC_ADDRESS() CPU (h_atomic_address)
+#define SET_H_ATOMIC_ADDRESS(x) (CPU (h_atomic_address) = (x))
   } hardware;
 #define CPU_CGEN_HW(cpu) (& (cpu)->cpu_data.hardware)
 } OR1K64BF_CPU_DATA;

@@ -4482,6 +4490,10 @@ UDI or1k64bf_h_sys_fpcsr_inf_get (SIM_CPU *);
 void or1k64bf_h_sys_fpcsr_inf_set (SIM_CPU *, UDI);
 UDI or1k64bf_h_sys_fpcsr_dzf_get (SIM_CPU *);
 void or1k64bf_h_sys_fpcsr_dzf_set (SIM_CPU *, UDI);
+BI or1k64bf_h_atomic_reserve_get (SIM_CPU *);
+void or1k64bf_h_atomic_reserve_set (SIM_CPU *, BI);
+SI or1k64bf_h_atomic_address_get (SIM_CPU *);
+void or1k64bf_h_atomic_address_set (SIM_CPU *, SI);
 
 /* These must be hand-written.  */
 extern CPUREG_FETCH_FN or1k64bf_fetch_register;

@@ -4621,6 +4633,17 @@ struct scache {
   f_resv_20_5 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
   f_uimm16 = EXTRACT_LSB0_UINT (insn, 32, 15, 16); \
 
+#define EXTRACT_IFMT_L_MSYNC_VARS \
+  UINT f_opcode; \
+  UINT f_op_25_5; \
+  UINT f_resv_20_21; \
+  unsigned int length;
+#define EXTRACT_IFMT_L_MSYNC_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_op_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_resv_20_21 = EXTRACT_LSB0_UINT (insn, 32, 20, 21); \
+
 #define EXTRACT_IFMT_L_RFE_VARS \
   UINT f_opcode; \
   UINT f_resv_25_26; \

@@ -4718,7 +4741,7 @@ struct scache {
 
 #define EXTRACT_IFMT_L_SW_VARS \
   UINT f_opcode; \
-  UINT f_r1; \
+  UINT f_r2; \
   UINT f_r3; \
   UINT f_imm16_25_5; \
   UINT f_imm16_10_11; \

@@ -4727,12 +4750,25 @@ struct scache {
 #define EXTRACT_IFMT_L_SW_CODE \
   length = 4; \
   f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
-  f_r1 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
+  f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
   f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
   f_imm16_25_5 = EXTRACT_LSB0_UINT (insn, 32, 25, 5); \
   f_imm16_10_11 = EXTRACT_LSB0_UINT (insn, 32, 10, 11); \
   f_simm16_split = ((HI) (UINT) (((((f_imm16_25_5) << (11))) | (f_imm16_10_11))));\
 
+#define EXTRACT_IFMT_L_SWA_VARS \
+  UINT f_opcode; \
+  UINT f_r2; \
+  UINT f_r3; \
+  INT f_simm16; \
+  unsigned int length;
+#define EXTRACT_IFMT_L_SWA_CODE \
+  length = 4; \
+  f_opcode = EXTRACT_LSB0_UINT (insn, 32, 31, 6); \
+  f_r2 = EXTRACT_LSB0_UINT (insn, 32, 20, 5); \
+  f_r3 = EXTRACT_LSB0_UINT (insn, 32, 15, 5); \
+  f_simm16 = EXTRACT_LSB0_SINT (insn, 32, 15, 16); \
+
 #define EXTRACT_IFMT_L_SLL_VARS \
   UINT f_opcode; \
   UINT f_r1; \

index 182bc74..7e792fa 100644
@@ -33,8 +33,8 @@ This file is part of the GNU simulators.
 #include "decode.h"
 #endif
 
-extern const MACH or32_mach;
-extern const MACH or32nd_mach;
+extern const SIM_MACH or32_mach;
+extern const SIM_MACH or32nd_mach;
 
 #ifndef WANT_CPU
 /* The ARGBUF struct.  */

index 8207d8b..7a58a18 100644
@@ -33,8 +33,8 @@ This file is part of the GNU simulators.
 #include "decode64.h"
 #endif
 
-extern const MACH or64_mach;
-extern const MACH or64nd_mach;
+extern const SIM_MACH or64_mach;
+extern const SIM_MACH or64nd_mach;
 
 #ifndef WANT_CPU
 /* The ARGBUF struct.  */

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index 4fa3399..93107d2 100644
@@ -45,19 +45,19 @@ This file is part of the GNU simulators.
 #define TIMING_DATA(td) 0
 #endif
 
-static const MODEL or64_models[] =
+static const SIM_MODEL or64_models[] =
 {
   { 0 }
 };
 
-static const MODEL or64nd_models[] =
+static const SIM_MODEL or64nd_models[] =
 {
   { 0 }
 };
 
 /* The properties of this cpu's implementation.  */
 
-static const MACH_IMP_PROPERTIES or1k64bf_imp_properties =
+static const SIM_MACH_IMP_PROPERTIES or1k64bf_imp_properties =
 {
   sizeof (SIM_CPU),
 #if WITH_SCACHE

@@ -99,7 +99,7 @@ or64_init_cpu (SIM_CPU *cpu)
 #endif
 }
 
-const MACH or64_mach =
+const SIM_MACH or64_mach =
 {
   "or64", "or1k64", MACH_OR64,
   64, 64, & or64_models[0], & or1k64bf_imp_properties,

@@ -125,7 +125,7 @@ or64nd_init_cpu (SIM_CPU *cpu)
 #endif
 }
 
-const MACH or64nd_mach =
+const SIM_MACH or64nd_mach =
 {
   "or64nd", "or1k64nd", MACH_OR64ND,
   64, 64, & or64nd_models[0], & or1k64bf_imp_properties,

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index 9e1754f..7213caa 100644
@@ -4,7 +4,7 @@
 #include "symcat.h"
 
 /* GDB register numbers. */
-#define PC_REGNUM	16
+#define PC_REGNUM	33
 
 /* Misc. profile data.  */
 typedef struct {

index 98225ab..565a018 100644
@@ -9,27 +9,52 @@
 #include "sim-main.h"
 #include "symcat.h"
 #include "cgen-ops.h"
+#include "cgen-mem.h"
+#include "cpuall.h"
 
 #include <string.h>
 
-/* not sure what the point of these is */
 int XCONCAT2(WANT_CPU,_fetch_register) (sim_cpu *current_cpu, int rn, unsigned char *buf, int len)
 {
-  return -1;
+   if (rn < 32)
+    SETTWI (buf, XCONCAT2(WANT_CPU,_h_gpr_get) (current_cpu, rn));
+  else
+    switch (rn)
+      {
+      case PC_REGNUM :
+        SETTWI (buf, XCONCAT2(WANT_CPU,_h_pc_get) (current_cpu));
+        break;
+      default :
+         return 0;
+      }
+  return sizeof(WI); /* WI from arch.h */
 }
 
 int XCONCAT2(WANT_CPU,_store_register) (sim_cpu *current_cpu, int rn, unsigned char *buf, int len)
 {
-  return -1;
+  if (rn < 32)
+    XCONCAT2(WANT_CPU,_h_gpr_set) (current_cpu, rn, GETTWI (buf));
+  else
+    switch (rn)
+      {
+      case PC_REGNUM :
+        XCONCAT2(WANT_CPU,_h_pc_set) (current_cpu, GETTWI (buf));
+        break;
+      default :
+         return 0;
+      }
+  return sizeof(WI); /* WI from arch.h */
 }
 
 #ifdef WANT_CPU_OR1K32BF
 int or1k32bf_model_or1200_u_exec (sim_cpu * UNUSED current_cpu, const IDESC * UNUSED idesc, int unit_num, int referenced)
 {
+  return -1;
 }
 
 int or1k32bf_model_or1200nd_u_exec (sim_cpu * UNUSED current_cpu, const IDESC * UNUSED idesc, int unit_num, int referenced)
 {
+  return -1;
 }
 
 void or1k32bf_model_insn_before (sim_cpu * UNUSED current_cpu, int UNUSED first_p)

index 526f2e7..235d9b5 100644
@@ -17,48 +17,52 @@ sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
 #ifdef WANT_CPU_OR1K32BF
   or1k32bf_exception (current_cpu, cia, EXCEPT_ILLEGAL);
 #endif
-  
+
   return vpc;
 }
 
 void or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
 {
   SIM_DESC sd = CPU_STATE(current_cpu);
-  
-  SET_H_SYS_ESR0 (GET_H_SYS_SR ());
-  
-  SET_H_SYS_SR_DSX (current_cpu->delay_slot);
-  
-  switch (exnum) {
-  case EXCEPT_RESET:
-    break;
 
-  case EXCEPT_SYSCALL:
-    SET_H_SYS_EPCR0 (pc + 4 - (current_cpu->delay_slot ? 4 : 0));
-    break;
+  if (exnum == EXCEPT_TRAP) {
+    /* Trap, used for breakpoints, sends control back to gdb breakpoint handling */
+    sim_engine_halt (sd, current_cpu, NULL, pc, sim_stopped, SIM_SIGTRAP);
+  } else {
+
+    /* Calculate the exception program counter */
+    switch (exnum) {
+    case EXCEPT_RESET:
+      break;
+
+    case EXCEPT_SYSCALL:
+      SET_H_SYS_EPCR0 (pc + 4 - (current_cpu->delay_slot ? 4 : 0));
+      break;
+
+    case EXCEPT_BUSERR:
+    case EXCEPT_ALIGN:
+    case EXCEPT_ILLEGAL:
+      SET_H_SYS_EPCR0 (pc - (current_cpu->delay_slot ? 4 : 0));
+      break;
+
+    default:
+      sim_io_error (sd, "unexpected exception 0x%x raised at PC 0x%08x", exnum, pc);
+      break;
+    }
 
-  case EXCEPT_BUSERR:
-  case EXCEPT_ALIGN:
-  case EXCEPT_RANGE:
-  case EXCEPT_TRAP:
-  case EXCEPT_ILLEGAL:
-    SET_H_SYS_EPCR0 (pc - (current_cpu->delay_slot ? 4 : 0));
-    break;
+    /* Store the curent SR into ESR0 */
+    SET_H_SYS_ESR0 (GET_H_SYS_SR ());
 
-  default:
-    sim_io_error (sd, "unexpected exception 0x%x raised at PC 0x%08x", exnum, pc);
-    break;
-    
+    /* Indicate in SR if the failed instruction is in delay slot or not */
+    SET_H_SYS_SR_DSX (current_cpu->delay_slot);
+
+    current_cpu->next_delay_slot = 0;
+
+    /* jump program counter into handler */
+    IADDR handler_pc = (GET_H_SYS_SR_EPH() ? 0xf0000000 : 0x00000000) + (exnum << 8);
+
+    sim_engine_restart (sd, current_cpu, NULL, handler_pc);
   }
-  
-  current_cpu->next_delay_slot = 0;
-  
-  IADDR handler_pc = (GET_H_SYS_SR_EPH() ? 0xf0000000 : 0x00000000) + (exnum << 8);
-  
-  sim_engine_restart (CPU_STATE (current_cpu),
-                      current_cpu,
-                      NULL,
-                      handler_pc);
 }
 
 void or1k32bf_rfe (sim_cpu *current_cpu)

@@ -97,8 +101,8 @@ USI or1k32bf_mfspr (sim_cpu *current_cpu, USI addr)
   case SPR_ADDR(SYS,PPC):
   case SPR_ADDR(SYS,FPCSR):
   case SPR_ADDR(SYS,EPCR0):
-  case SPR_ADDR(MAC,MACHI):
   case SPR_ADDR(MAC,MACLO):
+  case SPR_ADDR(MAC,MACHI):
     break;
 
   default:

index 7213caa..2ad6f8c 100644
@@ -4,7 +4,9 @@
 #include "symcat.h"
 
 /* GDB register numbers. */
+#define PPC_REGNUM	32
 #define PC_REGNUM	33
+#define SR_REGNUM	34
 
 /* Misc. profile data.  */
 typedef struct {

index 565a018..9f50c33 100644
@@ -21,9 +21,15 @@ int XCONCAT2(WANT_CPU,_fetch_register) (sim_cpu *current_cpu, int rn, unsigned c
   else
     switch (rn)
       {
+      case PPC_REGNUM :
+        SETTWI (buf, XCONCAT2(WANT_CPU,_h_sys_ppc_get) (current_cpu));
+        break;
       case PC_REGNUM :
         SETTWI (buf, XCONCAT2(WANT_CPU,_h_pc_get) (current_cpu));
         break;
+      case SR_REGNUM :
+        SETTWI (buf, XCONCAT2(WANT_CPU,_h_sys_sr_get) (current_cpu));
+        break;
       default :
          return 0;
       }

@@ -37,9 +43,15 @@ int XCONCAT2(WANT_CPU,_store_register) (sim_cpu *current_cpu, int rn, unsigned c
   else
     switch (rn)
       {
+      case PPC_REGNUM :
+        XCONCAT2(WANT_CPU,_h_sys_ppc_set) (current_cpu, GETTWI (buf));
+        break;
       case PC_REGNUM :
         XCONCAT2(WANT_CPU,_h_pc_set) (current_cpu, GETTWI (buf));
         break;
+      case SR_REGNUM :
+        XCONCAT2(WANT_CPU,_h_sys_sr_set) (current_cpu, GETTWI (buf));
+        break;
       default :
          return 0;
       }

index d2a111f..263657f 100644
@@ -6,3 +6,24 @@ sim_engine_invalid_insn (SIM_CPU *current_cpu, IADDR cia, SEM_PC vpc)
   /* TODO */
   abort();
 }
+
+void or1k32bf_exception (sim_cpu *current_cpu, USI pc, USI exnum)
+{
+  /* TODO */
+  abort();
+}
+
+void or1k32bf_rfe (sim_cpu *current_cpu)
+{
+  abort();
+}
+
+USI or1k32bf_mfspr (sim_cpu *current_cpu, USI addr)
+{
+  abort();
+}
+
+void or1k32bf_mtspr (sim_cpu *current_cpu, USI addr, USI val)
+{
+  abort();
+}