net: stmmac: enable tx queue 0 for gmac4 IPs synthesized with multiple TX queues

PATCH Applied Niklas Cassel 3 participants 9 messages Nov 24, 2016 – Dec 1, 2016

Subsystems (4)

Networking Network drivers Arm STM32 stmmac Ethernet driver

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Niklas Cassel

author

2016-11-24 14:36 UTC #0 lore raw

PATCH 1/1 net: stmmac: enable tx queue 0 for gmac4 IPs synthesized with multiple TX queues

From: Niklas Cassel <[email protected]>

The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W.

Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1.

The driver does still not utilize more than one tx queue in the IP.

Signed-off-by Niklas Cassel <[email protected]>

---
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h     |  3 +++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 12 +++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)

drivers/net/ethernet/stmicro/stmmac/dwmac4.h +3 -0

index 6f4f5ce25114..3e8d4fefa5e0 100644
@@ -155,8 +155,11 @@ enum power_event {
 #define MTL_CHAN_RX_DEBUG(x)		(MTL_CHANX_BASE_ADDR(x) + 0x38)
 
 #define MTL_OP_MODE_RSF			BIT(5)
+#define MTL_OP_MODE_TXQEN		BIT(3)
 #define MTL_OP_MODE_TSF			BIT(1)
 
+#define MTL_OP_MODE_TQS_MASK		GENMASK(24, 16)
+
 #define MTL_OP_MODE_TTC_MASK		0x70
 #define MTL_OP_MODE_TTC_SHIFT		4

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +11 -1

index 116151cd6a95..577316de6ba8 100644
@@ -213,7 +213,17 @@ static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode,
 		else
 			mtl_tx_op |= MTL_OP_MODE_TTC_512;
 	}
-
+	/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
+	 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
+	 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
+	 * with reset values: TXQEN off, TQS 256 bytes.
+	 *
+	 * Write the bits in both cases, since it will have no effect when RO.
+	 * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might
+	 * be RO, however, writing the whole TQS field will result in a value
+	 * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1.
+	 */
+	mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK;
 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
 
 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));

Signature · 1 line

2.1.4

Alexandre Torgue

2016-11-24 18:12 UTC #1 lore raw

Hi Niklas,

Quoted 43 lines · Niklas Cassel

From: Niklas Cassel <[email protected]>
The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by Niklas Cassel <[email protected]>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h     |  3 +++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 12 +++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)
drivers/net/ethernet/stmicro/stmmac/dwmac4.h +3 -0
index 6f4f5ce25114..3e8d4fefa5e0 100644
@@ -155,8 +155,11 @@ enum power_event {
 #define MTL_CHAN_RX_DEBUG(x)		(MTL_CHANX_BASE_ADDR(x) + 0x38)
 
 #define MTL_OP_MODE_RSF			BIT(5)
+#define MTL_OP_MODE_TXQEN		BIT(3)
 #define MTL_OP_MODE_TSF			BIT(1)
 
+#define MTL_OP_MODE_TQS_MASK		GENMASK(24, 16)
+
 #define MTL_OP_MODE_TTC_MASK		0x70
 #define MTL_OP_MODE_TTC_SHIFT		4
 
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +1 -1
index 116151cd6a95..577316de6ba8 100644
@@ -213,7 +213,17 @@ static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode,
 		else
 			mtl_tx_op |= MTL_OP_MODE_TTC_512;
 	}
-
+	/* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, · line 226

Quoted 10 lines

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +10 -0

+	 * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
+	 * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
+	 * with reset values: TXQEN off, TQS 256 bytes.
+	 *
+	 * Write the bits in both cases, since it will have no effect when RO.
+	 * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might
+	 * be RO, however, writing the whole TQS field will result in a value
+	 * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1.
+	 */
+	mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK;

Your patch sounds good. Just one question:

In synopsys databook I use, I see that MTL_OP_MODE_TXQEN for channel 2 can take several values "disabled / enabled / Enabled in AV mode":

Transmit Queue Enable
This field is used to enable/disable the transmit queue 1. 00 R/W ■ 2'b00 - Not enabled
■ 2'b01 - Enable in AV mode (Reserved when Enable Audio Video Bridging is not selected while configuring the core)
■ 2'b10 - Enabled
■ 2'b11 - Reserved

Do you plan to manage av mode in a future patch ?

Regards
Alex

Quoted 4 lines

drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +0 -0

 	writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
 
 	mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));

Niklas Cassel

author

2016-11-25 12:10 UTC #2 lore raw

Quoted 1 line · Alexandre Torgue

Hi Niklas,

Hello Alexandre

Quoted 68 lines · Niklas Cassel

Quoted 43 lines
From: Niklas Cassel <[email protected]>
The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by Niklas Cassel <[email protected]>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h     |  3 +++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 12 +++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)
drivers/net/ethernet/stmicro/stmmac/dwmac4.h +3 -0
index 6f4f5ce25114..3e8d4fefa5e0 100644
@@ -155,8 +155,11 @@ enum power_event {
 #define MTL_CHAN_RX_DEBUG(x)        (MTL_CHANX_BASE_ADDR(x) + 0x38)
 
 #define MTL_OP_MODE_RSF            BIT(5)
+#define MTL_OP_MODE_TXQEN        BIT(3)
 #define MTL_OP_MODE_TSF            BIT(1)
 
+#define MTL_OP_MODE_TQS_MASK        GENMASK(24, 16)
+
 #define MTL_OP_MODE_TTC_MASK        0x70
 #define MTL_OP_MODE_TTC_SHIFT        4
 
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +1 -1
index 116151cd6a95..577316de6ba8 100644
@@ -213,7 +213,17 @@ static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode,
         else
             mtl_tx_op |= MTL_OP_MODE_TTC_512;
     }
-
+    /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, · line 226
Quoted 10 lines
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +10 -0
+     * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
+     * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
+     * with reset values: TXQEN off, TQS 256 bytes.
+     *
+     * Write the bits in both cases, since it will have no effect when RO.
+     * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might
+     * be RO, however, writing the whole TQS field will result in a value
+     * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1.
+     */
+    mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK;
Your patch sounds good. Just one question:
In synopsys databook I use, I see that MTL_OP_MODE_TXQEN for channel 2 can take several values "disabled / enabled / Enabled in AV mode":
Transmit Queue Enable
This field is used to enable/disable the transmit queue 1. 00 R/W ■ 2'b00 - Not enabled
■ 2'b01 - Enable in AV mode (Reserved when Enable Audio Video Bridging is not selected while configuring the core)
■ 2'b10 - Enabled
■ 2'b11 - Reserved

Quoted 1 line

Do you plan to manage av mode in a future patch ?

We are not planning on using the AV mode.
We will probably not use TXQ1 at all.

I noticed that the MAC_HW_Feature2 Register actually has a TXQCNT field. It is currently saved in priv->dma_cap.number_tx_channel.
If you prefer, I could do a patch V2 where we only set the bits if priv->dma_cap.number_tx_channel > 1

However, I don't think the current patch is too bad either, since the bits are RO when number_tx_channel == 1.

Quoted 8 lines

Regards
Alex
Quoted 4 lines
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +0 -0
     writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
 
     mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));

Niklas Cassel

author

2016-11-25 12:14 UTC #3 lore raw

Quoted 70 lines · Niklas Cassel

Quoted 1 line · Alexandre Torgue
Hi Niklas,
Hello Alexandre
Quoted 66 lines · Niklas Cassel
Quoted 43 lines
From: Niklas Cassel <[email protected]>
The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by Niklas Cassel <[email protected]>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h     |  3 +++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 12 +++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)
drivers/net/ethernet/stmicro/stmmac/dwmac4.h +3 -0
index 6f4f5ce25114..3e8d4fefa5e0 100644
@@ -155,8 +155,11 @@ enum power_event {
 #define MTL_CHAN_RX_DEBUG(x)        (MTL_CHANX_BASE_ADDR(x) + 0x38)
 
 #define MTL_OP_MODE_RSF            BIT(5)
+#define MTL_OP_MODE_TXQEN        BIT(3)
 #define MTL_OP_MODE_TSF            BIT(1)
 
+#define MTL_OP_MODE_TQS_MASK        GENMASK(24, 16)
+
 #define MTL_OP_MODE_TTC_MASK        0x70
 #define MTL_OP_MODE_TTC_SHIFT        4
 
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +1 -1
index 116151cd6a95..577316de6ba8 100644
@@ -213,7 +213,17 @@ static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode,
         else
             mtl_tx_op |= MTL_OP_MODE_TTC_512;
     }
-
+    /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, · line 226
Quoted 10 lines
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +10 -0
+     * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
+     * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
+     * with reset values: TXQEN off, TQS 256 bytes.
+     *
+     * Write the bits in both cases, since it will have no effect when RO.
+     * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might
+     * be RO, however, writing the whole TQS field will result in a value
+     * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1.
+     */
+    mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK;
Your patch sounds good. Just one question:
In synopsys databook I use, I see that MTL_OP_MODE_TXQEN for channel 2 can take several values "disabled / enabled / Enabled in AV mode":
Transmit Queue Enable
This field is used to enable/disable the transmit queue 1. 00 R/W ■ 2'b00 - Not enabled
■ 2'b01 - Enable in AV mode (Reserved when Enable Audio Video Bridging is not selected while configuring the core)
■ 2'b10 - Enabled
■ 2'b11 - Reserved

Quoted 8 lines

Quoted 1 line
Do you plan to manage av mode in a future patch ?
We are not planning on using the AV mode.
We will probably not use TXQ1 at all.
I noticed that the MAC_HW_Feature2 Register actually has a TXQCNT field. It is currently saved in priv->dma_cap.number_tx_channel.
If you prefer, I could do a patch V2 where we only set the bits if priv->dma_cap.number_tx_channel > 1

Oh, sorry, that was number of tx _channels_,
not number of tx _queues_.

However, we could add a number_tx_queue to struct dma_features, if you would prefer that.

Quoted 12 lines

However, I don't think the current patch is too bad either, since the bits are RO when number_tx_channel == 1.
Quoted 7 lines
Regards
Alex
Quoted 4 lines
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +0 -0
     writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
 
     mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));

Alexandre Torgue

2016-11-25 15:41 UTC #4 lore raw

Hi Niklas

Quoted 80 lines · Niklas Cassel

Quoted 70 lines · Niklas Cassel
Quoted 1 line · Alexandre Torgue
Hi Niklas,
Hello Alexandre
Quoted 66 lines · Niklas Cassel
Quoted 43 lines
From: Niklas Cassel <[email protected]>
The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by Niklas Cassel <[email protected]>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h     |  3 +++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 12 +++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)
drivers/net/ethernet/stmicro/stmmac/dwmac4.h +3 -0
index 6f4f5ce25114..3e8d4fefa5e0 100644
@@ -155,8 +155,11 @@ enum power_event {
 #define MTL_CHAN_RX_DEBUG(x)        (MTL_CHANX_BASE_ADDR(x) + 0x38)
 
 #define MTL_OP_MODE_RSF            BIT(5)
+#define MTL_OP_MODE_TXQEN        BIT(3)
 #define MTL_OP_MODE_TSF            BIT(1)
 
+#define MTL_OP_MODE_TQS_MASK        GENMASK(24, 16)
+
 #define MTL_OP_MODE_TTC_MASK        0x70
 #define MTL_OP_MODE_TTC_SHIFT        4
 
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +1 -1
index 116151cd6a95..577316de6ba8 100644
@@ -213,7 +213,17 @@ static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode,
         else
             mtl_tx_op |= MTL_OP_MODE_TTC_512;
     }
-
+    /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, · line 226
Quoted 10 lines
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +10 -0
+     * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
+     * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
+     * with reset values: TXQEN off, TQS 256 bytes.
+     *
+     * Write the bits in both cases, since it will have no effect when RO.
+     * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might
+     * be RO, however, writing the whole TQS field will result in a value
+     * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1.
+     */
+    mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK;
Your patch sounds good. Just one question:
In synopsys databook I use, I see that MTL_OP_MODE_TXQEN for channel 2 can take several values "disabled / enabled / Enabled in AV mode":
Transmit Queue Enable
This field is used to enable/disable the transmit queue 1. 00 R/W ■ 2'b00 - Not enabled
■ 2'b01 - Enable in AV mode (Reserved when Enable Audio Video Bridging is not selected while configuring the core)
■ 2'b10 - Enabled
■ 2'b11 - Reserved
Quoted 8 lines
Quoted 1 line
Do you plan to manage av mode in a future patch ?
We are not planning on using the AV mode.
We will probably not use TXQ1 at all.
I noticed that the MAC_HW_Feature2 Register actually has a TXQCNT field. It is currently saved in priv->dma_cap.number_tx_channel.
If you prefer, I could do a patch V2 where we only set the bits if priv->dma_cap.number_tx_channel > 1

Quoted 5 lines

Oh, sorry, that was number of tx _channels_,
not number of tx _queues_.
However, we could add a number_tx_queue to struct dma_features, if you would prefer that.

I agree your patch is good. It will work even if we use several tx channels. We will see in the future for AV mode.

regards
alex

Quoted 14 lines

Quoted 13 lines
However, I don't think the current patch is too bad either, since the bits are RO when number_tx_channel == 1.
Quoted 7 lines
Regards
Alex
Quoted 4 lines
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +0 -0
     writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
 
     mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));

Niklas Cassel

author

2016-11-25 16:49 UTC #5 lore raw

Quoted 83 lines · Alexandre Torgue

Hi Niklas
Quoted 80 lines · Niklas Cassel
Quoted 78 lines · Niklas Cassel
Quoted 1 line · Alexandre Torgue
Hi Niklas,
Hello Alexandre
Quoted 66 lines · Niklas Cassel
Quoted 43 lines
From: Niklas Cassel <[email protected]>
The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by Niklas Cassel <[email protected]>
---
 drivers/net/ethernet/stmicro/stmmac/dwmac4.h     |  3 +++
 drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c | 12 +++++++++++-
 2 files changed, 14 insertions(+), 1 deletion(-)
drivers/net/ethernet/stmicro/stmmac/dwmac4.h +3 -0
index 6f4f5ce25114..3e8d4fefa5e0 100644
@@ -155,8 +155,11 @@ enum power_event {
 #define MTL_CHAN_RX_DEBUG(x)        (MTL_CHANX_BASE_ADDR(x) + 0x38)
 
 #define MTL_OP_MODE_RSF            BIT(5)
+#define MTL_OP_MODE_TXQEN        BIT(3)
 #define MTL_OP_MODE_TSF            BIT(1)
 
+#define MTL_OP_MODE_TQS_MASK        GENMASK(24, 16)
+
 #define MTL_OP_MODE_TTC_MASK        0x70
 #define MTL_OP_MODE_TTC_SHIFT        4
 
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +1 -1
index 116151cd6a95..577316de6ba8 100644
@@ -213,7 +213,17 @@ static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode,
         else
             mtl_tx_op |= MTL_OP_MODE_TTC_512;
     }
-
+    /* For an IP with DWC_EQOS_NUM_TXQ == 1, the fields TXQEN and TQS are RO
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c static void dwmac4_dma_chan_op_mode(void __iomem *ioaddr, int txmode, · line 226
Quoted 10 lines
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +10 -0
+     * with reset values: TXQEN on, TQS == DWC_EQOS_TXFIFO_SIZE.
+     * For an IP with DWC_EQOS_NUM_TXQ > 1, the fields TXQEN and TQS are R/W
+     * with reset values: TXQEN off, TQS 256 bytes.
+     *
+     * Write the bits in both cases, since it will have no effect when RO.
+     * For DWC_EQOS_NUM_TXQ > 1, the top bits in MTL_OP_MODE_TQS_MASK might
+     * be RO, however, writing the whole TQS field will result in a value
+     * equal to DWC_EQOS_TXFIFO_SIZE, just like for DWC_EQOS_NUM_TXQ == 1.
+     */
+    mtl_tx_op |= MTL_OP_MODE_TXQEN | MTL_OP_MODE_TQS_MASK;
Your patch sounds good. Just one question:
In synopsys databook I use, I see that MTL_OP_MODE_TXQEN for channel 2 can take several values "disabled / enabled / Enabled in AV mode":
Transmit Queue Enable
This field is used to enable/disable the transmit queue 1. 00 R/W ■ 2'b00 - Not enabled
■ 2'b01 - Enable in AV mode (Reserved when Enable Audio Video Bridging is not selected while configuring the core)
■ 2'b10 - Enabled
■ 2'b11 - Reserved
Quoted 1 line
Do you plan to manage av mode in a future patch ?
We are not planning on using the AV mode.
We will probably not use TXQ1 at all.
I noticed that the MAC_HW_Feature2 Register actually has a TXQCNT field. It is currently saved in priv->dma_cap.number_tx_channel.
If you prefer, I could do a patch V2 where we only set the bits if priv->dma_cap.number_tx_channel > 1

Quoted 7 lines

Quoted 5 lines
Oh, sorry, that was number of tx _channels_,
not number of tx _queues_.
However, we could add a number_tx_queue to struct dma_features, if you would prefer that.
I agree your patch is good. It will work even if we use several tx channels. We will see in the future for AV mode.

Excellent :)

Can I convert that into an Acked-by?

Quoted 18 lines

regards
alex
Quoted 14 lines
Quoted 13 lines
However, I don't think the current patch is too bad either, since the bits are RO when number_tx_channel == 1.
Quoted 7 lines
Regards
Alex
Quoted 4 lines
drivers/net/ethernet/stmicro/stmmac/dwmac4_dma.c +0 -0
     writel(mtl_tx_op, ioaddr +  MTL_CHAN_TX_OP_MODE(channel));
 
     mtl_rx_op = readl(ioaddr + MTL_CHAN_RX_OP_MODE(channel));

David Miller

maintainer

2016-11-28 16:39 UTC #6 lore raw

In reply to Niklas Cassel

From: Niklas Cassel <[email protected]>
Date: Thu, 24 Nov 2016 15:36:33 +0100

Quoted 6 lines

From: Niklas Cassel <[email protected]>
The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W.

Quoted 6 lines

Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by Niklas Cassel <[email protected]>

Alexandre, we are still waiting for your implicit/explicit ACK on this change.

Thank you.

Alexandre Torgue

2016-12-01 17:21 UTC #7 lore raw

Hi David and Niklas,

Quoted 12 lines · David Miller

From: Niklas Cassel <[email protected]>
Date: Thu, 24 Nov 2016 15:36:33 +0100
Quoted 9 lines
From: Niklas Cassel <[email protected]>
The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W.
Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1.

Quoted 6 lines

Quoted 3 lines
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by Niklas Cassel <[email protected]>
Alexandre, we are still waiting for your implicit/explicit ACK on this change.

Yes you could add my Acked-by but it is already merged. My fault. Sorry for my late answer :(

Quoted 3 lines

Thank you.

David Miller

maintainer Applied

2016-11-30 00:11 UTC #8 lore raw

In reply to Niklas Cassel

From: Niklas Cassel <[email protected]>
Date: Thu, 24 Nov 2016 15:36:33 +0100

Quoted 6 lines

From: Niklas Cassel <[email protected]>
The dwmac4 IP can synthesized with 1-8 number of tx queues. On an IP synthesized with DWC_EQOS_NUM_TXQ > 1, all txqueues are disabled by default. For these IPs, the bitfield TXQEN is R/W.

Quoted 6 lines

Always enable tx queue 0. The write will have no effect on IPs synthesized with DWC_EQOS_NUM_TXQ == 1.
The driver does still not utilize more than one tx queue in the IP.
Signed-off-by Niklas Cassel <[email protected]>

Applied to net-next, thanks.