powerpc/mm: Fix lazy icache flush on pre-POWER5

PATCH Applied Benjamin Herrenschmidt 3 participants 3 messages Nov 29, 2016 – Nov 30, 2016 PowerPC

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Benjamin Herrenschmidt

author

2016-11-29 02:13 UTC #0 lore raw

PATCH 1/1 powerpc/mm: Fix lazy icache flush on pre-POWER5

On 64-bit CPUs with no-execute support and non-snooping icache, such as 970 or POWER4, we have a software mechanism to ensure coherency of the cache (using exec faults when needed).

This was broken due to a logic inversion when that code was rewritten from assembly to C.

Signed-off-by Benjamin Herrenschmidt <[email protected]>

Fixes 91f1da99792a1d133df94c4753510305353064a1

Fixes 89ff725051d177556b23d80f2a30f880a657a6c1

Fixes a43c0eb8364c022725df586e91dd753633374d66

arch/powerpc/mm/hash64_4k.c +1 -1

index 42c702b..6fa450c 100644
@@ -55,7 +55,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
 	 */
 	rflags = htab_convert_pte_flags(new_pte);
 
-	if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&
+	if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
 	    !cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
 		rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);

arch/powerpc/mm/hash64_64k.c +2 -2

index 3bbbea0..1a68cb1 100644
@@ -87,7 +87,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
 	subpg_pte = new_pte & ~subpg_prot;
 	rflags = htab_convert_pte_flags(subpg_pte);
 
-	if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&
+	if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
 	    !cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
 
 		/*

@@ -258,7 +258,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,
 
 	rflags = htab_convert_pte_flags(new_pte);
 
-	if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&
+	if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
 	    !cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
 		rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);

Aneesh Kumar K.V

Reviewed-by on v1 1/1

2016-11-29 02:55 UTC #1 lore raw

Quoted 6 lines · Benjamin Herrenschmidt

On 64-bit CPUs with no-execute support and non-snooping icache, such as 970 or POWER4, we have a software mechanism to ensure coherency of the cache (using exec faults when needed).
This was broken due to a logic inversion when that code was rewritten from assembly to C.

The asm code for reference is

BEGIN_FTR_SECTION

       mr      r4,r30
       mr      r5,r7
       bl      hash_page_do_lazy_icache

END_FTR_SECTION(CPU_FTR_NOEXECUTE|CPU_FTR_COHERENT_ICACHE, CPU_FTR_NOEXECUTE)

Reviewed-by Aneesh Kumar K.V <[email protected]>

Quoted 40 lines

Signed-off-by Benjamin Herrenschmidt <[email protected]>

Fixes 91f1da99792a1d133df94c4753510305353064a1

Fixes 89ff725051d177556b23d80f2a30f880a657a6c1

Fixes a43c0eb8364c022725df586e91dd753633374d66

arch/powerpc/mm/hash64_4k.c +1 -1

index 42c702b..6fa450c 100644
@@ -55,7 +55,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
 	 */
 	rflags = htab_convert_pte_flags(new_pte);
 
-	if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&
+	if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
 	    !cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
 		rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);

arch/powerpc/mm/hash64_64k.c +2 -2

index 3bbbea0..1a68cb1 100644
@@ -87,7 +87,7 @@ int __hash_page_4K(unsigned long ea, unsigned long access, unsigned long vsid,
 	subpg_pte = new_pte & ~subpg_prot;
 	rflags = htab_convert_pte_flags(subpg_pte);
 
-	if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&
+	if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
 	    !cpu_has_feature(CPU_FTR_COHERENT_ICACHE)) {
 
 		/*

@@ -258,7 +258,7 @@ int __hash_page_64K(unsigned long ea, unsigned long access,
 
 	rflags = htab_convert_pte_flags(new_pte);
 
-	if (!cpu_has_feature(CPU_FTR_NOEXECUTE) &&
+	if (cpu_has_feature(CPU_FTR_NOEXECUTE) &&
 	    !cpu_has_feature(CPU_FTR_COHERENT_ICACHE))
 		rflags = hash_page_do_lazy_icache(rflags, __pte(old_pte), trap);

Michael Ellerman

Applied

2016-11-30 12:27 UTC #2 lore raw

In reply to Benjamin Herrenschmidt

Quoted 4 lines · Benjamin Herrenschmidt

On 64-bit CPUs with no-execute support and non-snooping icache, such as 970 or POWER4, we have a software mechanism to ensure coherency of the cache (using exec faults when needed).

Quoted 8 lines

This was broken due to a logic inversion when that code was rewritten from assembly to C.
Signed-off-by Benjamin Herrenschmidt <[email protected]>
Fixes 91f1da99792a1d133df94c4753510305353064a1
Fixes 89ff725051d177556b23d80f2a30f880a657a6c1
Fixes a43c0eb8364c022725df586e91dd753633374d66
Reviewed-by Aneesh Kumar K.V <[email protected]>

Applied to powerpc fixes, thanks.

https://git.kernel.org/powerpc/c/dd7b2f035ec41a409f7a7cec7aabc0

cheers