aspeed/g5: Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board
Subsystems (4)
PATCH v3 1/6 aspeed/g5: Device Tree for ast2500, copied from openbmc/linux (include file), plus minimal device tree configuration for ast2500 eval board
aspeed-g5.dtsi include file is copied from
https://github.com/openbmc/linux/blob/c5682cb/arch/arm/boot/dts/aspeed-g5.dtsi
Signed-off-by Maxim Sloyko <[email protected]>
Reviewed-by Simon Glass <[email protected]>
--- arch/arm/dts/Makefile | 2 + arch/arm/dts/aspeed-g5-evb.dts | 28 + arch/arm/dts/aspeed-g5.dtsi | 1278 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 1308 insertions(+) create mode 100644 arch/arm/dts/aspeed-g5-evb.dts create mode 100644 arch/arm/dts/aspeed-g5.dtsi
arch/arm/dts/Makefile +2 -0
@@ -262,6 +262,8 @@ dtb-$(CONFIG_SOC_KEYSTONE) += k2hk-evm.dtb \ k2e-evm.dtb \ k2g-evm.dtb +dtb-$(CONFIG_TARGET_AST_G5) += aspeed-g5-evb.dtb + targets += $(dtb-y) # Add any required device tree compiler flags here
arch/arm/dts/aspeed-g5-evb.dts new file +28 -0
@@ -0,0 +1,28 @@ +/dts-v1/; + +#include "aspeed-g5.dtsi" + +/ { + memory { + device_type = "memory"; + reg = <0x80000000 0x20000000>; + }; + + aliases { + i2c1 = &i2c0; + i2c4 = &i2c3; + i2c8 = &i2c7; + }; +}; + +&i2c0 { + status = "okay"; +}; + +&i2c3 { + status = "okay"; +}; + +&i2c7 { + status = "okay"; +};
arch/arm/dts/aspeed-g5.dtsi new file +1278 -0
1,278 lines not on this page · raw message
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2.8.0.rc3.226.g39d4020
PATCH v3 2/6 aspeed: Fix FUC/FUN typo in SCU
Change FUC to FUN in SCU registers naming, which was a typo that go out of hand
Signed-off-by Maxim Sloyko <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes for v1:
Patch split into two parts with this part only fixing the FUC->FUN typo. --- arch/arm/include/asm/arch-aspeed/regs-scu.h | 64 ++++++++++++++--------------- arch/arm/mach-aspeed/ast-scu.c | 2 +- 2 files changed, 33 insertions(+), 33 deletions(-)
arch/arm/include/asm/arch-aspeed/regs-scu.h +32 -32
@@ -830,49 +830,49 @@/* AST_SCU_FUN_PIN_CTRL5 0x90 - Multi-function Pin Control#5 */ #define SCU_FUN_PIN_SPICS1 (0x1 << 31)#define SCU_FUN_PIN_LPC_PLUS (0x1 << 30) -#define SCU_FUC_PIN_USB20_HOST (0x1 << 29) -#define SCU_FUC_PIN_USB11_PORT4 (0x1 << 28) -#define SCU_FUC_PIN_I2C14 (0x1 << 27) -#define SCU_FUC_PIN_I2C13 (0x1 << 26) -#define SCU_FUC_PIN_I2C12 (0x1 << 25) -#define SCU_FUC_PIN_I2C11 (0x1 << 24) -#define SCU_FUC_PIN_I2C10 (0x1 << 23) -#define SCU_FUC_PIN_I2C9 (0x1 << 22) -#define SCU_FUC_PIN_I2C8 (0x1 << 21) -#define SCU_FUC_PIN_I2C7 (0x1 << 20) -#define SCU_FUC_PIN_I2C6 (0x1 << 19) -#define SCU_FUC_PIN_I2C5 (0x1 << 18) -#define SCU_FUC_PIN_I2C4 (0x1 << 17) -#define SCU_FUC_PIN_I2C3 (0x1 << 16) -#define SCU_FUC_PIN_MII2_RX_DWN_DIS (0x1 << 15) -#define SCU_FUC_PIN_MII2_TX_DWN_DIS (0x1 << 14) -#define SCU_FUC_PIN_MII1_RX_DWN_DIS (0x1 << 13) -#define SCU_FUC_PIN_MII1_TX_DWN_DIS (0x1 << 12) - -#define SCU_FUC_PIN_MII2_TX_DRIV (x) (x << 10) -#define SCU_FUC_PIN_MII2_TX_DRIV_MASK (0x3 << 10) -#define SCU_FUC_PIN_MII1_TX_DRIV (x) (x << 8) -#define SCU_FUC_PIN_MII1_TX_DRIV_MASK (0x3 << 8) +#define SCU_FUN_PIN_USB20_HOST (0x1 << 29) +#define SCU_FUN_PIN_USB11_PORT4 (0x1 << 28) +#define SCU_FUN_PIN_I2C14 (0x1 << 27) +#define SCU_FUN_PIN_I2C13 (0x1 << 26) +#define SCU_FUN_PIN_I2C12 (0x1 << 25) +#define SCU_FUN_PIN_I2C11 (0x1 << 24) +#define SCU_FUN_PIN_I2C10 (0x1 << 23) +#define SCU_FUN_PIN_I2C9 (0x1 << 22) +#define SCU_FUN_PIN_I2C8 (0x1 << 21) +#define SCU_FUN_PIN_I2C7 (0x1 << 20) +#define SCU_FUN_PIN_I2C6 (0x1 << 19) +#define SCU_FUN_PIN_I2C5 (0x1 << 18) +#define SCU_FUN_PIN_I2C4 (0x1 << 17) +#define SCU_FUN_PIN_I2C3 (0x1 << 16) +#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15) +#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14) +#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13) +#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12) + +#define SCU_FUN_PIN_MII2_TX_DRIV (x) (x << 10) +#define SCU_FUN_PIN_MII2_TX_DRIV_MASK (0x3 << 10) +#define SCU_FUN_PIN_MII1_TX_DRIV (x) (x << 8) +#define SCU_FUN_PIN_MII1_TX_DRIV_MASK (0x3 << 8)#define MII_NORMAL_DRIV 0x0#define MII_HIGH_DRIV 0x2 -#define SCU_FUC_PIN_UART6 (0x1 << 7) -#define SCU_FUC_PIN_ROM_16BIT (0x1 << 6) -#define SCU_FUC_PIN_DIGI_V_OUT (x) (x) -#define SCU_FUC_PIN_DIGI_V_OUT_MASK (0x3) +#define SCU_FUN_PIN_UART6 (0x1 << 7) +#define SCU_FUN_PIN_ROM_16BIT (0x1 << 6) +#define SCU_FUN_PIN_DIGI_V_OUT (x) (x) +#define SCU_FUN_PIN_DIGI_V_OUT_MASK (0x3)#define VIDEO_DISABLE 0x0#define VIDEO_12BITS 0x1#define VIDEO_24BITS 0x2//#define VIDEO_DISABLE 0x3 -#define SCU_FUC_PIN_USB11_PORT2 (0x1 << 3) -#define SCU_FUC_PIN_SD1_8BIT (0x1 << 3) +#define SCU_FUN_PIN_USB11_PORT2 (0x1 << 3) +#define SCU_FUN_PIN_SD1_8BIT (0x1 << 3) -#define SCU_FUC_PIN_MAC1_MDIO (0x1 << 2) -#define SCU_FUC_PIN_SD2 (0x1 << 1) -#define SCU_FUC_PIN_SD1 (0x1 << 0) +#define SCU_FUN_PIN_MAC1_MDIO (0x1 << 2) +#define SCU_FUN_PIN_SD2 (0x1 << 1) +#define SCU_FUN_PIN_SD1 (0x1 << 0)/* AST_SCU_FUN_PIN_CTRL6 0x94 - Multi-function Pin Control#6*/
arch/arm/mach-aspeed/ast-scu.c +1 -1
@@ -394,7 +394,7 @@ void ast_scu_multi_func_eth(u8 num) AST_SCU_FUN_PIN_CTRL1);ast_scu_write (ast_scu_read (AST_SCU_FUN_PIN_CTRL5 ) | -SCU_FUC_PIN_MAC1_MDIO , +SCU_FUN_PIN_MAC1_MDIO ,AST_SCU_FUN_PIN_CTRL5 );break ;
--
2.8.0.rc3.226.g39d4020
PATCH v3 3/6 aspeed/scu: Add definitions needed to configure pins for I2C
In reply to Maxim SloykoAdd missing definitions for configuring I2C pins
Signed-off-by Maxim Sloyko <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes for v1:
Split patch into two with this part adding definitions.
Changes for v2:
Dropped redundant parens.
--- arch/arm/include/asm/arch-aspeed/regs-scu.h | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/include/asm/arch-aspeed/regs-scu.h +9 -0
@@ -844,11 +844,15 @@#define SCU_FUN_PIN_I2C5 (0x1 << 18)#define SCU_FUN_PIN_I2C4 (0x1 << 17)#define SCU_FUN_PIN_I2C3 (0x1 << 16) +#define SCU_FUN_PIN_I2C (n) (0x1 << (16 + (n) - 3))#define SCU_FUN_PIN_MII2_RX_DWN_DIS (0x1 << 15)#define SCU_FUN_PIN_MII2_TX_DWN_DIS (0x1 << 14)#define SCU_FUN_PIN_MII1_RX_DWN_DIS (0x1 << 13)#define SCU_FUN_PIN_MII1_TX_DWN_DIS (0x1 << 12) +#define SCU_I2C_MIN_BUS_NUM 1 +#define SCU_I2C_MAX_BUS_NUM 14 +#define SCU_FUN_PIN_MII2_TX_DRIV (x) (x << 10)#define SCU_FUN_PIN_MII2_TX_DRIV_MASK (0x3 << 10)#define SCU_FUN_PIN_MII1_TX_DRIV (x) (x << 8)
@@ -914,6 +918,11 @@#define SCU_FUN_PIN_ROMA4 (0x1 << 18)#define SCU_FUN_PIN_ROMA3 (0x1 << 17)#define SCU_FUN_PIN_ROMA2 (0x1 << 16) +/* AST2500 only */ +#define SCU_FUN_PIN_SDA2 (0x1 << 15) +#define SCU_FUN_PIN_SCL2 (0x1 << 14) +#define SCU_FUN_PIN_SDA1 (0x1 << 13) +#define SCU_FUN_PIN_SCL1 (0x1 << 12)/* AST_SCU_FUN_PIN_CTRL9 0xA8 - Multi-function Pin Control#9 */ #define SCU_FUN_PIN_ROMA21 (0x1 << 3)
--
2.8.0.rc3.226.g39d4020
PATCH v3 4/6 aspeed: Add function to calculate APB Clock frequency
In reply to Maxim SloykoThis is needed by I2C driver.
Signed-off-by Maxim Sloyko <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes for v1:
Add function comment.
--- arch/arm/include/asm/arch-aspeed/ast_scu.h | 4 ++++ arch/arm/mach-aspeed/ast-scu.c | 13 +++++++++++++ 2 files changed, 17 insertions(+)
arch/arm/include/asm/arch-aspeed/ast_scu.h +4 -0
@@ -38,6 +38,10 @@ extern void ast_scu_get_who_init_dram(void);extern u32 ast_get_clk_source (void );extern u32 ast_get_h_pll_clk (void );extern u32 ast_get_ahbclk (void ); +/* +* Return the frequency of APB clock +*/ +extern u32 ast_get_apbclk (void );extern u32 ast_scu_get_vga_memsize (void );
arch/arm/mach-aspeed/ast-scu.c +13 -0
@@ -318,6 +318,19 @@ u32 ast_get_ahbclk(void)#endif /* AST_SOC_G5 */ +u32 ast_get_apbclk (void ) +{ +ulong h_pll =ast_get_h_pll_clk (); + +/* +* The formula for converting the bit pattern to divisor is +* (4 + 4 * DIV), according to datasheet +*/ +ulong apb_div =4 +4 *SCU_GET_PCLK_DIV (ast_scu_read (AST_SCU_CLK_SEL )); +return h_pll / apb_div; +} + +void ast_scu_show_system_info (void ) {
--
2.8.0.rc3.226.g39d4020
PATCH v3 5/6 aspeed: Add function to configure pins for I2C devices
In reply to Maxim SloykoIn the absence of pinmux driver, I2C driver will be configuring pins directly.
Signed-off-by Maxim Sloyko <[email protected]>
Reviewed-by Simon Glass <[email protected]>
--- arch/arm/include/asm/arch-aspeed/ast_scu.h | 6 ++++++ arch/arm/mach-aspeed/ast-scu.c | 28 ++++++++++++++++++++++++++++ 2 files changed, 34 insertions(+)
arch/arm/include/asm/arch-aspeed/ast_scu.h +6 -0
@@ -49,4 +49,10 @@ extern void ast_scu_init_eth(u8 num);extern void ast_scu_multi_func_eth (u8 num);extern void ast_scu_multi_func_romcs (u8 num); +/* +* Enable I2C controller and pins for a particular device. +* Device numbering starts at 1 +*/ +extern void ast_scu_enable_i2c (u8 num); +#endif
arch/arm/mach-aspeed/ast-scu.c +28 -0
@@ -509,3 +509,31 @@ void ast_scu_get_who_init_dram(void)break ; } } + +void ast_scu_enable_i2c (u8 bus_num) +{ +if (bus_num >SCU_I2C_MAX_BUS_NUM ) { +debug ("%s: bus_num is out of range, must be [%d - %d]\n" , + __func__,SCU_I2C_MIN_BUS_NUM ,SCU_I2C_MAX_BUS_NUM ); +return ; + } + +if (bus_num ==0 ) { +/* Enable I2C Controllers */ +clrbits_le32 (AST_SCU_BASE +AST_SCU_RESET ,SCU_RESET_I2C ); + }else if (bus_num >=3 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL5 , +SCU_FUN_PIN_I2C (bus_num)); +/* In earlier versions of the SoC these pins are always assigned to +* respective I2C buses and require no configuration. +*/ +#ifdef AST_SOC_G5 + }else if (bus_num ==1 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA1 |SCU_FUN_PIN_SCL1 ); + }else if (bus_num ==2 ) { +setbits_le32 (AST_SCU_BASE +AST_SCU_FUN_PIN_CTRL8 , +SCU_FUN_PIN_SDA2 |SCU_FUN_PIN_SCL2 ); +#endif + } +}
--
2.8.0.rc3.226.g39d4020
PATCH v3 6/6 aspeed: I2C driver
In reply to Maxim SloykoThe driver is very limited: only single master mode is supported and only byte-by-byte synchronous reads and writes are supported, no Pool Buffers or DMA.
Signed-off-by Maxim Sloyko <[email protected]>
Reviewed-by Simon Glass <[email protected]>
---
Changes for v1:
- Style fixes: blank lines, line formatting, dropped inline from definitions
- More documentation for CONFIG_SYS_I2C_AST
- Use standard ETIMEOUT error
- Documented struct ast_i2c
- Documented get_clk_reg_val function
- Rewritten get_clk_reg_val to use register masks and shifts defined in ast_i2c.h
- Dropped AST_ prefix from AST_I2CD_ defines
Changes for v2:
- More style fixes for things missed in v1
- Return error from ast_i2c_xfer on deblock failure
--- drivers/i2c/Kconfig | 9 ++ drivers/i2c/Makefile | 1 + drivers/i2c/ast_i2c.c | 335 ++++++++++++++++++++++++++++++++++++++++++++++++++ drivers/i2c/ast_i2c.h | 130 ++++++++++++++++++++ 4 files changed, 475 insertions(+) create mode 100644 drivers/i2c/ast_i2c.c create mode 100644 drivers/i2c/ast_i2c.h
drivers/i2c/Kconfig +9 -0
@@ -90,6 +90,15 @@ config SYS_I2C_DW_ENABLE_STATUS_UNSUPPORTED enable status register. This config option can be enabled in such cases. +config SYS_I2C_AST + bool "Aspeed I2C Controller" + depends on DM_I2C + help + Say yes here to select Aspeed I2C Host Controller. The driver + supports AST2500 and AST2400 controllers, but is very limited. + Only single master mode is supported and only byte-by-byte + synchronous reads and writes are supported, no Pool Buffers or DMA. + config SYS_I2C_INTEL bool "Intel I2C/SMBUS driver" depends on DM_I2C
drivers/i2c/Makefile +1 -0
@@ -16,6 +16,7 @@ obj-$(CONFIG_PCA9564_I2C) += pca9564_i2c.o obj-$(CONFIG_TSI108_I2C) += tsi108_i2c.o obj-$(CONFIG_SH_SH7734_I2C) += sh_sh7734_i2c.o obj-$(CONFIG_SYS_I2C) += i2c_core.o +obj-$(CONFIG_SYS_I2C_AST) += ast_i2c.o obj-$(CONFIG_SYS_I2C_CADENCE) += i2c-cdns.o obj-$(CONFIG_SYS_I2C_DAVINCI) += davinci_i2c.o obj-$(CONFIG_SYS_I2C_DW) += designware_i2c.o
drivers/i2c/ast_i2c.c new file +335 -0
335 lines not on this page · raw message
drivers/i2c/ast_i2c.h new file +130 -0
130 lines not on this page · raw message
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2.8.0.rc3.226.g39d4020