iommu/intel-iommu: fix pasid table size encoding
PATCH v2 1/1 iommu/intel-iommu: fix pasid table size encoding
Different encodings are used to represent supported PASID bits and number of PASID table entries.
The current code assigns ecap_pss directly to extended context table entry PTS which is wrong and could result in writing non-zero bits to the reserved fields. IOMMU fault reason 11 will be reported when reserved bits are nonzero. This patch converts ecap_pss to extend context entry pts encoding based on VT-d spec. Chapter 9.4 as follows:
- number of PASID bits = ecap_pss + 1
- number of PASID table entries = 2^(pts + 5)
Software assigned limit of pasid_max value is also respected to match the allocation limitation of PASID table.
--- drivers/iommu/intel-iommu.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)
drivers/iommu/intel-iommu.c +22 -1
@@ -5173,6 +5173,25 @@ static void intel_iommu_remove_device(struct device *dev) }#ifdef CONFIG_INTEL_IOMMU_SVM +#define MAX_NR_PASID_BITS (20) +static inline unsigned long intel_iommu_get_pts (struct intel_iommu *iommu) +{ +/* +* Convert ecap_pss to extend context entry pts encoding, also +* respect the soft pasid_max value set by the iommu. +* - number of PASID bits = ecap_pss + 1 +* - number of PASID table entries = 2^(pts + 5) +* Therefore, pts = ecap_pss - 4 +* e.g. KBL ecap_pss = 0x13, PASID has 20 bits, pts = 15 +*/ +if (ecap_pss (iommu->ecap) <5 ) +return 0 ; + +/* pasid_max is encoded as actual number of entries not the bits */ +return find_first_bit ((unsigned long *)&iommu->pasid_max, +MAX_NR_PASID_BITS ) -5 ; +} +int intel_iommu_enable_pasid (struct intel_iommu *iommu,struct intel_svm_dev *sdev) {struct device_domain_info *info;
@@ -5205,7 +5224,9 @@ int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdif (!(ctx_lo &CONTEXT_PASIDE )) { context[1 ].hi = (u64 )virt_to_phys (iommu->pasid_state_table); - context[1 ].lo = (u64 )virt_to_phys (iommu->pasid_table) |ecap_pss (iommu->ecap); + context[1 ].lo = (u64 )virt_to_phys (iommu->pasid_table) | +intel_iommu_get_pts (iommu); +wmb ();/* CONTEXT_TT_MULTI_LEVEL and CONTEXT_TT_DEV_IOTLB are both * extended to permit requests-with-PASID if the PASIDE bit
Signature · 1 line
2.7.4
Hi Joerg/David,
Just wondering if you have any more comments?
Thanks,
Jacob
Quoted 65 lines · On Tue, 6 Dec 2016 10:14:23 -0800 Jacob Pan <[email protected]>…
Different encodings are used to represent supported PASID bits and number of PASID table entries.
The current code assignsecap_pssdirectly to extended context table entry PTS which is wrong and could result in writing non-zero bits to the reserved fields. IOMMU fault reason 11 will be reported when reserved bits are nonzero. This patch convertsecap_pssto extend context entry pts encoding based on VT-d spec. Chapter 9.4 as follows:
- number of PASID bits =ecap_pss+ 1
- number of PASID table entries = 2^(pts + 5)
Software assigned limit ofpasid_maxvalue is also respected to match the allocation limitation of PASID table.cc Mika Kuoppala <[email protected]>cc Ashok Raj <[email protected]>Signed-off-by Jacob Pan <[email protected]>--- drivers/iommu/intel-iommu.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)drivers/iommu/intel-iommu.c +4
-0@@ -5173,6 +5173,25 @@ static void intel_iommu_remove_device(struct device *dev) }#ifdef CONFIG_INTEL_IOMMU_SVM +#define MAX_NR_PASID_BITS (20) +static inline unsigned long intel_iommu_get_pts (struct intel_iommu *iommu) +{ +/* +* Convert ecap_pss to extend context entry pts encoding, also
drivers/iommu/intel-iommu.c +10
-0+* respect the soft pasid_max value set by the iommu. +* - number of PASID bits = ecap_pss + 1 +* - number of PASID table entries = 2^(pts + 5) +* Therefore, pts = ecap_pss - 4 +* e.g. KBL ecap_pss = 0x13, PASID has 20 bits, pts = 15 +*/ +if (ecap_pss (iommu->ecap) <5 ) +return 0 ; + +/* pasid_max is encoded as actual number of entries not the bits */
drivers/iommu/intel-iommu.c +4
-0+return find_first_bit ((unsigned long *)&iommu->pasid_max, +MAX_NR_PASID_BITS ) -5 ; +} + int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct
intel_svm_dev*sdev) {drivers/iommu/intel-iommu.c +1
-1struct device_domain_info *info;@@ -5205,7 +5224,9 @@ int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdif (!(ctx_lo &CONTEXT_PASIDE )) { context[1 ].hi = (u64 )virt_to_phys (iommu->pasid_state_table); - context[1 ].lo = (u64 )virt_to_phys (iommu->pasid_table) |ecap_pss (iommu->ecap); + context[1].lo =(u64)virt_to_phys(iommu->pasid_table) |
drivers/iommu/intel-iommu.c +2
-0+intel_iommu_get_pts (iommu); +wmb ();/* CONTEXT_TT_MULTI_LEVEL and CONTEXT_TT_DEV_IOTLB
Quoted 3 lines
are both
* extended to permit requests-with-PASID if the
PASIDE bit
[Jacob Pan]
Quoted 13 lines · Jacob Pan
Different encodings are used to represent supported PASID bits and number of PASID table entries.
The current code assignsecap_pssdirectly to extended context table entry PTS which is wrong and could result in writing non-zero bits to the reserved fields. IOMMU fault reason 11 will be reported when reserved bits are nonzero. This patch convertsecap_pssto extend context entry pts encoding based on VT-d spec. Chapter 9.4 as follows:
- number of PASID bits =ecap_pss+ 1
- number of PASID table entries = 2^(pts + 5)
Software assigned limit ofpasid_maxvalue is also respected to match the allocation limitation of PASID table.
Quoted 3 lines
cc Mika Kuoppala <[email protected]>cc Ashok Raj <[email protected]>Signed-off-by Jacob Pan <[email protected]>
Quoted 47 lines
--- drivers/iommu/intel-iommu.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)drivers/iommu/intel-iommu.c +22
-1@@ -5173,6 +5173,25 @@ static void intel_iommu_remove_device(struct device *dev) }#ifdef CONFIG_INTEL_IOMMU_SVM +#define MAX_NR_PASID_BITS (20) +static inline unsigned long intel_iommu_get_pts (struct intel_iommu *iommu) +{ +/* +* Convert ecap_pss to extend context entry pts encoding, also +* respect the soft pasid_max value set by the iommu. +* - number of PASID bits = ecap_pss + 1 +* - number of PASID table entries = 2^(pts + 5) +* Therefore, pts = ecap_pss - 4 +* e.g. KBL ecap_pss = 0x13, PASID has 20 bits, pts = 15 +*/ +if (ecap_pss (iommu->ecap) <5 ) +return 0 ; + +/* pasid_max is encoded as actual number of entries not the bits */ +return find_first_bit ((unsigned long *)&iommu->pasid_max, +MAX_NR_PASID_BITS ) -5 ; +} +int intel_iommu_enable_pasid (struct intel_iommu *iommu,struct intel_svm_dev *sdev) {struct device_domain_info *info;@@ -5205,7 +5224,9 @@ int intel_iommu_enable_pasid(struct intel_iommu *iommu, struct intel_svm_dev *sdif (!(ctx_lo &CONTEXT_PASIDE )) { context[1 ].hi = (u64 )virt_to_phys (iommu->pasid_state_table); - context[1 ].lo = (u64 )virt_to_phys (iommu->pasid_table) |ecap_pss (iommu->ecap); + context[1 ].lo = (u64 )virt_to_phys (iommu->pasid_table) | +intel_iommu_get_pts (iommu); +wmb ();/* CONTEXT_TT_MULTI_LEVEL and CONTEXT_TT_DEV_IOTLB are both * extended to permit requests-with-PASID if the PASIDE bit Signature · 1 line
2.7.4
Hi David/Joerg
Haven't heard about it from David yet, but can we queue this for 4.10? If you have any questions/concerns please let us know.
Cheers,
Ashok
Quoted 6 lines · Mika Kuoppala
Quoted 4 lines
cc Mika Kuoppala <mika.kuoppala-VuQAYsv1563Yd54FQh9/[email protected]>cc Ashok Raj <[email protected]>Tested-by Mika Kuoppala <[email protected]>
Quoted 5 lines
Quoted 5 lines
--- drivers/iommu/intel-iommu.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)
Joerg Roedel
maintainerQuoted 2 lines · Ashok
Haven't heard about it from David yet, but can we queue this for 4.10? If you have any questions/concerns please let us know.
I'll queue the fix when rc1 is out.
Joerg
Quoted 2 lines · Jacob Pan
drivers/iommu/intel-iommu.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)
Applied to the fixes branch, thanks.