arm: socfpga: arria10: Added config option build for SPL

PATCH New Chee Tien Fong 3 participants 27 messages Dec 6, 2016 – Dec 19, 2016

Subsystems (4)

Arm (32-bit) Arm sub-architectures Library code Arm/socfpga architecture

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Chee Tien Fong

author

2016-12-06 07:52 UTC #0 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

From: Tien Fong Chee <[email protected]>

These changes to ensure Arria10 SPL build success.

Signed-off-by Tien Fong Chee <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Tien Fong <[email protected]>

---
 arch/arm/Kconfig |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

arch/arm/Kconfig +4 -4

index 220bb19..05ce8b8 100644
@@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select CPU_V7
-	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+	select SUPPORT_SPL
 	select OF_CONTROL
-	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+	select SPL_OF_CONTROL
 	select DM
-	select DM_SPI_FLASH
-	select DM_SPI
+	select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
+	select DM_SPI if !TARGET_SOCFPGA_ARRIA10
 
 config TARGET_CM_T43
 	bool "Support cm_t43"

Signature · 1 line

1.7.7.4

Chee Tien Fong

author

2016-12-06 07:52 UTC #1 lore raw

PATCH 3/10 arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

From: Tien Fong Chee <[email protected]>

Enhanced defconfig file for Arria10 to enable SPL build and supporting device tree build for SDMMC.

Signed-off-by Tien Fong Chee <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Tien Fong <[email protected]>

---
 arch/arm/mach-socfpga/include/mach/boot0.h |   17 +++++++++++++++++
 configs/socfpga_arria10_defconfig          |   18 +++++++++++++-----
 2 files changed, 30 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h

arch/arm/mach-socfpga/include/mach/boot0.h new file +17 -0

new file mode 100644
index 0000000..8052a0b
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+#if (defined(CONFIG_ARCH_SOCFPGA) && defined(CONFIG_SPL_BUILD))
+/* BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK	\
+	.fill 12, 4, 0xdeadbeef
+#else
+#define ARM_SOC_BOOT0_HOOK
+#endif
+#endif /* __BOOT0_H */

configs/socfpga_arria10_defconfig +13 -5

index 422261b..755bb66 100644
@@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
 CONFIG_TARGET_SOCFPGA_ARRIA10=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_DWAPB_GPIO=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y

Signature · 1 line

1.7.7.4

Marek Vasut

2016-12-06 12:48 UTC #2 lore raw

PATCH 3/10 arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

Quoted 25 lines · Chee Tien Fong

From: Tien Fong Chee <[email protected]>
Enhanced defconfig file for Arria10 to enable SPL build and supporting device tree build for SDMMC.
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 arch/arm/mach-socfpga/include/mach/boot0.h |   17 +++++++++++++++++
 configs/socfpga_arria10_defconfig          |   18 +++++++++++++-----
 2 files changed, 30 insertions(+), 5 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h
arch/arm/mach-socfpga/include/mach/boot0.h new file +3 -0
new file mode 100644
index 0000000..8052a0b
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *

arch/arm/mach-socfpga/include/mach/boot0.h line 13

Quoted 10 lines

arch/arm/mach-socfpga/include/mach/boot0.h new file +10 -0

+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+#if (defined(CONFIG_ARCH_SOCFPGA) && defined(CONFIG_SPL_BUILD))
+/* BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK	\
+	.fill 12, 4, 0xdeadbeef

Seems unrelated and something that was fixed in mainline already.

Quoted 37 lines

arch/arm/mach-socfpga/include/mach/boot0.h new file +4 -0

+#else
+#define ARM_SOC_BOOT0_HOOK
+#endif
+#endif /* __BOOT0_H */

configs/socfpga_arria10_defconfig +13 -5

index 422261b..755bb66 100644
@@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
 CONFIG_TARGET_SOCFPGA_ARRIA10=y
 CONFIG_DM_GPIO=y
 CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
 # CONFIG_CMD_IMLS is not set
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPIO=y
 CONFIG_DWAPB_GPIO=y
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
 CONFIG_SYS_NS16550=y
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
 CONFIG_DM_MMC=y
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-07 10:36 UTC #3 lore raw

PATCH 3/10 arm: socfpga: arria10: Enhanced socfpga_arria10_defconfig to support SPL

Quoted 34 lines · Marek Vasut

Quoted 33 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
Enhanced defconfig file for Arria10 to enable SPL build and supporting
device tree build for SDMMC.
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
?arch/arm/mach-socfpga/include/mach/boot0.h |???17
+++++++++++++++++
?configs/socfpga_arria10_defconfig??????????|???18 +++++++++++++--- --
?2 files changed, 30 insertions(+), 5 deletions(-) ?create mode 100644 arch/arm/mach-socfpga/include/mach/boot0.h
arch/arm/mach-socfpga/include/mach/boot0.h new file +6 -0
new file mode 100644
index 0000000..8052a0b
@@ -0,0 +1,17 @@
+/*
+ * Copyright (C) 2016, Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+

Quoted 9 lines

arch/arm/mach-socfpga/include/mach/boot0.h line 13
Quoted 7 lines
arch/arm/mach-socfpga/include/mach/boot0.h new file +7 -0
+#ifndef __BOOT0_H
+#define __BOOT0_H
+
+#if (defined(CONFIG_ARCH_SOCFPGA) && defined(CONFIG_SPL_BUILD))
+/* BOOT0 header information */
+#define ARM_SOC_BOOT0_HOOK	\
+	.fill 12, 4, 0xdeadbeef
Seems unrelated and something that was fixed in mainline already.

Okay. We need the fixed sync from mainline, otherwise spl would not working.?

Quoted 40 lines

Quoted 39 lines
arch/arm/mach-socfpga/include/mach/boot0.h new file +4 -0
+#else
+#define ARM_SOC_BOOT0_HOOK
+#endif
+#endif /* __BOOT0_H */
configs/socfpga_arria10_defconfig +0 -0
index 422261b..755bb66 100644
@@ -3,14 +3,22 @@ CONFIG_ARCH_SOCFPGA=y
?CONFIG_TARGET_SOCFPGA_ARRIA10=y
?CONFIG_DM_GPIO=y
?CONFIG_TARGET_SOCFPGA_ARRIA10_SOCDK=y
configs/socfpga_arria10_defconfig +2 -1
-CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk"
+CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
+CONFIG_IDENT_STRING="socfpga_arria10"
?# CONFIG_CMD_IMLS is not set
?# CONFIG_CMD_FLASH is not set
?CONFIG_CMD_GPIO=y
?CONFIG_DWAPB_GPIO=y
configs/socfpga_arria10_defconfig +0 -2
-CONFIG_DM_ETH=y
-CONFIG_ETH_DESIGNWARE=y
?CONFIG_SYS_NS16550=y
configs/socfpga_arria10_defconfig +0 -2
-CONFIG_CADENCE_QSPI=y
-CONFIG_DESIGNWARE_SPI=y
?CONFIG_DM_MMC=y
configs/socfpga_arria10_defconfig +11 -0
+CONFIG_SYS_MALLOC_F_LEN=0x2000
+CONFIG_CMD_MMC=y
+CONFIG_USE_TINY_PRINTF=y
+CONFIG_SPL=y
+CONFIG_SPL_DM=y
+CONFIG_SPL_SIMPLE_BUS=y
+CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_MMC_SUPPORT=y
+CONFIG_SPL_SERIAL_SUPPORT=y
+CONFIG_SPL_OF_LIBFDT=y
+CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y

Chee Tien Fong

author

2016-12-06 07:52 UTC #4 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

In reply to Chee Tien Fong

From: Tien Fong Chee <[email protected]>

These compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization.

Signed-off-by Tien Fong Chee <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Tien Fong <[email protected]>

---
 include/fdtdec.h |    8 ++++++++
 lib/fdtdec.c     |    2 ++
 2 files changed, 10 insertions(+), 0 deletions(-)

include/fdtdec.h +8 -0

index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */
 	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
 	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock initialization */
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* pinctrl-single */
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/* Arria10 hps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10 lwhps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/* Arria10 fpga2hps bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/* Arria10 fpga2SDRAM0 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/* Arria10 fpga2SDRAM1 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/* Arria10 fpga2SDRAM2 bridge */
 
 	COMPAT_COUNT,
 };

lib/fdtdec.c +2 -0

index 4defb90..09a1db4 100644
@@ -66,6 +66,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
 	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)

Signature · 1 line

1.7.7.4

Marek Vasut

2016-12-06 12:49 UTC #5 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 21 lines · Chee Tien Fong

From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and pin mux drivers to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 include/fdtdec.h |    8 ++++++++
 lib/fdtdec.c     |    2 ++
 2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-down params */

include/fdtdec.h enum fdt_compat_id { · line 165

Quoted 10 lines

include/fdtdec.h +8 -0

 	COMPAT_INTEL_IVYBRIDGE_FSP,	/* Intel Ivy Bridge FSP */
 	COMPAT_SUNXI_NAND,		/* SUNXI NAND controller */
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock initialization */
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* pinctrl-single */
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/* Arria10 hps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10 lwhps2fpga bridge */
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/* Arria10 fpga2hps bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/* Arria10 fpga2SDRAM0 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/* Arria10 fpga2SDRAM1 bridge */
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/* Arria10 fpga2SDRAM2 bridge */

Is all of this needed ? You're only adding two entries in the FDTDEC below.

Quoted 17 lines

include/fdtdec.h +0 -0

 	COMPAT_COUNT,
 };

lib/fdtdec.c +2 -0

index 4defb90..09a1db4 100644
@@ -66,6 +66,8 @@ static const char * const compat_names[COMPAT_COUNT] = {
 	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
 	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
 };
 
 const char *fdtdec_get_compatible(enum fdt_compat_id id)

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-07 10:48 UTC #6 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 39 lines · Marek Vasut

Quoted 38 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
?include/fdtdec.h |????8 ++++++++ ?lib/fdtdec.c?????|????2 ++
?2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
? COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP memory-
down params */
? COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP
*/
? COMPAT_SUNXI_NAND, /* SUNXI NAND controller
*/
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
initialization */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* pinctrl-
single */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/* Arria10
hps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
lwhps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/* Arria10
fpga2hps bridge */

Quoted 9 lines

Quoted 6 lines
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/* Arria10
fpga2SDRAM0 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/* Arria10
fpga2SDRAM1 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/* Arria10
fpga2SDRAM2 bridge */
Is all of this needed ? You're only adding two entries in the FDTDEC below.

This is to avoid compilation error, we have some functions ported from our internal branch, which using above COMPAT macro. Soon, in upcoming patches, we will need those functions and more entries will be added into FDTDEC below.

Quoted 20 lines

Quoted 19 lines

?
? COMPAT_COUNT,
?};

lib/fdtdec.c +2 -0

index 4defb90..09a1db4 100644
@@ -66,6 +66,8 @@ static const char * const
 compat_names[COMPAT_COUNT] = {
 ?	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 ?	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
 ?	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
 ?};

?
?const char *fdtdec_get_compatible(enum fdt_compat_id id)

Marek Vasut

2016-12-07 13:54 UTC #7 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 49 lines · Tien Fong

Quoted 39 lines · Marek Vasut
Quoted 38 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 include/fdtdec.h |    8 ++++++++
 lib/fdtdec.c     |    2 ++
 2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP memory-
down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge FSP
*/
COMPAT_SUNXI_NAND, /* SUNXI NAND controller
*/
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
initialization */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/* pinctrl-
single */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/* Arria10
hps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
lwhps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/* Arria10
fpga2hps bridge */
Quoted 9 lines
Quoted 6 lines
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/* Arria10
fpga2SDRAM0 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/* Arria10
fpga2SDRAM1 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/* Arria10
fpga2SDRAM2 bridge */
Is all of this needed ? You're only adding two entries in the FDTDEC below.

Quoted 4 lines

This is to avoid compilation error, we have some functions ported from our internal branch, which using above COMPAT macro. Soon, in upcoming patches, we will need those functions and more entries will be added into FDTDEC below.

You can add the compat strings when you really need them. Still, with DM, you shouldn't even need them AFAIK.

Quoted 19 lines

include/fdtdec.h +0 -0

 	COMPAT_COUNT,
 };

lib/fdtdec.c +2 -0

index 4defb90..09a1db4 100644
@@ -66,6 +66,8 @@ static const char * const
 compat_names[COMPAT_COUNT] = {
 	COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-mdp"),
 	COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
 	COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
+	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-single"),
 };

const char *fdtdec_get_compatible(enum fdt_compat_id id)

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-19 04:10 UTC #8 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 71 lines · Marek Vasut

Quoted 63 lines · Tien Fong
Quoted 52 lines · Marek Vasut
Quoted 50 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
?include/fdtdec.h |????8 ++++++++ ?lib/fdtdec.c?????|????2 ++
?2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
? COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP
memory-
down params */
? COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge
FSP
*/
? COMPAT_SUNXI_NAND, /* SUNXI NAND
controller
*/
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
initialization */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/*
pinctrl-
single */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/*
Arria10
hps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
lwhps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/*
Arria10
fpga2hps bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/*
Arria10
fpga2SDRAM0 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/*
Quoted 9 lines
Quoted 5 lines
Arria10
fpga2SDRAM1 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/*
Arria10
fpga2SDRAM2 bridge */
Is all of this needed ? You're only adding two entries in the FDTDEC
below.
Quoted 7 lines
This is to avoid compilation error, we have some functions ported from
our internal branch, which using above COMPAT macro. Soon, in upcoming
patches, we will need those functions and more entries will be added
into FDTDEC below.

Quoted 3 lines

You can add the compat strings when you really need them. Still, with DM, you shouldn't even need them AFAIK.

We have some drivers in these series of patches contain some COMPAT strings, without these compact strings, the compilation would fail due to error compact string is not defined. I think having compact string would giving us flexbility to put our nodes where we want without worrying to break our existing codes?

Quoted 25 lines

Quoted 24 lines
Quoted 24 lines
Quoted 24 lines
?
? COMPAT_COUNT,
?};
lib/fdtdec.c +0 -0
index 4defb90..09a1db4 100644
@@ -66,6 +66,8 @@ static const char * const
 compat_names[COMPAT_COUNT] = {
? COMPAT(INTEL_BAYTRAIL_FSP_MDP, "intel,baytrail-fsp-
mdp"),
? COMPAT(INTEL_IVYBRIDGE_FSP, "intel,ivybridge-fsp"),
? COMPAT(COMPAT_SUNXI_NAND, "allwinner,sun4i-a10-nand"),
lib/fdtdec.c +2 -0
+	COMPAT(ALTERA_SOCFPGA_CLK, "altr,clk-mgr"),
+	COMPAT(ALTERA_SOCFPGA_PINCTRL_SINGLE, "pinctrl-
single"),
?};
?
?const char *fdtdec_get_compatible(enum fdt_compat_id id)

Marek Vasut

2016-12-19 07:55 UTC #9 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 72 lines · Tien Fong

Quoted 71 lines · Marek Vasut
Quoted 70 lines · Tien Fong
Quoted 52 lines · Marek Vasut
Quoted 50 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and pin mux drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 include/fdtdec.h |    8 ++++++++
 lib/fdtdec.c     |    2 ++
 2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP
memory-
down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy Bridge
FSP
*/
COMPAT_SUNXI_NAND, /* SUNXI NAND
controller
*/
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
initialization */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/*
pinctrl-
single */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/*
Arria10
hps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
lwhps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/*
Arria10
fpga2hps bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/*
Arria10
fpga2SDRAM0 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/*
Quoted 9 lines
Quoted 5 lines
Arria10
fpga2SDRAM1 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/*
Arria10
fpga2SDRAM2 bridge */
Is all of this needed ? You're only adding two entries in the FDTDEC
below.
This is to avoid compilation error, we have some functions ported from
our internal branch, which using above COMPAT macro. Soon, in upcoming
patches, we will need those functions and more entries will be added
into FDTDEC below.

Quoted 6 lines

Quoted 3 lines
You can add the compat strings when you really need them. Still, with DM, you shouldn't even need them AFAIK.
We have some drivers in these series of patches contain some COMPAT strings, without these compact strings, the compilation would fail due to error compact string is not defined.

All of them ? Mind you, with DM you should not need to add those at all.

Quoted 3 lines

I think having compact string
would giving us flexbility to put our nodes where we want without worrying to break our existing codes?

Which existing codes ?

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-19 08:40 UTC #10 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 89 lines · Marek Vasut

Quoted 80 lines · Tien Fong
Quoted 78 lines · Marek Vasut
Quoted 76 lines · Tien Fong
Quoted 56 lines · Marek Vasut
Quoted 53 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and pin mux
drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
?include/fdtdec.h |????8 ++++++++ ?lib/fdtdec.c?????|????2 ++
?2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
? COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel FSP
memory-
down params */
? COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy
Bridge
FSP
*/
? COMPAT_SUNXI_NAND, /* SUNXI NAND
controller
*/
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
initialization */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/*
pinctrl-
single */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/*
Arria10
hps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
lwhps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/*
Arria10
fpga2hps bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/*
Arria10
fpga2SDRAM0 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/*
Quoted 9 lines
Quoted 5 lines
Arria10
fpga2SDRAM1 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/*
Arria10
fpga2SDRAM2 bridge */
Is all of this needed ? You're only adding two entries in the FDTDEC
below.
This is to avoid compilation error, we have some functions ported
from
our internal branch, which using above COMPAT macro. Soon, in upcoming
patches, we will need those functions and more entries will be added
into FDTDEC below.
Quoted 8 lines
Quoted 4 lines
You can add the compat strings when you really need them. Still, with
DM, you shouldn't even need them AFAIK.
We have some drivers in these series of patches contain some COMPAT strings, without these compact strings, the compilation would fail due
to error compact string is not defined.

Quoted 9 lines

All of them ? Mind you, with DM you should not need to add those at all.
Quoted 4 lines
I think having compact string
would giving us flexbility to put our nodes where we want without worrying to break our existing codes?
Which existing codes ?

let say we have version A, we found the node based on COMPAT STRING. One day, we move the node to somewhere else in version B, we still can find them based on COMPAT STRING without checking the node path. What do you think?

Marek Vasut

2016-12-19 08:43 UTC #11 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 97 lines · Tien Fong

Quoted 96 lines · Marek Vasut
Quoted 80 lines · Tien Fong
Quoted 78 lines · Marek Vasut
Quoted 76 lines · Tien Fong
Quoted 56 lines · Marek Vasut
Quoted 53 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and pin mux
drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 include/fdtdec.h |    8 ++++++++
 lib/fdtdec.c     |    2 ++
 2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel FSP
memory-
down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel Ivy
Bridge
FSP
*/
COMPAT_SUNXI_NAND, /* SUNXI NAND
controller
*/
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA Clock
initialization */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/*
pinctrl-
single */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		/*
Arria10
hps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/* Arria10
lwhps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		/*
Arria10
fpga2hps bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/*
Arria10
fpga2SDRAM0 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/*
Quoted 9 lines
Quoted 5 lines
Arria10
fpga2SDRAM1 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/*
Arria10
fpga2SDRAM2 bridge */
Is all of this needed ? You're only adding two entries in the FDTDEC
below.
This is to avoid compilation error, we have some functions ported
from
our internal branch, which using above COMPAT macro. Soon, in upcoming
patches, we will need those functions and more entries will be added
into FDTDEC below.
Quoted 8 lines
Quoted 4 lines
You can add the compat strings when you really need them. Still, with
DM, you shouldn't even need them AFAIK.
We have some drivers in these series of patches contain some COMPAT strings, without these compact strings, the compilation would fail due
to error compact string is not defined.
All of them ? Mind you, with DM you should not need to add those at all.
Quoted 4 lines
I think having compact string
would giving us flexbility to put our nodes where we want without worrying to break our existing codes?

Quoted 6 lines

Quoted 2 lines
Which existing codes ?
let say we have version A, we found the node based on COMPAT STRING. One day, we move the node to somewhere else in version B, we still can find them based on COMPAT STRING without checking the node path. What do you think?

I do not understand what you're trying to tell me here. The DM core will walk the DT and bind drivers according to compat strings, so if you ever move a node, it will still be bound.

Also, you didn't answer my question -- which existing codes do you refer to. Or is this some hypothetical concern ?

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-19 08:54 UTC #12 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 136 lines · Marek Vasut

Quoted 128 lines · Tien Fong
Quoted 120 lines · Marek Vasut
Quoted 106 lines · Tien Fong
Quoted 98 lines · Marek Vasut
Quoted 85 lines · Tien Fong
Quoted 72 lines · Marek Vasut
Quoted 68 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and pin
mux
drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <[email protected]
Quoted 1 line
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
?include/fdtdec.h |????8 ++++++++ ?lib/fdtdec.c?????|????2 ++
?2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
? COMPAT_INTEL_BAYTRAIL_FSP_MDP, /* Intel
FSP
memory-
down params */
? COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel
Ivy
Bridge
FSP
*/
? COMPAT_SUNXI_NAND, /* SUNXI
NAND
controller
*/
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA
Clock
initialization */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/
*
pinctrl-
single */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		
/*
Arria10
hps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/*
Arria10
lwhps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		
/*
Arria10
fpga2hps bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/
*
Arria10
fpga2SDRAM0 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/
*
Arria10
fpga2SDRAM1 bridge */
Quoted 9 lines
Quoted 4 lines
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/
*
Arria10
fpga2SDRAM2 bridge */
Is all of this needed ? You're only adding two entries in the
FDTDEC
below.
Quoted 10 lines
This is to avoid compilation error, we have some functions ported
from
our internal branch, which using above COMPAT macro. Soon, in
upcoming
patches, we will need those functions and more entries will be
added
into FDTDEC below.
Quoted 5 lines
You can add the compat strings when you really need them. Still,
with
DM, you shouldn't even need them AFAIK.
Quoted 6 lines
We have some drivers in these series of patches contain some COMPAT
strings, without these compact strings, the compilation would fail
due
to error compact string is not defined.
All of them ? Mind you, with DM you should not need to add those at
all.
Quoted 2 lines
Quoted 6 lines
Quoted 4 lines
I think having compact string
would giving us flexbility to put our nodes where we want without
worrying to break our existing codes?
Which existing codes ?
Quoted 7 lines
let say we have version A, we found the node based on COMPAT STRING.
One day, we move the node to somewhere else in version B, we still can
find them based on COMPAT STRING without checking the node path. What
do you think?

Quoted 9 lines

I do not understand what you're trying to tell me here. The DM core will
walk the DT and bind drivers according to compat strings, so if you ever move a node, it will still be bound.
Also, you didn't answer my question -- which existing codes do you refer
to. Or is this some hypothetical concern ?

existing codes is hypothetical example, when someone move the node somewhere, the DM still can find the node based on COMPAT STRING. Without COMPAT STRING, we need to change the driver code for the node path right?

Marek Vasut

2016-12-19 10:04 UTC #13 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 142 lines · Tien Fong

Quoted 141 lines · Marek Vasut
Quoted 128 lines · Tien Fong
Quoted 120 lines · Marek Vasut
Quoted 106 lines · Tien Fong
Quoted 98 lines · Marek Vasut
Quoted 85 lines · Tien Fong
Quoted 72 lines · Marek Vasut
Quoted 68 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and pin
mux
drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <[email protected]
Quoted 1 line
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 include/fdtdec.h |    8 ++++++++
 lib/fdtdec.c     |    2 ++
 2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/* Intel
FSP
memory-
down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /* Intel
Ivy
Bridge
FSP
*/
COMPAT_SUNXI_NAND, /* SUNXI
NAND
controller
*/
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_CLK,	/* SoCFPGA
Clock
initialization */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	/
*
pinctrl-
single */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		
/*
Arria10
hps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/*
Arria10
lwhps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		
/*
Arria10
fpga2hps bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		/
*
Arria10
fpga2SDRAM0 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		/
*
Arria10
fpga2SDRAM1 bridge */
Quoted 9 lines
Quoted 4 lines
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		/
*
Arria10
fpga2SDRAM2 bridge */
Is all of this needed ? You're only adding two entries in the
FDTDEC
below.
Quoted 10 lines
This is to avoid compilation error, we have some functions ported
from
our internal branch, which using above COMPAT macro. Soon, in
upcoming
patches, we will need those functions and more entries will be
added
into FDTDEC below.
Quoted 5 lines
You can add the compat strings when you really need them. Still,
with
DM, you shouldn't even need them AFAIK.
Quoted 6 lines
We have some drivers in these series of patches contain some COMPAT
strings, without these compact strings, the compilation would fail
due
to error compact string is not defined.
All of them ? Mind you, with DM you should not need to add those at
all.
Quoted 2 lines
Quoted 6 lines
Quoted 4 lines
I think having compact string
would giving us flexbility to put our nodes where we want without
worrying to break our existing codes?
Which existing codes ?
Quoted 7 lines
let say we have version A, we found the node based on COMPAT STRING.
One day, we move the node to somewhere else in version B, we still can
find them based on COMPAT STRING without checking the node path. What
do you think?
I do not understand what you're trying to tell me here. The DM core will
walk the DT and bind drivers according to compat strings, so if you ever move a node, it will still be bound.

Quoted 6 lines

Quoted 4 lines
Also, you didn't answer my question -- which existing codes do you refer
to. Or is this some hypothetical concern ?
existing codes is hypothetical example, when someone move the node somewhere, the DM still can find the node based on COMPAT STRING.

Correct. If you only have hypothetical concerns, we'll deal with those when they become real.

Quoted 2 lines

Without COMPAT STRING, we need to change the driver code for the node path right?

Uh no, the driver must never encode a fixed DT path. It should match on the compat string and that's it. And the compat string is part of the driver, not the FDT decoder. AFAIK, the strings in FDT decoder are just temporary helpers during the DT conversion of drivers.

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-19 10:31 UTC #14 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 188 lines · Marek Vasut

Quoted 172 lines · Tien Fong
Quoted 170 lines · Marek Vasut
Quoted 153 lines · Tien Fong
Quoted 144 lines · Marek Vasut
Quoted 125 lines · Tien Fong
Quoted 116 lines · Marek Vasut
Quoted 99 lines · Tien Fong
Quoted 85 lines · Marek Vasut
Quoted 80 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and
pin
mux
drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <tien.fong.chee@intel
.com
Quoted 2 lines
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
?include/fdtdec.h |????8 ++++++++ ?lib/fdtdec.c?????|????2 ++
?2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
? COMPAT_INTEL_BAYTRAIL_FSP_MDP, /*
Intel
FSP
memory-
down params */
? COMPAT_INTEL_IVYBRIDGE_FSP, /*
Intel
Ivy
Bridge
FSP
*/
? COMPAT_SUNXI_NAND, /* SUNXI
NAND
controller
*/
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_CLK,	/*
SoCFPGA
Clock
initialization */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	
/
*
pinctrl-
single */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		
/*
Arria10
hps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/*
Arria10
lwhps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		
/*
Arria10
fpga2hps bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		
/
*
Arria10
fpga2SDRAM0 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		
/
*
Arria10
fpga2SDRAM1 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		
/
Quoted 9 lines
Quoted 3 lines
*
Arria10
fpga2SDRAM2 bridge */
Is all of this needed ? You're only adding two
entries in
the
FDTDEC
below.
Quoted 13 lines
This is to avoid compilation error, we have some functions
ported
from
our internal branch, which using above COMPAT macro. Soon,
in
upcoming
patches, we will need those functions and more entries will
be
added
into FDTDEC below.
Quoted 5 lines
You can add the compat strings when you really need them. Still,
with
DM, you shouldn't even need them AFAIK.
Quoted 8 lines
We have some drivers in these series of patches contain some
COMPAT
strings, without these compact strings, the compilation would
fail
due
to error compact string is not defined.
All of them ? Mind you, with DM you should not need to add those
at
all.
Quoted 3 lines
Quoted 6 lines
Quoted 4 lines
I think having compact string
would giving us flexbility to put our nodes where we want without
worrying to break our existing codes?
Which existing codes ?
Quoted 9 lines
let say we have version A, we found the node based on COMPAT STRING.
One day, we move the node to somewhere else in version B, we still
can
find them based on COMPAT STRING without checking the node path.
What
do you think?
I do not understand what you're trying to tell me here. The DM core
will
walk the DT and bind drivers according to compat strings, so if you ever move a node, it will still be bound.
Quoted 7 lines
Quoted 5 lines
Also, you didn't answer my question -- which existing codes do you
refer
to. Or is this some hypothetical concern ?
existing codes is hypothetical example, when someone move the node somewhere, the DM still can find the node based on COMPAT STRING.
Correct. If you only have hypothetical concerns, we'll deal with those
when they become real.
Quoted 4 lines
Without COMPAT STRING, we need to change the driver code for the node
path right?

Quoted 7 lines

Uh no, the driver must never encode a fixed DT path. It should match on
the compat string and that's it. And the compat string is part of the driver, not the FDT decoder. AFAIK, the strings in FDT decoder are just
temporary helpers during the DT conversion of drivers.

Yeah, i have bridges reset driver in this series patches, and these drivers contains those COMPAT string. Without those COMPAT string, compilation would fail. It could be i missed to add those FDT entries, i can add those FDT entries in next version.

Marek Vasut

2016-12-19 12:40 UTC #15 lore raw

PATCH 4/10 arm: socfpga: arria10: Added clock manager and pin mux compat macro

Quoted 196 lines · Tien Fong

Quoted 188 lines · Marek Vasut
Quoted 172 lines · Tien Fong
Quoted 170 lines · Marek Vasut
Quoted 153 lines · Tien Fong
Quoted 144 lines · Marek Vasut
Quoted 125 lines · Tien Fong
Quoted 116 lines · Marek Vasut
Quoted 99 lines · Tien Fong
Quoted 85 lines · Marek Vasut
Quoted 80 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These compat macros would be used by clock manager and
pin
mux
drivers
to look the required HW info from DTS for hardware initialization.
Signed-off-by Tien Fong Chee <tien.fong.chee@intel
.com
Quoted 2 lines
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 include/fdtdec.h |    8 ++++++++
 lib/fdtdec.c     |    2 ++
 2 files changed, 10 insertions(+), 0 deletions(-)
include/fdtdec.h +0 -0
index 27887c8..68cb199 100644
@@ -155,6 +155,14 @@ enum fdt_compat_id {
 	COMPAT_INTEL_BAYTRAIL_FSP_MDP,	/*
Intel
FSP
memory-
down params */
COMPAT_INTEL_IVYBRIDGE_FSP, /*
Intel
Ivy
Bridge
FSP
*/
COMPAT_SUNXI_NAND, /* SUNXI
NAND
controller
*/
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_CLK,	/*
SoCFPGA
Clock
initialization */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_PINCTRL_SINGLE,	
/
*
pinctrl-
single */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_H2F_BRG,		
/*
Arria10
hps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,	/*
Arria10
lwhps2fpga bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2H_BRG,		
/*
Arria10
fpga2hps bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR0,		
/
*
Arria10
fpga2SDRAM0 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR1,		
/
*
Arria10
fpga2SDRAM1 bridge */
include/fdtdec.h +1 -0
+	COMPAT_ALTERA_SOCFPGA_F2SDR2,		
/
Quoted 9 lines
Quoted 3 lines
*
Arria10
fpga2SDRAM2 bridge */
Is all of this needed ? You're only adding two
entries in
the
FDTDEC
below.
Quoted 13 lines
This is to avoid compilation error, we have some functions
ported
from
our internal branch, which using above COMPAT macro. Soon,
in
upcoming
patches, we will need those functions and more entries will
be
added
into FDTDEC below.
Quoted 5 lines
You can add the compat strings when you really need them. Still,
with
DM, you shouldn't even need them AFAIK.
Quoted 8 lines
We have some drivers in these series of patches contain some
COMPAT
strings, without these compact strings, the compilation would
fail
due
to error compact string is not defined.
All of them ? Mind you, with DM you should not need to add those
at
all.
Quoted 3 lines
Quoted 6 lines
Quoted 4 lines
I think having compact string
would giving us flexbility to put our nodes where we want without
worrying to break our existing codes?
Which existing codes ?
Quoted 9 lines
let say we have version A, we found the node based on COMPAT STRING.
One day, we move the node to somewhere else in version B, we still
can
find them based on COMPAT STRING without checking the node path.
What
do you think?
I do not understand what you're trying to tell me here. The DM core
will
walk the DT and bind drivers according to compat strings, so if you ever move a node, it will still be bound.
Quoted 7 lines
Quoted 5 lines
Also, you didn't answer my question -- which existing codes do you
refer
to. Or is this some hypothetical concern ?
existing codes is hypothetical example, when someone move the node somewhere, the DM still can find the node based on COMPAT STRING.
Correct. If you only have hypothetical concerns, we'll deal with those
when they become real.
Quoted 4 lines
Without COMPAT STRING, we need to change the driver code for the node
path right?
Quoted 7 lines
Uh no, the driver must never encode a fixed DT path. It should match on
the compat string and that's it. And the compat string is part of the driver, not the FDT decoder. AFAIK, the strings in FDT decoder are just
temporary helpers during the DT conversion of drivers.

Quoted 4 lines

Yeah, i have bridges reset driver in this series patches, and these drivers contains those COMPAT string. Without those COMPAT string, compilation would fail. It could be i missed to add those FDT entries, i can add those FDT entries in next version.

OK, then add those compat strings with the matching driver if and only if it is needed.

Signature · 2 lines

Best regards,
Marek Vasut

Marek Vasut

2016-12-06 12:47 UTC #16 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

In reply to Chee Tien Fong

Quoted 3 lines · Chee Tien Fong

From: Tien Fong Chee <[email protected]>
These changes to ensure Arria10 SPL build success.

Please reword the commit message, mention you're removing the Arria10 bits. Still, this does not even apply on mainline, on top of what does this apply ?

Quoted 31 lines

Signed-off-by Tien Fong Chee <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Tien Fong <[email protected]>

---
 arch/arm/Kconfig |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

arch/arm/Kconfig +4 -4

index 220bb19..05ce8b8 100644
@@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select CPU_V7
-	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+	select SUPPORT_SPL
 	select OF_CONTROL
-	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+	select SPL_OF_CONTROL
 	select DM
-	select DM_SPI_FLASH
-	select DM_SPI
+	select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
+	select DM_SPI if !TARGET_SOCFPGA_ARRIA10
 
 config TARGET_CM_T43
 	bool "Support cm_t43"

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-07 10:57 UTC #17 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

Quoted 10 lines · Marek Vasut

Quoted 4 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These changes to ensure Arria10 SPL build success.
Please reword the commit message, mention you're removing the Arria10 bits. Still, this does not even apply on mainline, on top of what does
this apply ?

I disabled some features temporary, so SPL build can pass and print out working. I will enable these features back in upcoming patches. This is base on 01-arria10 branch.

Quoted 33 lines

Quoted 32 lines
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
?arch/arm/Kconfig |????8 ++++----
?1 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/Kconfig +0 -0
index 220bb19..05ce8b8 100644
@@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
?config ARCH_SOCFPGA
? bool "Altera SOCFPGA family"
? select CPU_V7
arch/arm/Kconfig +1 -1
-	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+	select SUPPORT_SPL
? select OF_CONTROL
arch/arm/Kconfig +1 -1
-	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+	select SPL_OF_CONTROL
? select DM
arch/arm/Kconfig +2 -2
-	select DM_SPI_FLASH
-	select DM_SPI
+	select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
+	select DM_SPI if !TARGET_SOCFPGA_ARRIA10
?
?config TARGET_CM_T43
? bool "Support cm_t43"

Marek Vasut

2016-12-07 13:54 UTC #18 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

Quoted 6 lines · Tien Fong

Quoted 5 lines · Marek Vasut
Quoted 4 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These changes to ensure Arria10 SPL build success.

Quoted 8 lines

Quoted 5 lines
Please reword the commit message, mention you're removing the Arria10 bits. Still, this does not even apply on mainline, on top of what does
this apply ?
I disabled some features temporary, so SPL build can pass and print out working. I will enable these features back in upcoming patches. This is base on 01-arria10 branch.

But this patch seems to only enable stuff ... ?

Quoted 31 lines

Signed-off-by Tien Fong Chee <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Tien Fong <[email protected]>

---
 arch/arm/Kconfig |    8 ++++----
 1 files changed, 4 insertions(+), 4 deletions(-)

arch/arm/Kconfig +4 -4

index 220bb19..05ce8b8 100644
@@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
 config ARCH_SOCFPGA
 	bool "Altera SOCFPGA family"
 	select CPU_V7
-	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+	select SUPPORT_SPL
 	select OF_CONTROL
-	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+	select SPL_OF_CONTROL
 	select DM
-	select DM_SPI_FLASH
-	select DM_SPI
+	select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
+	select DM_SPI if !TARGET_SOCFPGA_ARRIA10
 
 config TARGET_CM_T43
 	bool "Support cm_t43"

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-09 09:46 UTC #19 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

Quoted 16 lines · Marek Vasut

Quoted 15 lines · Tien Fong
Quoted 13 lines · Marek Vasut
Quoted 5 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These changes to ensure Arria10 SPL build success.
Please reword the commit message, mention you're removing the Arria10
bits. Still, this does not even apply on mainline, on top of what does
this apply ?

Quoted 7 lines

Quoted 5 lines
I disabled some features temporary, so SPL build can pass and print out
working. I will enable these features back in upcoming patches. This is
base on 01-arria10 branch.
But this patch seems to only enable stuff ... ?

Enable the spl. Disable SPI flash temporary, for preventing build failed, but this will be enabled back with upcoming patches for supporting SPI flash.

Quoted 35 lines

Quoted 34 lines
Quoted 34 lines
Quoted 34 lines
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
?arch/arm/Kconfig |????8 ++++----
?1 files changed, 4 insertions(+), 4 deletions(-)
arch/arm/Kconfig +0 -0
index 220bb19..05ce8b8 100644
@@ -622,12 +622,12 @@ config ARCH_SNAPDRAGON
?config ARCH_SOCFPGA
? bool "Altera SOCFPGA family"
? select CPU_V7
arch/arm/Kconfig +1 -1
-	select SUPPORT_SPL if !TARGET_SOCFPGA_ARRIA10
+	select SUPPORT_SPL
? select OF_CONTROL
arch/arm/Kconfig +1 -1
-	select SPL_OF_CONTROL if !TARGET_SOCFPGA_ARRIA10
+	select SPL_OF_CONTROL
? select DM
arch/arm/Kconfig +2 -2
-	select DM_SPI_FLASH
-	select DM_SPI
+	select DM_SPI_FLASH if !TARGET_SOCFPGA_ARRIA10
+	select DM_SPI if !TARGET_SOCFPGA_ARRIA10
?
?config TARGET_CM_T43
? bool "Support cm_t43"

Marek Vasut

2016-12-09 13:02 UTC #20 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

Quoted 22 lines · Tien Fong

Quoted 21 lines · Marek Vasut
Quoted 20 lines · Tien Fong
Quoted 4 lines · Marek Vasut
Quoted 2 lines · Chee Tien Fong
Quoted 9 lines
Quoted 3 lines
From: Tien Fong Chee <[email protected]>
These changes to ensure Arria10 SPL build success.
Please reword the commit message, mention you're removing the Arria10
bits. Still, this does not even apply on mainline, on top of what does
this apply ?
I disabled some features temporary, so SPL build can pass and print out
working. I will enable these features back in upcoming patches. This is
base on 01-arria10 branch.

Quoted 5 lines

Quoted 2 lines
But this patch seems to only enable stuff ... ?
Enable the spl. Disable SPI flash temporary, for preventing build failed, but this will be enabled back with upcoming patches for supporting SPI flash.

What's the problem with SPI flash ? I thought it's the same block as in C/A 5 ?

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-19 04:04 UTC #21 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

Quoted 30 lines · Marek Vasut

Quoted 29 lines · Tien Fong
Quoted 27 lines · Marek Vasut
Quoted 25 lines · Tien Fong
Quoted 8 lines · Marek Vasut
Quoted 5 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
Quoted 8 lines
Quoted 1 line
These changes to ensure Arria10 SPL build success.
Please reword the commit message, mention you're removing the Arria10
bits. Still, this does not even apply on mainline, on top of what
does
this apply ?
I disabled some features temporary, so SPL build can pass and print
out
working. I will enable these features back in upcoming patches. This is
base on 01-arria10 branch.

Quoted 9 lines

Quoted 5 lines
Quoted 2 lines
But this patch seems to only enable stuff ... ?
Enable the spl. Disable SPI flash temporary, for preventing build failed, but this will be enabled back with upcoming patches for supporting SPI flash.
What's the problem with SPI flash ? I thought it's the same block as in
C/A 5 ?

Some compilation error, but i haven't checked it out what errors causing the build failed. My plan is to have SPL and print out working, then following boot from SDMMC, FPGA configuration, DDR up. Once booting from SDMMC working, i will work to boot from QSPI and NAND too.

Quoted 1 line

Marek Vasut

2016-12-19 07:56 UTC #22 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

Quoted 40 lines · Tien Fong

Quoted 30 lines · Marek Vasut
Quoted 29 lines · Tien Fong
Quoted 27 lines · Marek Vasut
Quoted 25 lines · Tien Fong
Quoted 8 lines · Marek Vasut
Quoted 5 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
Quoted 8 lines
Quoted 1 line
These changes to ensure Arria10 SPL build success.
Please reword the commit message, mention you're removing the Arria10
bits. Still, this does not even apply on mainline, on top of what
does
this apply ?
I disabled some features temporary, so SPL build can pass and print
out
working. I will enable these features back in upcoming patches. This is
base on 01-arria10 branch.
Quoted 9 lines
Quoted 5 lines
Quoted 2 lines
But this patch seems to only enable stuff ... ?
Enable the spl. Disable SPI flash temporary, for preventing build failed, but this will be enabled back with upcoming patches for supporting SPI flash.
What's the problem with SPI flash ? I thought it's the same block as in
C/A 5 ?

Quoted 5 lines

Some compilation error, but i haven't checked it out what errors causing the build failed. My plan is to have SPL and print out working, then following boot from SDMMC, FPGA configuration, DDR up. Once booting from SDMMC working, i will work to boot from QSPI and NAND too.

MW is now closed, so you can focus on fixing the CQSPI too, it shouldn't be too hard.

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-19 08:41 UTC #23 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

Quoted 60 lines · Marek Vasut

Quoted 53 lines · Tien Fong
Quoted 42 lines · Marek Vasut
Quoted 40 lines · Tien Fong
Quoted 37 lines · Marek Vasut
Quoted 24 lines · Tien Fong
Quoted 11 lines · Marek Vasut
Quoted 7 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These changes to ensure Arria10 SPL build success.
Quoted 9 lines
Please reword the commit message, mention you're removing the
Arria10
bits. Still, this does not even apply on mainline, on top of
what
does
this apply ?
Quoted 8 lines
I disabled some features temporary, so SPL build can pass and
print
out
working. I will enable these features back in upcoming patches.
This is
base on 01-arria10 branch.
But this patch seems to only enable stuff ... ?
Quoted 9 lines
Quoted 4 lines
Enable the spl. Disable SPI flash temporary, for preventing build
failed, but this will be enabled back with upcoming patches for supporting SPI flash.
What's the problem with SPI flash ? I thought it's the same block as
in
C/A 5 ?
Quoted 6 lines
Some compilation error, but i haven't checked it out what errors causing the build failed. My plan is to have SPL and print out working,
then following boot from SDMMC, FPGA configuration, DDR up. Once booting from SDMMC working, i will work to boot from QSPI and NAND too.

Quoted 4 lines

MW is now closed, so you can focus on fixing the CQSPI too, it shouldn't
be too hard.

What is MW?

Marek Vasut

2016-12-19 08:44 UTC #24 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

Quoted 61 lines · Tien Fong

Quoted 60 lines · Marek Vasut
Quoted 59 lines · Tien Fong
Quoted 42 lines · Marek Vasut
Quoted 40 lines · Tien Fong
Quoted 37 lines · Marek Vasut
Quoted 24 lines · Tien Fong
Quoted 11 lines · Marek Vasut
Quoted 7 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These changes to ensure Arria10 SPL build success.
Quoted 9 lines
Please reword the commit message, mention you're removing the
Arria10
bits. Still, this does not even apply on mainline, on top of
what
does
this apply ?
Quoted 8 lines
I disabled some features temporary, so SPL build can pass and
print
out
working. I will enable these features back in upcoming patches.
This is
base on 01-arria10 branch.
But this patch seems to only enable stuff ... ?
Quoted 9 lines
Quoted 4 lines
Enable the spl. Disable SPI flash temporary, for preventing build
failed, but this will be enabled back with upcoming patches for supporting SPI flash.
What's the problem with SPI flash ? I thought it's the same block as
in
C/A 5 ?
Some compilation error, but i haven't checked it out what errors causing the build failed. My plan is to have SPL and print out working,
then following boot from SDMMC, FPGA configuration, DDR up. Once booting from SDMMC working, i will work to boot from QSPI and NAND too.

Quoted 6 lines

Quoted 4 lines
MW is now closed, so you can focus on fixing the CQSPI too, it shouldn't
be too hard.
What is MW?

Merge Window

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-19 10:34 UTC #25 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

Quoted 79 lines · Marek Vasut

Quoted 78 lines · Tien Fong
Quoted 76 lines · Marek Vasut
Quoted 74 lines · Tien Fong
Quoted 56 lines · Marek Vasut
Quoted 46 lines · Tien Fong
Quoted 42 lines · Marek Vasut
Quoted 38 lines · Tien Fong
Quoted 13 lines · Marek Vasut
Quoted 8 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These changes to ensure Arria10 SPL build success.
Quoted 11 lines
Please reword the commit message, mention you're removing
the
Arria10
bits. Still, this does not even apply on mainline, on top
of
what
does
this apply ?
I disabled some features temporary, so SPL build can pass
and
print
out
working. I will enable these features back in upcoming patches.
This is
base on 01-arria10 branch.
Quoted 7 lines
Quoted 2 lines
But this patch seems to only enable stuff ... ?
Enable the spl. Disable SPI flash temporary, for preventing build
failed, but this will be enabled back with upcoming patches for
supporting SPI flash.
Quoted 6 lines
What's the problem with SPI flash ? I thought it's the same block
as
in
C/A 5 ?
Some compilation error, but i haven't checked it out what errors
causing the build failed. My plan is to have SPL and print out working,
then following boot from SDMMC, FPGA configuration, DDR up. Once
booting from SDMMC working, i will work to boot from QSPI and NAND
too.

Quoted 7 lines

Quoted 6 lines
Quoted 4 lines
MW is now closed, so you can focus on fixing the CQSPI too, it shouldn't
be too hard.
What is MW?
Merge Window

just for comfirmation, are you means rebase to master of u-boot- socfpga.git or denx master? I think former,right?

Marek Vasut

2016-12-19 12:36 UTC #26 lore raw

PATCH 2/10 arm: socfpga: arria10: Added config option build for SPL

Quoted 84 lines · Tien Fong

Quoted 83 lines · Marek Vasut
Quoted 82 lines · Tien Fong
Quoted 80 lines · Marek Vasut
Quoted 65 lines · Tien Fong
Quoted 56 lines · Marek Vasut
Quoted 46 lines · Tien Fong
Quoted 42 lines · Marek Vasut
Quoted 38 lines · Tien Fong
Quoted 13 lines · Marek Vasut
Quoted 8 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
These changes to ensure Arria10 SPL build success.
Quoted 11 lines
Please reword the commit message, mention you're removing
the
Arria10
bits. Still, this does not even apply on mainline, on top
of
what
does
this apply ?
I disabled some features temporary, so SPL build can pass
and
print
out
working. I will enable these features back in upcoming patches.
This is
base on 01-arria10 branch.
Quoted 7 lines
Quoted 2 lines
But this patch seems to only enable stuff ... ?
Enable the spl. Disable SPI flash temporary, for preventing build
failed, but this will be enabled back with upcoming patches for
supporting SPI flash.
Quoted 6 lines
What's the problem with SPI flash ? I thought it's the same block
as
in
C/A 5 ?
Quoted 9 lines
Some compilation error, but i haven't checked it out what errors
causing the build failed. My plan is to have SPL and print out working,
then following boot from SDMMC, FPGA configuration, DDR up. Once
booting from SDMMC working, i will work to boot from QSPI and NAND
too.
MW is now closed, so you can focus on fixing the CQSPI too, it shouldn't
be too hard.

Quoted 7 lines

Quoted 3 lines
Quoted 2 lines
What is MW?
Merge Window
just for comfirmation, are you means rebase to master of u-boot- socfpga.git or denx master? I think former,right?

You can use either now, u-boot-socfpga has no patches queued and u-boot.git is more up-to-date .

Signature · 2 lines

Best regards,
Marek Vasut