arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

PATCH New Chee Tien Fong 3 participants 6 messages Dec 6, 2016 – Dec 9, 2016

Subsystems (4)

Arm (32-bit) Arm sub-architectures FPGA manager framework Arm/socfpga architecture

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Chee Tien Fong

author

2016-12-06 08:07 UTC #0 lore raw

PATCH 5/10 arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

From: Tien Fong Chee <[email protected]>

Signed-off-by Tien Fong Chee <[email protected]>

Cc Marek Vasut <[email protected]>

Cc Dinh Nguyen <[email protected]>

Cc Chin Liang See <[email protected]>

Cc Tien Fong <[email protected]>

---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   11 +-
 arch/arm/mach-socfpga/system_manager.c             |    4 +-
 drivers/fpga/socfpga.c                             |    7 +-
 include/configs/socfpga_arria10_socdk.h            |  152 +++++++++++++++++--
 4 files changed, 151 insertions(+), 23 deletions(-)

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +7 -4

index 902c321..487a5dc 100644
@@ -1,7 +1,7 @@
 /*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0
  */
 
 #ifndef _SOCFPGA_A10_BASE_HARDWARE_H_

@@ -35,11 +35,14 @@
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS		0xff8c3000
 #define SOCFPGA_UART0_ADDRESS			0xffc02000
-#define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER1_ADDRESS		0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS			0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS			0xffd05000
 
-#define SOCFPGA_SDR_ADDRESS			0xffcfb000
+#define SOCFPGA_SDR_ADDRESS					0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST        0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST			0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS	0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS	0xffd13300

arch/arm/mach-socfpga/system_manager.c +3 -1

index 9e1c3fd..e1f0082 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013-2016 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -11,8 +11,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /*
  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.

drivers/fpga/socfpga.c +5 -2

index bfefafd..7fd922e 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
  * All rights reserved.
  *
  * SPDX-License-Identifier:	BSD-3-Clause

@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
 	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)

@@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 	}
 
 	/* Prior programming the FPGA, all bridges need to be shut off */
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 	/* Disable all signals from hps peripheral controller to fpga */
 	writel(0, &sysmgr_regs->fpgaintfgrp_module);
+#endif
 
 	/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS	0x5080

include/configs/socfpga_arria10_socdk.h +136 ~~-16~~

190 lines not on this page · raw message

Signature · 1 line

1.7.7.4

Marek Vasut

2016-12-06 12:51 UTC #1 lore raw

PATCH 5/10 arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

Quoted 19 lines · Chee Tien Fong

From: Tien Fong Chee <[email protected]>
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   11 +-
 arch/arm/mach-socfpga/system_manager.c             |    4 +-
 drivers/fpga/socfpga.c                             |    7 +-
 include/configs/socfpga_arria10_socdk.h            |  152 +++++++++++++++++--
 4 files changed, 151 insertions(+), 23 deletions(-)
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +0 -0
index 902c321..487a5dc 100644

arch/arm/mach-socfpga/include/mach/base_addr_a10.h line 4

Quoted 6 lines

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +2 -2

@@ -1,7 +1,7 @@
 /*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0

Can you change license this way ?

arch/arm/mach-socfpga/include/mach/base_addr_a10.h line 41

Quoted 12 lines

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +2 -1

  */
 
 #ifndef _SOCFPGA_A10_BASE_HARDWARE_H_

@@ -35,11 +35,14 @@
 
 #define SOCFPGA_ECC_OCRAM_ADDRESS		0xff8c3000
 #define SOCFPGA_UART0_ADDRESS			0xffc02000
-#define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER1_ADDRESS		0xffd00100
 #define SOCFPGA_CLKMGR_ADDRESS			0xffd04000
 #define SOCFPGA_RSTMGR_ADDRESS			0xffd05000

This should be in a separate patch.

arch/arm/mach-socfpga/system_manager.c

Quoted 11 lines

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +3 -1

-#define SOCFPGA_SDR_ADDRESS			0xffcfb000
+#define SOCFPGA_SDR_ADDRESS					0xffcfb000
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST        0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST			0xffd13500
 #define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xffd12400
 #define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS	0xffd13200
 #define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS	0xffd13300

arch/arm/mach-socfpga/system_manager.c +0 -0

index 9e1c3fd..e1f0082 100644

This should also be in a separate patch, don't go hacking common code in board-support patch.

Quoted 153 lines

arch/arm/mach-socfpga/system_manager.c +3 -1

@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013-2016 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0+
  */

@@ -11,8 +11,10 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /*
  * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.

drivers/fpga/socfpga.c +5 -2

index bfefafd..7fd922e 100644
@@ -1,5 +1,5 @@
 /*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
  * All rights reserved.
  *
  * SPDX-License-Identifier:	BSD-3-Clause

@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
 
 static struct socfpga_fpga_manager *fpgamgr_regs =
 	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
 
 /* Set CD ratio */
 static void fpgamgr_set_cd_ratio(unsigned long ratio)

@@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
 	}
 
 	/* Prior programming the FPGA, all bridges need to be shut off */
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 	/* Disable all signals from hps peripheral controller to fpga */
 	writel(0, &sysmgr_regs->fpgaintfgrp_module);
+#endif
 
 	/* Disable all signals from FPGA to HPS SDRAM */
 #define SDR_CTRLGRP_FPGAPORTRST_ADDRESS	0x5080

include/configs/socfpga_arria10_socdk.h +45 ~~-14~~

index 577f60f..15c7a28 100644
@@ -1,5 +1,5 @@
 /*
- *  Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2015-2016 Altera Corporation <www.altera.com>
  *
  * SPDX-License-Identifier:	GPL-2.0
  */

@@ -16,36 +16,67 @@
 
 #define CONFIG_CMD_ASKENV
 #define CONFIG_CMD_BOOTZ
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
 #define CONFIG_CMD_EXT4
 #define CONFIG_CMD_EXT4_WRITE
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
 #define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MMC
 #define CONFIG_CMD_PING
 
-/*
- * Memory configurations
- */
-#define PHYS_SDRAM_1_SIZE		0x2000000
-
 /* Booting Linux */
-#define CONFIG_BOOTDELAY	3
 #define CONFIG_BOOTFILE		"zImage"
 #define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
 #define CONFIG_BOOTCOMMAND      "run mmcload; run mmcboot"
-#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_LOADADDR		0x8000
 #define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR
 
 /*
+ * U-Boot general configurations
+ */
+/* Base address for .text section. */
+/* Ensure located start of HPS OCRAM */
+#define CONFIG_SYS_TEXT_BASE		0xFFE00000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
+
+/*
+ * U-Boot console configurations
+ */
+#define CONFIG_SYS_MAXARGS             64
+#define CONFIG_SYS_CBSIZE              2048
+#define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE + \
+                                       sizeof(CONFIG_SYS_PROMPT) + 16)
+#define CONFIG_SYS_BARGSIZE            CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_DOS_PARTITION
+
+/* U-Boot run time memory configurations  */
+#define CONFIG_SYS_INIT_RAM_ADDR       0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE       0x40000
+#define CONFIG_SYS_INIT_SP_ADDR        (CONFIG_SYS_INIT_RAM_ADDR \
+                                       + CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET      (CONFIG_SYS_INIT_SP_ADDR)
+#define CONFIG_SYS_MALLOC_LEN          (64 * 1024 * 1024)
+
+/*
  * Display CPU and Board Info
  */
 #define CONFIG_DISPLAY_CPUINFO
 #define CONFIG_DISPLAY_BOARDINFO
 #define CONFIG_DISPLAY_BOARDINFO_LATE
 
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE		1
+#ifndef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE		4096
+#endif
+
 /* Ethernet on SoC (EMAC) */
 #if defined(CONFIG_CMD_NET)

@@ -55,7 +86,7 @@
 
 #endif
 
-#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_MMC
 #define CONFIG_SYS_MMC_ENV_DEV		0/* device 0 */
 #define CONFIG_ENV_OFFSET		512/* just after the MBR */

include/configs/socfpga_arria10_socdk.h line 125

Quoted 8 lines

include/configs/socfpga_arria10_socdk.h +3 -2

@@ -89,6 +120,95 @@
 		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
 		"bootm ${loadaddr} - ${fdt_addr}\0"
 
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
+/*
+ * External memory configurations
+ */

Why is this being duplicated in board support code when it previously was in common code ? That's just wrong.

Quoted 90 lines

include/configs/socfpga_arria10_socdk.h +88 -0

+#define PHYS_SDRAM_1                   0x0
+#define PHYS_SDRAM_1_SIZE              0x80000000
+#define CONFIG_SYS_SDRAM_BASE          0
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_MEMTEST_START       0
+#define CONFIG_SYS_MEMTEST_END         0x100000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE    -4
+#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, 115200}
+#define CONFIG_SYS_NS16550_CLK         (50000000)
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                115200
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_SYSTIMER0_ADDRESS
+/* address of timer counter value */
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+/* Clocks source frequency to timer */
+#define CONFIG_SYS_TIMER_RATE		(25000000)
+
+/* DesignWare timer is a countdown timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+/*
+ * L4 Watchdog configurations
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#define CONFIG_HPS_CLK_OSC1_HZ	25000000
+#define CONFIG_DW_WDT_CLOCK_KHZ		(CONFIG_HPS_CLK_OSC1_HZ / 1000)
+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	(2000)
+#endif
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH        1024
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT           256
+#endif
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_NO_FLASH
+
+/* SPL configuration */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
+#define CONFIG_SPL_MAX_SIZE			CONFIG_SYS_INIT_RAM_SIZE
+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#ifdef CONFIG_SPL_NAND_DENALI
+#define CONFIG_SPL_NAND_SUPPORT
+#endif
+
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK			CONFIG_SYS_INIT_SP_ADDR
+
+/* SPL SDMMC boot support */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-boot-dtb.img"
+
 #endif	/* __CONFIG_H */

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-07 11:21 UTC #2 lore raw

PATCH 5/10 arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

Quoted 17 lines · Marek Vasut

Quoted 16 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
?arch/arm/mach-socfpga/include/mach/base_addr_a10.h |???11 +-
?arch/arm/mach-socfpga/system_manager.c?????????????|????4 +-
?drivers/fpga/socfpga.c?????????????????????????????|????7 +-
?include/configs/socfpga_arria10_socdk.h????????????|??152
+++++++++++++++++--
?4 files changed, 151 insertions(+), 23 deletions(-)

Quoted 14 lines

Quoted 6 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +0 -0
index 902c321..487a5dc 100644
@@ -1,7 +1,7 @@
Quoted 6 lines
?/*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com> ? *
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0
Can you change license this way ?

Okay, i will revert this change. I discussed with Chin Liang today, and we decided to let owner to make the changes. How about the year change 2014-2016?

Quoted 25 lines

Quoted 11 lines
? */
?
?#ifndef _SOCFPGA_A10_BASE_HARDWARE_H_
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +0 -0
@@ -35,11 +35,14 @@
?
?#define SOCFPGA_ECC_OCRAM_ADDRESS 0xff8c3000
?#define SOCFPGA_UART0_ADDRESS 0xffc02000
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +2 -1
-#define SOCFPGA_OSC1TIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER1_ADDRESS		0xffd00100
Quoted 2 lines
?#define SOCFPGA_CLKMGR_ADDRESS 0xffd04000
?#define SOCFPGA_RSTMGR_ADDRESS 0xffd05000
This should be in a separate patch.
Quoted 10 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +1 -1
-#define SOCFPGA_SDR_ADDRESS			0xffcfb000
+#define SOCFPGA_SDR_ADDRESS					
0xffcfb000
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +2 -0
+#define SOCFPGA_NOC_L4_PRIV_FLT_OFST????????0xffd11000
+#define SOCFPGA_NOC_FW_H2F_SCR_OFST			0xffd13
500
?#define SOCFPGA_SDR_SCHEDULER_ADDRESS 0xffd12400
?#define SOCFPGA_SDR_FIREWALL_OCRAM_ADDRESS 0xffd13200
?#define SOCFPGA_SDR_FIREWALL_MPU_FPGA_ADDRESS 0xffd13300

Quoted 9 lines

arch/arm/mach-socfpga/system_manager.c
Quoted 5 lines
arch/arm/mach-socfpga/system_manager.c +0 -0
index 9e1c3fd..e1f0082 100644
This should also be in a separate patch, don't go hacking common code in
board-support patch.

Okay, i will move these changes to separate patch. Those removed #define is no longer valid.

Quoted 166 lines

Quoted 166 lines
arch/arm/mach-socfpga/system_manager.c +0 -0
@@ -1,5 +1,5 @@
?/*
- * Copyright (C) 2013 Altera Corporation <www.altera.com>
+ * Copyright (C) 2013-2016 Altera Corporation <www.altera.com> ? *
? * SPDX-License-Identifier: GPL-2.0+
? */
arch/arm/mach-socfpga/system_manager.c +0 -0
@@ -11,8 +11,10 @@
?
?DECLARE_GLOBAL_DATA_PTR;
?
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
?static struct socfpga_system_manager *sysmgr_regs =
? (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
?
?/*
? * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
drivers/fpga/socfpga.c +0 -0
index bfefafd..7fd922e 100644
@@ -1,5 +1,5 @@
?/*
- * Copyright (C) 2012 Altera Corporation <www.altera.com>
+ * Copyright (C) 2012-2016 Altera Corporation <www.altera.com> ? * All rights reserved.
? *
? * SPDX-License-Identifier: BSD-3-Clause
drivers/fpga/socfpga.c +0 -0
@@ -19,8 +19,10 @@ DECLARE_GLOBAL_DATA_PTR;
?
?static struct socfpga_fpga_manager *fpgamgr_regs =
? (struct socfpga_fpga_manager
*)SOCFPGA_FPGAMGRREGS_ADDRESS;
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5) ?static struct socfpga_system_manager *sysmgr_regs =
? (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
+#endif
?
?/* Set CD ratio */
?static void fpgamgr_set_cd_ratio(unsigned long ratio)
drivers/fpga/socfpga.c +0 -0
@@ -267,9 +269,10 @@ int socfpga_load(Altera_desc *desc, const void
 *rbf_data, size_t rbf_size)
 ?	}
?
? /* Prior programming the FPGA, all bridges need to be shut
off */
drivers/fpga/socfpga.c +1 -1
-
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
? /* Disable all signals from hps peripheral controller to
fpga */
? writel(0, &sysmgr_regs->fpgaintfgrp_module);
+#endif
?
? /* Disable all signals from FPGA to HPS SDRAM */
?#define SDR_CTRLGRP_FPGAPORTRST_ADDRESS 0x5080
include/configs/socfpga_arria10_socdk.h +0 -0
index 577f60f..15c7a28 100644
@@ -1,5 +1,5 @@
?/*
- *??Copyright (C) 2015 Altera Corporation <www.altera.com>
+ *??Copyright (C) 2015-2016 Altera Corporation <www.altera.com> ? *
? * SPDX-License-Identifier: GPL-2.0
? */
include/configs/socfpga_arria10_socdk.h +0 -0
@@ -16,36 +16,67 @@
?
?#define CONFIG_CMD_ASKENV
?#define CONFIG_CMD_BOOTZ
include/configs/socfpga_arria10_socdk.h +0 -2
-#define CONFIG_CMD_CACHE
-#define CONFIG_CMD_DHCP
?#define CONFIG_CMD_EXT4
?#define CONFIG_CMD_EXT4_WRITE
include/configs/socfpga_arria10_socdk.h +0 -2
-#define CONFIG_CMD_FAT
-#define CONFIG_CMD_FS_GENERIC
?#define CONFIG_CMD_GREPENV
-#define CONFIG_CMD_MMC
?#define CONFIG_CMD_PING
?
include/configs/socfpga_arria10_socdk.h +0 -5
-/*
- * Memory configurations
- */
-#define PHYS_SDRAM_1_SIZE		0x2000000
-
?/* Booting Linux */
-#define CONFIG_BOOTDELAY 3
?#define CONFIG_BOOTFILE "zImage"
?#define CONFIG_BOOTARGS "console=ttyS0,"
__stringify(CONFIG_BAUDRATE)
?#define CONFIG_BOOTCOMMAND??????"run mmcload; run mmcboot"
include/configs/socfpga_arria10_socdk.h +1 -1
-#define CONFIG_LOADADDR		0x01000000
+#define CONFIG_LOADADDR		0x8000
?#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
?
?/*
+ * U-Boot general configurations
+ */
include/configs/socfpga_arria10_socdk.h +18 -0
+/* Base address for .text section. */
+/* Ensure located start of HPS OCRAM */
+#define CONFIG_SYS_TEXT_BASE		0xFFE00000
+#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
+
+/* Cache options */
+#define CONFIG_SYS_DCACHE_OFF
+#define CONFIG_CMD_CACHE
+#define CONFIG_SYS_L2_PL310
+#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS
+
+/*
+ * U-Boot console configurations
+ */
+#define CONFIG_SYS_MAXARGS?????????????64
+#define CONFIG_SYS_CBSIZE??????????????2048
+#define CONFIG_SYS_PBSIZE??????????????(CONFIG_SYS_CBSIZE + \
+???????????????????????????????????????sizeof(CONFIG_SYS_PROMPT) +
16)
include/configs/socfpga_arria10_socdk.h +14 -0
+#define CONFIG_SYS_BARGSIZE????????????CONFIG_SYS_CBSIZE
+#define CONFIG_SYS_LONGHELP
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_DOS_PARTITION
+
+/* U-Boot run time memory configurations??*/
+#define CONFIG_SYS_INIT_RAM_ADDR???????0xFFE00000
+#define CONFIG_SYS_INIT_RAM_SIZE???????0x40000
+#define CONFIG_SYS_INIT_SP_ADDR????????(CONFIG_SYS_INIT_RAM_ADDR \
+???????????????????????????????????????+ CONFIG_SYS_INIT_RAM_SIZE)
+#define CONFIG_SYS_INIT_SP_OFFSET??????(CONFIG_SYS_INIT_SP_ADDR)
+#define CONFIG_SYS_MALLOC_LEN??????????(64 * 1024 * 1024)
+
+/*
? * Display CPU and Board Info
? */
?#define CONFIG_DISPLAY_CPUINFO
?#define CONFIG_DISPLAY_BOARDINFO
?#define CONFIG_DISPLAY_BOARDINFO_LATE
?
include/configs/socfpga_arria10_socdk.h +8 -0
+/*
+ * U-Boot environment configurations
+ */
+#define CONFIG_ENV_IS_NOWHERE		1
+#ifndef CONFIG_ENV_SIZE
+#define CONFIG_ENV_SIZE		4096
+#endif
+
?/* Ethernet on SoC (EMAC) */
?#if defined(CONFIG_CMD_NET)
?
include/configs/socfpga_arria10_socdk.h +0 -0
@@ -55,7 +86,7 @@
?
?#endif
?
include/configs/socfpga_arria10_socdk.h +1 -1
-#define CONFIG_ENV_IS_IN_MMC
+#undef CONFIG_ENV_IS_IN_MMC
?#define CONFIG_SYS_MMC_ENV_DEV 0/* device 0 */
?#define CONFIG_ENV_OFFSET 512/* just after the MBR
*/
?
include/configs/socfpga_arria10_socdk.h +0 -0
@@ -89,6 +120,95 @@
? " root=${qspiroot} rw
rootfstype=${qspirootfstype};"\
? "bootm ${loadaddr} - ${fdt_addr}\0"

Quoted 9 lines

include/configs/socfpga_arria10_socdk.h line 125
Quoted 6 lines
?
include/configs/socfpga_arria10_socdk.h +3 -2
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
+/*
+ * External memory configurations
+ */
Why is this being duplicated in board support code when it previously was in common code ? That's just wrong.

I found that many conflicts between the board support code and common code. It is safe for Arria10 having its own setting here. What do you think?

Quoted 100 lines

Quoted 99 lines

include/configs/socfpga_arria10_socdk.h +15 -0

+#define PHYS_SDRAM_1???????????????????0x0
+#define PHYS_SDRAM_1_SIZE??????????????0x80000000
+#define CONFIG_SYS_SDRAM_BASE??????????0
+#define CONFIG_NR_DRAM_BANKS???????????1
+#define CONFIG_SYS_MEMTEST_START???????0
+#define CONFIG_SYS_MEMTEST_END?????????0x100000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE????-4
+#define CONFIG_SYS_NS16550_COM1????????SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400,

57600, 115200}

include/configs/socfpga_arria10_socdk.h +10 -0

+#define CONFIG_SYS_NS16550_CLK?????????(50000000)
+#define CONFIG_CONS_INDEX??????????????1
+#define CONFIG_BAUDRATE????????????????115200
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_SYSTIMER0_ADDR

ESS

include/configs/socfpga_arria10_socdk.h +2 -0

+/* address of timer counter value */
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE +

0x4)

include/configs/socfpga_arria10_socdk.h +16 -0

+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+/* Clocks source frequency to timer */
+#define CONFIG_SYS_TIMER_RATE		(25000000)
+
+/* DesignWare timer is a countdown timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+/*
+ * L4 Watchdog configurations
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#define CONFIG_HPS_CLK_OSC1_HZ	25000000
+#define CONFIG_DW_WDT_CLOCK_KHZ		(CONFIG_HPS_CLK_OSC

1_HZ / 1000)

include/configs/socfpga_arria10_socdk.h +26 -0

+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	(2000)
+#endif
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH????????1024
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT???????????256
+#endif
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS?????1
+#define CONFIG_SYS_NO_FLASH
+
+/* SPL configuration */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_AD

DR
+#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT
_RAM_SIZE

include/configs/socfpga_arria10_socdk.h +13 -0

+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#ifdef CONFIG_SPL_NAND_DENALI
+#define CONFIG_SPL_NAND_SUPPORT
+#endif
+
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK			CONFIG_SYS_INIT_SP

_ADDR

include/configs/socfpga_arria10_socdk.h +4 -0

+
+/* SPL SDMMC boot support */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION?????1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME????????????????"u-boot-

dtb.img"
+
?#endif /* __CONFIG_H */

Marek Vasut

2016-12-07 13:57 UTC #3 lore raw

PATCH 5/10 arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

Quoted 32 lines · Tien Fong

Quoted 17 lines · Marek Vasut
Quoted 16 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   11 +-
 arch/arm/mach-socfpga/system_manager.c             |    4 +-
 drivers/fpga/socfpga.c                             |    7 +-
 include/configs/socfpga_arria10_socdk.h            |  152
+++++++++++++++++--
 4 files changed, 151 insertions(+), 23 deletions(-)
Quoted 14 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h line 4
Quoted 12 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +2 -2
index 902c321..487a5dc 100644
@@ -1,7 +1,7 @@
 /*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0
Can you change license this way ?

Quoted 3 lines

Okay, i will revert this change. I discussed with Chin Liang today, and we decided to let owner to make the changes. How about the year change 2014-2016?

To change a license of a file, you need to get an ACK from every single contributor to that file.

Year change I believe is fine.

[...]

Quoted 13 lines

Quoted 5 lines
Quoted 5 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +0 -0
@@ -89,6 +120,95 @@
 		" root=${qspiroot} rw
 rootfstype=${qspirootfstype};"\
 		"bootm ${loadaddr} - ${fdt_addr}\0"
 
Quoted 8 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h line 126
Quoted 5 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +3 -2
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
+/*
+ * External memory configurations
+ */
Why is this being duplicated in board support code when it previously was in common code ? That's just wrong.

Quoted 3 lines

I found that many conflicts between the board support code and common code. It is safe for Arria10 having its own setting here. What do you think?

It looks like 95% of the stuff below is the same as the stuff in socfpga-common.h , the rest can be pulled from DT or ifdef'd .

Quoted 98 lines

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +15 -0

+#define PHYS_SDRAM_1                   0x0
+#define PHYS_SDRAM_1_SIZE              0x80000000
+#define CONFIG_SYS_SDRAM_BASE          0
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_MEMTEST_START       0
+#define CONFIG_SYS_MEMTEST_END         0x100000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE    -4
+#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400,

57600, 115200}

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +10 -0

+#define CONFIG_SYS_NS16550_CLK         (50000000)
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                115200
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_SYSTIMER0_ADDR

ESS

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +2 -0

+/* address of timer counter value */
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE +

0x4)

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +16 -0

+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+/* Clocks source frequency to timer */
+#define CONFIG_SYS_TIMER_RATE		(25000000)
+
+/* DesignWare timer is a countdown timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+/*
+ * L4 Watchdog configurations
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
+#define CONFIG_HPS_CLK_OSC1_HZ	25000000
+#define CONFIG_DW_WDT_CLOCK_KHZ		(CONFIG_HPS_CLK_OSC

1_HZ / 1000)

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +26 -0

+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	(2000)
+#endif
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH        1024
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT           256
+#endif
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_NO_FLASH
+
+/* SPL configuration */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_AD

DR
+#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT
_RAM_SIZE

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +13 -0

+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#ifdef CONFIG_SPL_NAND_DENALI
+#define CONFIG_SPL_NAND_SUPPORT
+#endif
+
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK			CONFIG_SYS_INIT_SP

_ADDR

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +4 -0

+
+/* SPL SDMMC boot support */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-boot-

dtb.img"
+
#endif /* __CONFIG_H */

Signature · 2 lines

Best regards,
Marek Vasut

Chee

2016-12-09 09:55 UTC #4 lore raw

PATCH 5/10 arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

Quoted 41 lines · Marek Vasut

Quoted 35 lines · Tien Fong
Quoted 19 lines · Marek Vasut
Quoted 17 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
?arch/arm/mach-socfpga/include/mach/base_addr_a10.h |???11 +-
?arch/arm/mach-socfpga/system_manager.c?????????????|????4 +-
?drivers/fpga/socfpga.c?????????????????????????????|????7 +-
?include/configs/socfpga_arria10_socdk.h????????????|??152
+++++++++++++++++--
?4 files changed, 151 insertions(+), 23 deletions(-)
Quoted 14 lines
Quoted 6 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +0 -0
index 902c321..487a5dc 100644
@@ -1,7 +1,7 @@
Quoted 6 lines
?/*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com> ? *
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0
Can you change license this way ?
Quoted 5 lines
Okay, i will revert this change. I discussed with Chin Liang today, and
we decided to let owner to make the changes. How about the year change
2014-2016?

Quoted 8 lines

To change a license of a file, you need to get an ACK from every single
contributor to that file.
Year change I believe is fine.
[...]

Okay, noted.

Quoted 17 lines

Quoted 17 lines
Quoted 17 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h
Quoted 13 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +0 -0
@@ -89,6 +120,95 @@
? " root=${qspiroot} rw
rootfstype=${qspirootfstype};"\
? "bootm ${loadaddr} - ${fdt_addr}\0"
?
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +3 -2
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
+/*
+ * External memory configurations
+ */
Why is this being duplicated in board support code when it previously
was in common code ? That's just wrong.

Quoted 8 lines

Quoted 5 lines
I found that many conflicts between the board support code and common
code. It is safe for Arria10 having its own setting here. What do you
think?
It looks like 95% of the stuff below is the same as the stuff in socfpga-common.h , the rest can be pulled from DT or ifdef'd .

If socfpga-common.h is preferred, then i have to use ifdef method, are you ok with this? However, this would look a bit messy, because some #define setting in here, and other #define setting in socfpga-common.h under same category or peripheral configuration group.

Quoted 110 lines

Quoted 109 lines

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +15 -0

+#define PHYS_SDRAM_1???????????????????0x0
+#define PHYS_SDRAM_1_SIZE??????????????0x80000000
+#define CONFIG_SYS_SDRAM_BASE??????????0
+#define CONFIG_NR_DRAM_BANKS???????????1
+#define CONFIG_SYS_MEMTEST_START???????0
+#define CONFIG_SYS_MEMTEST_END?????????0x100000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE????-4
+#define CONFIG_SYS_NS16550_COM1????????SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400,

57600, 115200}

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +10 -0

+#define CONFIG_SYS_NS16550_CLK?????????(50000000)
+#define CONFIG_CONS_INDEX??????????????1
+#define CONFIG_BAUDRATE????????????????115200
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_SYSTIMER0_

ADDR
ESS

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +3 -0

+/* address of timer counter value */
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE
+

0x4)

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +14 -0

+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+/* Clocks source frequency to timer */
+#define CONFIG_SYS_TIMER_RATE		(25000000)
+
+/* DesignWare timer is a countdown timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+/*
+ * L4 Watchdog configurations
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRES

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +2 -0

+#define CONFIG_HPS_CLK_OSC1_HZ	25000000
+#define CONFIG_DW_WDT_CLOCK_KHZ		(CONFIG_HPS_CLK

_OSC
1_HZ / 1000)

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +26 -0

+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	(2000)
+#endif
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH????????1024
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT???????????256
+#endif
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS?????1
+#define CONFIG_SYS_NO_FLASH
+
+/* SPL configuration */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RA

M_AD
DR
+#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_
INIT
_RAM_SIZE

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +13 -0

+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#ifdef CONFIG_SPL_NAND_DENALI
+#define CONFIG_SPL_NAND_SUPPORT
+#endif
+
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK			CONFIG_SYS_INI

T_SP
_ADDR

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +4 -0

+
+/* SPL SDMMC boot support */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION?????1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME????????????????"u-

boot-
dtb.img"
+
?#endif /* __CONFIG_H */

Marek Vasut

2016-12-09 12:54 UTC #5 lore raw

PATCH 5/10 arm: socfpga: arria10: Added support for Arria 10 SoC dev kit

Quoted 73 lines · Tien Fong

Quoted 41 lines · Marek Vasut
Quoted 35 lines · Tien Fong
Quoted 19 lines · Marek Vasut
Quoted 17 lines · Chee Tien Fong
From: Tien Fong Chee <[email protected]>
Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 arch/arm/mach-socfpga/include/mach/base_addr_a10.h |   11 +-
 arch/arm/mach-socfpga/system_manager.c             |    4 +-
 drivers/fpga/socfpga.c                             |    7 +-
 include/configs/socfpga_arria10_socdk.h            |  152
+++++++++++++++++--
 4 files changed, 151 insertions(+), 23 deletions(-)
Quoted 14 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h line 4
Quoted 12 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +2 -2
index 902c321..487a5dc 100644
@@ -1,7 +1,7 @@
 /*
- * Copyright (C) 2014 Altera Corporation <www.altera.com>
+ * Copyright (C) 2014-2016 Altera Corporation <www.altera.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0
Can you change license this way ?
Quoted 5 lines
Okay, i will revert this change. I discussed with Chin Liang today, and
we decided to let owner to make the changes. How about the year change
2014-2016?
Quoted 8 lines
To change a license of a file, you need to get an ACK from every single
contributor to that file.
Year change I believe is fine.
[...]
Okay, noted.
Quoted 22 lines
Quoted 22 lines
Quoted 8 lines
Quoted 8 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +0 -0
@@ -89,6 +120,95 @@
 		" root=${qspiroot} rw
 rootfstype=${qspirootfstype};"\
 		"bootm ${loadaddr} - ${fdt_addr}\0"
 
Quoted 9 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h line 126
Quoted 5 lines
arch/arm/mach-socfpga/include/mach/base_addr_a10.h +3 -2
-/* The rest of the configuration is shared */
-#include <configs/socfpga_common.h>
+/*
+ * External memory configurations
+ */
Why is this being duplicated in board support code when it previously
was in common code ? That's just wrong.
I found that many conflicts between the board support code and common
code. It is safe for Arria10 having its own setting here. What do you
think?

Quoted 7 lines

Quoted 3 lines
It looks like 95% of the stuff below is the same as the stuff in socfpga-common.h , the rest can be pulled from DT or ifdef'd .
If socfpga-common.h is preferred, then i have to use ifdef method, are you ok with this? However, this would look a bit messy, because some #define setting in here, and other #define setting in socfpga-common.h under same category or peripheral configuration group.

Looks like there are only about two or three differences between the stuff below and socfpga_common.h , so just put it into common , it should be OK.

Quoted 108 lines

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +15 -0

+#define PHYS_SDRAM_1                   0x0
+#define PHYS_SDRAM_1_SIZE              0x80000000
+#define CONFIG_SYS_SDRAM_BASE          0
+#define CONFIG_NR_DRAM_BANKS           1
+#define CONFIG_SYS_MEMTEST_START       0
+#define CONFIG_SYS_MEMTEST_END         0x100000
+
+/*
+ * Serial / UART configurations
+ */
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_MEM32
+#define CONFIG_SYS_NS16550_REG_SIZE    -4
+#define CONFIG_SYS_NS16550_COM1        SOCFPGA_UART1_ADDRESS
+#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400,

57600, 115200}

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +10 -0

+#define CONFIG_SYS_NS16550_CLK         (50000000)
+#define CONFIG_CONS_INDEX              1
+#define CONFIG_BAUDRATE                115200
+
+/*
+ * L4 OSC1 Timer 0
+ */
+/* This timer use eosc1 where the clock frequency is fixed
+ * throughout any condition */
+#define CONFIG_SYS_TIMERBASE		SOCFPGA_SYSTIMER0_

ADDR
ESS

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +3 -0

+/* address of timer counter value */
+#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE
+

0x4)

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +14 -0

+/* reload value when timer count to zero */
+#define TIMER_LOAD_VAL			0xFFFFFFFF
+/* Clocks source frequency to timer */
+#define CONFIG_SYS_TIMER_RATE		(25000000)
+
+/* DesignWare timer is a countdown timer */
+#define CONFIG_SYS_TIMER_COUNTS_DOWN
+
+/*
+ * L4 Watchdog configurations
+ */
+#ifdef CONFIG_HW_WATCHDOG
+#define CONFIG_DESIGNWARE_WATCHDOG
+#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRES

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +2 -0

+#define CONFIG_HPS_CLK_OSC1_HZ	25000000
+#define CONFIG_DW_WDT_CLOCK_KHZ		(CONFIG_HPS_CLK

_OSC
1_HZ / 1000)

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +26 -0

+#define CONFIG_HW_WATCHDOG_TIMEOUT_MS	(2000)
+#endif
+
+/*
+ * SDMMC configurations
+ */
+#ifdef CONFIG_CMD_MMC
+#define CONFIG_MMC
+#define CONFIG_BOUNCE_BUFFER
+#define CONFIG_GENERIC_MMC
+#define CONFIG_DWMMC
+#define CONFIG_SOCFPGA_DWMMC
+#define CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH        1024
+#define CONFIG_SYS_MMC_MAX_BLK_COUNT           256
+#endif
+
+/*
+ * Flash configurations
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS     1
+#define CONFIG_SYS_NO_FLASH
+
+/* SPL configuration */
+#define CONFIG_SPL_FRAMEWORK
+#define CONFIG_SPL_RAM_DEVICE
+#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RA

M_AD
DR
+#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_
INIT
_RAM_SIZE

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +13 -0

+
+#ifdef CONFIG_SPL_BUILD
+#define CONFIG_SYS_MALLOC_SIMPLE
+#endif
+
+#ifdef CONFIG_SPL_NAND_DENALI
+#define CONFIG_SPL_NAND_SUPPORT
+#endif
+
+/*
+ * Stack setup
+ */
+#define CONFIG_SPL_STACK			CONFIG_SYS_INI

T_SP
_ADDR

arch/arm/mach-socfpga/include/mach/base_addr_a10.h +4 -0

+
+/* SPL SDMMC boot support */
+#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION     1
+#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME                "u-

boot-
dtb.img"
+
#endif /* __CONFIG_H */

Signature · 2 lines

Best regards,
Marek Vasut