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arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

PATCH New Chee Tien Fong 4 participants 6 messages Dec 6, 2016 – Dec 21, 2016

Subsystems (3)
Arm (32-bit) Arm sub-architectures Arm/socfpga architecture
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Chee Tien Fong

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#0 lore raw

PATCH 10/10 arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

From: Tien Fong Chee <[email protected]>

This patch adding the Arria10 critical hardware initialization before enabling console print out in spl.

Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 arch/arm/mach-socfpga/spl.c |   86 +++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 83 insertions(+), 3 deletions(-)
arch/arm/mach-socfpga/spl.c +83 -3
index fec4c7a..9375514 100644
@@ -1,7 +1,7 @@
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0
  */
 
 #include <common.h>

@@ -19,22 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <watchdog.h>
+#include <fdtdec.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
 	const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 	switch (bsel & 0x7) {
 	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
 		return BOOT_DEVICE_RAM;

@@ -55,6 +65,24 @@ u32 spl_boot_device(void)
 		printf("Invalid boot device (bsel=%08x)!\n", bsel);
 		hang();
 	}
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+	switch ((bsel>>12) & 0x7) {
+	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
+		return BOOT_DEVICE_RAM;
+	case 0x2:	/* NAND Flash (1.8V) */
+	case 0x3:	/* NAND Flash (3.0V) */
+		return BOOT_DEVICE_NAND;
+	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
+	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
+		return BOOT_DEVICE_MMC1;
+	case 0x6:	/* QSPI Flash (1.8V) */
+	case 0x7:	/* QSPI Flash (3.0V) */
+		return BOOT_DEVICE_SPI;
+	default:
+		printf("Invalid boot device (bsel=%08x)!\n", bsel);
+		hang();
+	}
+#endif
 }
 
 #ifdef CONFIG_SPL_MMC_SUPPORT

@@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
 	writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -182,3 +211,54 @@ void board_init_f(ulong dummy)
 	/* Configure simple malloc base pointer into RAM. */
 	gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	/*
+	 * Configure Clock Manager to use intosc clock instead external osc to
+	 * ensure success watchdog operation. We do it as early as possible.
+	 */
+	cm_use_intosc();
+
+	watchdog_disable();
+
+	arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* release osc1 watchdog timer 0 from reset */
+	reset_deassert_osc1wd0();
+
+	/* reconfigure and enable the watchdog */
+	hw_watchdog_init();
+	WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL
+	/* We need to access to FDT as this stage */
+	/* FDT is at end of image */
+	gd->fdt_blob = (void *)(__bss_end);
+	/* Check whether we have a valid FDT or not. */
+	if (fdtdec_prepare_fdt()) {
+		panic("** CONFIG_OF_CONTROL defined but no FDT - please see "
+			"doc/README.fdt-control");
+	}
+#endif /* CONFIG_OF_CONTROL */
+
+	/* Initialize the timer */
+	timer_init();
+
+	/* configuring the clock based on handoff */
+	cm_basic_init(gd->fdt_blob);
+	WATCHDOG_RESET();
+
+	config_dedicated_pins(gd->fdt_blob);
+	WATCHDOG_RESET();
+
+	/* configure the Reset Manager */
+	reset_deassert_dedicated_peripherals();
+
+	/* enable console uart printing */
+	preloader_console_init();
+}
+#endif
Signature · 1 line
1.7.7.4
#1 lore raw

PATCH 10/10 arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

arch/arm/mach-socfpga/spl.c

Quoted 20 lines · Chee Tien Fong

From: Tien Fong Chee <[email protected]>

This patch adding the Arria10 critical hardware initialization before enabling console print out in spl.

Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>

---
?arch/arm/mach-socfpga/spl.c |???86
+++++++++++++++++++++++++++++++++++++++++-
?1 files changed, 83 insertions(+), 3 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index fec4c7a..9375514 100644

arch/arm/mach-socfpga/spl.c +0 -0

Any comments on this patch before i start the version 2?

Quoted 135 lines
arch/arm/mach-socfpga/spl.c +0 -0
@@ -1,7 +1,7 @@

?/*
- *??Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *??Copyright (C) 2012-2016 Altera Corporation <www.altera.com> ? *
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0
? */
?
?#include <common.h>

arch/arm/mach-socfpga/spl.c +0 -0
@@ -19,22 +19,32 @@

?#include <asm/arch/sdram.h>
?#include <asm/arch/scu.h>
?#include <asm/arch/nic301.h>

arch/arm/mach-socfpga/spl.c +6 -0
+#include <asm/sections.h>
+#include <watchdog.h>
+#include <fdtdec.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif

?
?DECLARE_GLOBAL_DATA_PTR;
?
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
?static struct pl310_regs *const pl310 =
? (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
?static struct scu_registers *scu_regs =
? (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
?static struct nic301_registers *nic301_regs =
? (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;

arch/arm/mach-socfpga/spl.c +3 -1
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =

? (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
?
?u32 spl_boot_device(void)
?{
? const u32 bsel = readl(&sysmgr_regs->bootinfo);
?
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
? switch (bsel & 0x7) {
? case 0x1: /* FPGA (HPS2FPGA Bridge) */
? return BOOT_DEVICE_RAM;

arch/arm/mach-socfpga/spl.c +18 -0
@@ -55,6 +65,24 @@ u32 spl_boot_device(void)
 ?		printf("Invalid boot device (bsel=%08x)!\n", bsel);
 ?		hang();
 ?	}
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+	switch ((bsel>>12) & 0x7) {
+	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
+		return BOOT_DEVICE_RAM;
+	case 0x2:	/* NAND Flash (1.8V) */
+	case 0x3:	/* NAND Flash (3.0V) */
+		return BOOT_DEVICE_NAND;
+	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
+	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
+		return BOOT_DEVICE_MMC1;
+	case 0x6:	/* QSPI Flash (1.8V) */
+	case 0x7:	/* QSPI Flash (3.0V) */
+		return BOOT_DEVICE_SPI;
+	default:
+		printf("Invalid boot device (bsel=%08x)!\n", bsel);
+		hang();
+	}
+#endif
 ?}

?
?#ifdef CONFIG_SPL_MMC_SUPPORT

arch/arm/mach-socfpga/spl.c +0 -0
@@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device)
 ?}

?#endif
?
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
?static void socfpga_nic301_slave_ns(void)
?{
? writel(0x1, &nic301_regs->lwhps2fpgaregs);

arch/arm/mach-socfpga/spl.c +0 -0
@@ -182,3 +211,54 @@ void board_init_f(ulong dummy)

? /* Configure simple malloc base pointer into RAM. */
? gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
?}

arch/arm/mach-socfpga/spl.c +6 -0
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	/*
+	?* Configure Clock Manager to use intosc clock instead

external osc to

arch/arm/mach-socfpga/spl.c +1 -0
+	?* ensure success watchdog operation. We do it as early as

possible.

arch/arm/mach-socfpga/spl.c +23 -0
+	?*/
+	cm_use_intosc();
+
+	watchdog_disable();
+
+	arch_early_init_r();
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* release osc1 watchdog timer 0 from reset */
+	reset_deassert_osc1wd0();
+
+	/* reconfigure and enable the watchdog */
+	hw_watchdog_init();
+	WATCHDOG_RESET();
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL
+	/* We need to access to FDT as this stage */
+	/* FDT is at end of image */
+	gd->fdt_blob = (void *)(__bss_end);
+	/* Check whether we have a valid FDT or not. */
+	if (fdtdec_prepare_fdt()) {
+		panic("** CONFIG_OF_CONTROL defined but no FDT -

please see "

arch/arm/mach-socfpga/spl.c +21 -0
+			"doc/README.fdt-control");
+	}
+#endif /* CONFIG_OF_CONTROL */
+
+	/* Initialize the timer */
+	timer_init();
+
+	/* configuring the clock based on handoff */
+	cm_basic_init(gd->fdt_blob);
+	WATCHDOG_RESET();
+
+	config_dedicated_pins(gd->fdt_blob);
+	WATCHDOG_RESET();
+
+	/* configure the Reset Manager */
+	reset_deassert_dedicated_peripherals();
+
+	/* enable console uart printing */
+	preloader_console_init();
+}
+#endif
#2 lore raw

PATCH 10/10 arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

Quoted 16 lines · Tien Fong
Quoted 15 lines · Chee Tien Fong

From: Tien Fong Chee <[email protected]>

This patch adding the Arria10 critical hardware initialization before enabling console print out in spl.

Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 arch/arm/mach-socfpga/spl.c |   86
+++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 83 insertions(+), 3 deletions(-)
Quoted 6 lines

arch/arm/mach-socfpga/spl.c

Quoted 5 lines
arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index fec4c7a..9375514 100644

arch/arm/mach-socfpga/spl.c +0 -0

Any comments on this patch before i start the version 2?

This patch will probably need changes to work with v2, so I'll review it then.

Signature · 2 lines
Best regards,
Marek Vasut
maintainer
#3 lore raw

PATCH 10/10 arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

In reply to Chee
Quoted 16 lines · Tien Fong
Quoted 15 lines · Chee Tien Fong

From: Tien Fong Chee <[email protected]>

This patch adding the Arria10 critical hardware initialization before enabling console print out in spl.

Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 arch/arm/mach-socfpga/spl.c |   86
+++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 83 insertions(+), 3 deletions(-)
Quoted 7 lines

arch/arm/mach-socfpga/spl.c

Quoted 5 lines
arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index fec4c7a..9375514 100644

arch/arm/mach-socfpga/spl.c +0 -0

Any comments on this patch before i start the version 2?

I know that the license change will need to be reverted, but let me review it again.

Dinh

maintainer
#4 lore raw

PATCH 10/10 arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

In reply to Chee Tien Fong
Quoted 19 lines · Chee Tien Fong

From: Tien Fong Chee <[email protected]>

This patch adding the Arria10 critical hardware initialization before enabling console print out in spl.

Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>
---
 arch/arm/mach-socfpga/spl.c |   86 +++++++++++++++++++++++++++++++++++++++++-
 1 files changed, 83 insertions(+), 3 deletions(-)
arch/arm/mach-socfpga/spl.c +0 -0
index fec4c7a..9375514 100644

arch/arm/mach-socfpga/spl.c line 5

Quoted 7 lines
arch/arm/mach-socfpga/spl.c +2 -2
@@ -1,7 +1,7 @@
 /*
- *  Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *  Copyright (C) 2012-2016 Altera Corporation <www.altera.com>
  *
- * SPDX-License-Identifier:	GPL-2.0+
+ * SPDX-License-Identifier:	GPL-2.0
  */

Shouldn't be changing the license.

arch/arm/mach-socfpga/spl.c line 27

Quoted 12 lines
arch/arm/mach-socfpga/spl.c +6 -0
 #include <common.h>

@@ -19,22 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <watchdog.h>
+#include <fdtdec.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif

I don't know about all these includes, do you really need them? I don't see where you would need pinmux.h in this patch.

Quoted 37 lines
arch/arm/mach-socfpga/spl.c +14 -1
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
 	const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 	switch (bsel & 0x7) {
 	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
 		return BOOT_DEVICE_RAM;

@@ -55,6 +65,24 @@ u32 spl_boot_device(void)
 		printf("Invalid boot device (bsel=%08x)!\n", bsel);
 		hang();
 	}
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+	switch ((bsel>>12) & 0x7) {
+	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
+		return BOOT_DEVICE_RAM;
+	case 0x2:	/* NAND Flash (1.8V) */
+	case 0x3:	/* NAND Flash (3.0V) */
+		return BOOT_DEVICE_NAND;
+	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
+	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */

arch/arm/mach-socfpga/spl.c u32 spl_boot_device(void) · line 86

Quoted 10 lines
arch/arm/mach-socfpga/spl.c +9 -0
+		return BOOT_DEVICE_MMC1;
+	case 0x6:	/* QSPI Flash (1.8V) */
+	case 0x7:	/* QSPI Flash (3.0V) */
+		return BOOT_DEVICE_SPI;
+	default:
+		printf("Invalid boot device (bsel=%08x)!\n", bsel);
+		hang();
+	}
+#endif
 }

You should just do a shift define here, so you don't have to add all this extra code here. Something like

	switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7)
Quoted 15 lines
arch/arm/mach-socfpga/spl.c +2 -0
 #ifdef CONFIG_SPL_MMC_SUPPORT

@@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
 	writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -182,3 +211,54 @@ void board_init_f(ulong dummy)
 	/* Configure simple malloc base pointer into RAM. */
 	gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
 }
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 224

Quoted 10 lines
arch/arm/mach-socfpga/spl.c +10 -0
+void board_init_f(ulong dummy)
+{
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	/*
+	 * Configure Clock Manager to use intosc clock instead external osc to
+	 * ensure success watchdog operation. We do it as early as possible.
+	 */
+	cm_use_intosc();
+
+	watchdog_disable();

Why?

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 226

Quoted 2 lines
arch/arm/mach-socfpga/spl.c +2 -0
+
+	arch_early_init_r();

I don't think you should be calling this here.

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 234

Quoted 8 lines
arch/arm/mach-socfpga/spl.c +8 -0
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* release osc1 watchdog timer 0 from reset */
+	reset_deassert_osc1wd0();
+
+	/* reconfigure and enable the watchdog */
+	hw_watchdog_init();
+	WATCHDOG_RESET();

Do you really need all these WATCHDOG_RESET()'s?

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 237

Quoted 3 lines
arch/arm/mach-socfpga/spl.c +3 -0
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL

There's no need for this #ifdef. If you build for ARCH_SOCFPGA is OF_CONTROL selected.

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 238

Quoted 1 line
arch/arm/mach-socfpga/spl.c +1 -0
+	/* We need to access to FDT as this stage */

Why?

Dinh

#5 lore raw

PATCH 10/10 arm: socfpga: arria10: Added Arria10 critical HW initialization to spl

Quoted 19 lines · Dinh Nguyen
Quoted 17 lines · Chee Tien Fong

From: Tien Fong Chee <[email protected]>

This patch adding the Arria10 critical hardware initialization before
enabling console print out in spl.

Signed-off-by Tien Fong Chee <[email protected]>
Cc Marek Vasut <[email protected]>
Cc Dinh Nguyen <[email protected]>
Cc Chin Liang See <[email protected]>
Cc Tien Fong <[email protected]>

---
?arch/arm/mach-socfpga/spl.c |???86
+++++++++++++++++++++++++++++++++++++++++-
?1 files changed, 83 insertions(+), 3 deletions(-)

Quoted 15 lines
Quoted 6 lines
arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index fec4c7a..9375514 100644

arch/arm/mach-socfpga/spl.c +0 -0
@@ -1,7 +1,7 @@
Quoted 7 lines

?/*
- *??Copyright (C) 2012 Altera Corporation <www.altera.com>
+ *??Copyright (C) 2012-2016 Altera Corporation <www.altera.com> ? *
- * SPDX-License-Identifier: GPL-2.0+
+ * SPDX-License-Identifier: GPL-2.0
? */

Shouldn't be changing the license.

Yeah, i will revert it.

Quoted 17 lines

arch/arm/mach-socfpga/spl.c line 27

Quoted 13 lines

?#include <common.h>

arch/arm/mach-socfpga/spl.c +0 -0
@@ -19,22 +19,32 @@

?#include <asm/arch/sdram.h>
?#include <asm/arch/scu.h>
?#include <asm/arch/nic301.h>

arch/arm/mach-socfpga/spl.c +6 -0
+#include <asm/sections.h>
+#include <watchdog.h>
+#include <fdtdec.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif

I don't know about all these includes, do you really need them? I don't?
see where you would need pinmux.h in this patch.

Yeah, we those header, otherwise compilation failed.
we need pinmux.h also, because there is a function?config_dedicated_pins(gd->fdt_blob); in void board_init_f(ulong dummy). This function would configure the dedicated IO such as UART IO before enable print console.

Quoted 77 lines
Quoted 40 lines

?DECLARE_GLOBAL_DATA_PTR;

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
?static struct pl310_regs *const pl310 =
? (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
?static struct scu_registers *scu_regs =
? (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
?static struct nic301_registers *nic301_regs =
? (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;

arch/arm/mach-socfpga/spl.c +3 -1
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =

? (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

?u32 spl_boot_device(void)
?{
? const u32 bsel = readl(&sysmgr_regs->bootinfo);

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
? switch (bsel & 0x7) {
? case 0x1: /* FPGA (HPS2FPGA Bridge) */
? return BOOT_DEVICE_RAM;

arch/arm/mach-socfpga/spl.c +10 -0
@@ -55,6 +65,24 @@ u32 spl_boot_device(void)
 ?		printf("Invalid boot device (bsel=%08x)!\n",
 bsel);
 ?		hang();
 ?	}
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+	switch ((bsel>>12) & 0x7) {
+	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
+		return BOOT_DEVICE_RAM;
+	case 0x2:	/* NAND Flash (1.8V) */
+	case 0x3:	/* NAND Flash (3.0V) */
+		return BOOT_DEVICE_NAND;
+	case 0x4:	/* SD/MMC External Transceiver (1.8V) */
+	case 0x5:	/* SD/MMC Internal Transceiver (3.0V) */
+		return BOOT_DEVICE_MMC1;

arch/arm/mach-socfpga/spl.c u32 spl_boot_device(void) · line 88

Quoted 10 lines
arch/arm/mach-socfpga/spl.c +8 -0
+	case 0x6:	/* QSPI Flash (1.8V) */
+	case 0x7:	/* QSPI Flash (3.0V) */
+		return BOOT_DEVICE_SPI;
+	default:
+		printf("Invalid boot device (bsel=%08x)!\n",
 bsel);
+		hang();
+	}
+#endif
 ?}

You should just do a shift define??here, so you don't have to add all?
this extra code here. Something like

	switch ((bsel >> BOOTINFO_BSEL_SHIFT) & 0x7)
Quoted 21 lines

?#ifdef CONFIG_SPL_MMC_SUPPORT

arch/arm/mach-socfpga/spl.c +0 -0
@@ -68,6 +96,7 @@ u32 spl_boot_mode(const u32 boot_device)
 ?}

?#endif

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
?static void socfpga_nic301_slave_ns(void)
?{
? writel(0x1, &nic301_regs->lwhps2fpgaregs);

arch/arm/mach-socfpga/spl.c +0 -0
@@ -182,3 +211,54 @@ void board_init_f(ulong dummy)

? /* Configure simple malloc base pointer into RAM. */
? gd->malloc_base = CONFIG_SYS_TEXT_BASE + (1024 * 1024);
?}

arch/arm/mach-socfpga/spl.c +6 -0
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+void board_init_f(ulong dummy)
+{
+	memset(__bss_start, 0, __bss_end - __bss_start);
+	/*
+	?* Configure Clock Manager to use intosc clock instead
Quoted 9 lines

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 224

Quoted 7 lines

external osc to

arch/arm/mach-socfpga/spl.c +1 -0
+	?* ensure success watchdog operation. We do it as early as

possible.

arch/arm/mach-socfpga/spl.c +4 -0
+	?*/
+	cm_use_intosc();
+
+	watchdog_disable();

Why?

Disabled watchdog for watchdog configuration, this cater for scenario watchdog already starting running such as warm reset.

Quoted 5 lines

arch/arm/mach-socfpga/spl.c

Quoted 3 lines
arch/arm/mach-socfpga/spl.c +2 -0
+
+	arch_early_init_r();

I don't think you should be calling this here.

This function contains security policies initialization(before accessing any slaves), asserting reset to all timers(L4) before HW configuration. This is to ensure no firewall blocking on slave, timer in idle state after power up/warm reset.

Quoted 18 lines

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 234

Quoted 9 lines
arch/arm/mach-socfpga/spl.c +8 -0
+
+#ifdef CONFIG_HW_WATCHDOG
+	/* release osc1 watchdog timer 0 from reset */
+	reset_deassert_osc1wd0();
+
+	/* reconfigure and enable the watchdog */
+	hw_watchdog_init();
+	WATCHDOG_RESET();

Do you really need all these WATCHDOG_RESET()'s?

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 237

Quoted 4 lines
arch/arm/mach-socfpga/spl.c +3 -0
+#endif /* CONFIG_HW_WATCHDOG */
+
+#ifdef CONFIG_OF_CONTROL

There's no need for this #ifdef. If you build for ARCH_SOCFPGA is? OF_CONTROL selected.

Quoted 1 line
Quoted 3 lines

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 238

Quoted 1 line
arch/arm/mach-socfpga/spl.c +1 -0
+	/* We need to access to FDT as this stage */

Why?

we have dedicated IO configuration and clock configuration based on handoff data in FDT.

Quoted 1 line

Dinh