mx6qsabreauto: Fix the EIM clock for the mx6qp variant

-----Original Message-----
From: Fabio Estevam [mailto:festevam at gmail.com]
Sent: Tuesday, December 27, 2016 9:05 AM
To: sbabic at denx.de
Cc: Peng Fan <[email protected]>; u-boot at lists.denx.de; Fabio Estevam <[email protected]>
Subject: [PATCH] mx6qsabreauto: Fix the EIM clock for the mx6qp variant

From: Fabio Estevam <[email protected]>

On the MX6Q the aclk_eim_slow_podf field is '1' after POR, while on the MX6DQP it is '3'.

This makes the EIM clock to be only 66MHz on the mx6qp variant, instead of 132 MHz.

Instead of relying on the POR values for the CSMR1 register, make sure to manually configure the clk_eim_slow_sel field as '00' so that EIM clock is derived from AXI clock and the aclk_eim_slow_podf field as '1' so that EIM clock can be AXI clock divided by 2.

This way a consistent EIM clock frequency is configured for all the mx6 variants.

Signed-off-by Fabio Estevam <[email protected]>

From: Fabio Estevam <[email protected]>

On the MX6Q the aclk_eim_slow_podf field is '1' after POR, while on the MX6DQP it is '3'.

This makes the EIM clock to be only 66MHz on the mx6qp variant, instead of 132 MHz.

Instead of relying on the POR values for the CSMR1 register, make sure to manually configure the clk_eim_slow_sel field as '00' so that EIM clock is derived from AXI clock and the aclk_eim_slow_podf field as '1' so that EIM clock can be AXI clock divided by 2.

This way a consistent EIM clock frequency is configured for all the mx6 variants.

Signed-off-by Fabio Estevam <[email protected]>

---
 board/freescale/mx6qsabreauto/mx6qsabreauto.c | 28 +++++++++++++++++++++++++++
 1 file changed, 28 insertions(+)

board/freescale/mx6qsabreauto/mx6qsabreauto.c +27 -0

index 5fca4d1..51bbbc4 100644
@@ -231,6 +231,33 @@ static void eimnor_cs_setup(void)
 	set_chipselect_size(CS0_128);
 }
 
+static void eim_clk_setup(void)
+{
+	struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
+	int cscmr1, ccgr6;
+
+
+	/* Turn off EIM clock */
+	ccgr6 = readl(&imx_ccm->CCGR6);
+	ccgr6 &= ~(0x3 << 10);
+	writel(ccgr6, &imx_ccm->CCGR6);
+
+	/*
+	 * Configure clk_eim_slow_sel = 00 --> derive clock from AXI clk root
+	 * and aclk_eim_slow_podf = 01 --> divide by 2
+	 * so that we can have EIM at the maximum clock of 132MHz
+	 */
+	cscmr1 = readl(&imx_ccm->cscmr1);
+	cscmr1 &= ~(MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK |
+		    MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK);
+	cscmr1 |= (1 << MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET);
+	writel(cscmr1, &imx_ccm->cscmr1);
+
+	/* Turn on EIM clock */
+	ccgr6 |= (0x3 << 10);
+	writel(ccgr6, &imx_ccm->CCGR6);
+}
+
 static void setup_iomux_eimnor(void)
 {
 	imx_iomux_v3_setup_multiple_pads(eimnor_pads, ARRAY_SIZE(eimnor_pads));