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ARM64: Add support for FSL's LS2085A SoC

PATCH Superseded Bhupesh Sharma 3 participants 11 messages Nov 15, 2014 – Nov 16, 2014

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v5 of 7 Superseded Latest is v7 →

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v5 cover ARM64: Add support for FSL's LS2085A SoC

This patchset adds the support for FSL's LS2085A SoC which is based on ARMv8 architecture.

This patchset also has patches which address DT compatible strings for nodes which appear un-documented.

The enable-method for the CPU nodes is left for the bootloader (u-boot or UEFI) to patch-up which is expected to be PSCI v0.2

This patchset has been tested with the following patches which add PSCI v0.2 support in ARMv8 u-boot:
http://patchwork.ozlabs.org/patch/383556/
http://patchwork.ozlabs.org/patch/383555/
http://patchwork.ozlabs.org/patch/383557/
http://patchwork.ozlabs.org/patch/383558/
http://patchwork.ozlabs.org/patch/383559/
http://patchwork.ozlabs.org/patch/383560/
http://patchwork.ozlabs.org/patch/383561/
http://patchwork.ozlabs.org/patch/383562/

Rebased against v3.18-rc4

Changes from v4:
----------------
* Addressed review comments:
- Multi-line comment style fix.
- Rebasing related changes.
- Added Mark's Acked-by for patch 1/6
* Note that optional GIC-500 regs like GICC, GICH and GICV are currently not tested and hence are not part of the DTS patch.

[1] https://patchwork.ozlabs.org/patch/385246/

Bhupesh Sharma (6):
Documentation: DT: Add bindings for FSL NS16550A UART
Documentation: DT: Add entry for FSL LS2085A SoC and Simulator model
Documentation: DT: Add entry for FSL Management Complex
arm64: Add DTS support for FSL's LS2085A SoC
arm64: dts/Makefile: Add support for FSL's LS2085A simulator model
arm64: Add support for FSL's LS2085A SoC in Kconfig and defconfig

 Documentation/devicetree/bindings/arm/fsl.txt      |    8 +
 .../devicetree/bindings/misc/fsl,qoriq-mc.txt      |   40 +++++
 .../devicetree/bindings/serial/of-serial.txt       |   12 ++
 arch/arm64/Kconfig                                 |    5 +
 arch/arm64/boot/dts/Makefile                       |    1 +
 arch/arm64/boot/dts/fsl-ls2085a-simu.dts           |   65 ++++++++
 arch/arm64/boot/dts/fsl-ls2085a.dtsi               |  163 ++++++++++++++++++++
 arch/arm64/configs/defconfig                       |    1 +
 8 files changed, 295 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
 create mode 100644 arch/arm64/boot/dts/fsl-ls2085a-simu.dts
 create mode 100644 arch/arm64/boot/dts/fsl-ls2085a.dtsi
Signature · 1 line
1.7.9.5
#1 lore raw

PATCH v5 1/6 Documentation: DT: Add bindings for FSL NS16550A UART

This patch addss the device-tree documentation for Freescale's NS16550 UART (also called DUART).

There is a specific errata fix required in FSL NS16550 UART which ensures that an random interrupt storm is not observed when a break is provided as an input to the UART.

---
 .../devicetree/bindings/serial/of-serial.txt       |   12 ++++++++++++
 1 file changed, 12 insertions(+)
Documentation/devicetree/bindings/serial/of-serial.txt +12 -0
index 8c4fd03..1b3220b 100644
@@ -15,6 +15,7 @@ Required properties:
 	- "altr,16550-FIFO64"
 	- "altr,16550-FIFO128"
 	- "fsl,16550-FIFO64"
+	- "fsl,ns16550"
 	- "serial" if the port type is unknown.
 - reg : offset and length of the register set for the device.
 - interrupts : should contain uart interrupt.
@@ -39,6 +40,17 @@ Optional properties:
   driver is allowed to detect support for the capability even without this
   property.
 
+Note:
+* fsl,ns16550:
+  ------------
+  Freescale DUART is very similar to the PC16552D (and to a
+  pair of NS16550A), albeit with some nonstandard behavior such as
+  erratum A-004737 (relating to incorrect BRK handling).
+
+  Represents a single port that is compatible with the DUART found
+  on many Freescale chips (examples include mpc8349, mpc8548,
+  mpc8641d, p4080 and ls2085a).
+
 Example:
 
 	uart at 80230000 {
Signature · 1 line
1.7.9.5
#2 lore raw

PATCH v5 2/6 Documentation: DT: Add entry for FSL LS2085A SoC and Simulator model

In reply to Bhupesh Sharma

This patch adds a devicetree binding documentation for FSL's LS2085A SoC and Simulator model.

---
 Documentation/devicetree/bindings/arm/fsl.txt |    8 ++++++++
 1 file changed, 8 insertions(+)
Documentation/devicetree/bindings/arm/fsl.txt +8 -0
index e935d7d..3b28c4d 100644
@@ -74,3 +74,11 @@ Required root node properties:
 i.MX6q generic board
 Required root node properties:
     - compatible = "fsl,imx6q";
+
+Freescale LS2085A SoC Device Tree Bindings
+------------------------------------------
+
+LS2085A ARMv8 based Simulator model
+Required root node properties:
+    - compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
+
Signature · 1 line
1.7.9.5
#3 lore raw

PATCH v5 3/6 Documentation: DT: Add entry for FSL Management Complex

In reply to Bhupesh Sharma

This patch adds a devicetree binding documentation for FSL's Management Complex.

Management Complex is a hardware resource manager that manages specialized hardware objects used in network-oriented packet processing applications

---
 .../devicetree/bindings/misc/fsl,qoriq-mc.txt      |   40 ++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt
Documentation/devicetree/bindings/misc/fsl,qoriq-mc.txt new file +40 -0
new file mode 100644
index 0000000..c7a26ca
@@ -0,0 +1,40 @@
+* Freescale Management Complex
+
+The Freescale Management Complex (fsl-mc) is a hardware resource
+manager that manages specialized hardware objects used in
+network-oriented packet processing applications. After the fsl-mc
+block is enabled, pools of hardware resources are available, such as
+queues, buffer pools, I/O interfaces. These resources are building
+blocks that can be used to create functional hardware objects/devices
+such as network interfaces, crypto accelerator instances, L2 switches,
+etc.
+
+Required properties:
+
+    - compatible
+        Value type: <string>
+        Definition: Must be "fsl,qoriq-mc".  A Freescale Management Complex
+                    compatible with this binding must have Block Revision
+                    Registers BRR1 and BRR2 at offset 0x0BF8 and 0x0BFC in
+                    the MC control register region.
+
+    - reg
+        Value type: <prop-encoded-array>
+        Definition: A standard property.  Specifies one or two regions
+                    defining the MC's registers:
+
+                       -the first region is the command portal for the
+                        this machine and must always be present
+
+                       -the second region is the MC control registers. This
+                        region may not be present in some scenarios, such
+                        as in the device tree presented to a virtual machine.
+
+Example:
+
+        fsl_mc: fsl-mc at 80c000000 {
+                compatible = "fsl,qoriq-mc";
+                reg = <0x00000008 0x0c000000 0 0x40>,    /* MC portal base */
+                      <0x00000000 0x08340000 0 0x40000>; /* MC control reg */
+        };
+
Signature · 1 line
1.7.9.5
#4 lore raw

PATCH v5 4/6 arm64: Add DTS support for FSL's LS2085A SoC

In reply to Bhupesh Sharma

This patch adds the device tree support for FSL LS2085A SoC based on ARMv8 architecture.

Following levels of DTSI/DTS files have been created for the LS2085A SoC family:

- fsl-ls2085a.dtsi:
DTS-Include file for FSL LS2085A SoC.

- fsl-ls2085a-simu.dts:
DTS file for FSL LS2085a software simulator model.

---
 arch/arm64/boot/dts/fsl-ls2085a-simu.dts |   65 ++++++++++++
 arch/arm64/boot/dts/fsl-ls2085a.dtsi     |  163 ++++++++++++++++++++++++++++++
 2 files changed, 228 insertions(+)
 create mode 100644 arch/arm64/boot/dts/fsl-ls2085a-simu.dts
 create mode 100644 arch/arm64/boot/dts/fsl-ls2085a.dtsi
arch/arm64/boot/dts/fsl-ls2085a-simu.dts new file +65 -0
new file mode 100644
index 0000000..82e2a6f
@@ -0,0 +1,65 @@
+/*
+ * Device Tree file for Freescale LS2085a software Simulator model
+ *
+ * Copyright (C) 2014, Freescale Semiconductor
+ *
+ * Bhupesh Sharma <[email protected]>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ *  a) This library is free software; you can redistribute it and/or
+ *     modify it under the terms of the GNU General Public License as
+ *     published by the Free Software Foundation; either version 2 of the
+ *     License, or (at your option) any later version.
+ *
+ *     This library is distributed in the hope that it will be useful,
+ *     but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *     GNU General Public License for more details.
+ *
+ *     You should have received a copy of the GNU General Public
+ *     License along with this library; if not, write to the Free
+ *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ *     MA 02110-1301 USA
+ *
+ * Or, alternatively,
+ *
+ *  b) Permission is hereby granted, free of charge, to any person
+ *     obtaining a copy of this software and associated documentation
+ *     files (the "Software"), to deal in the Software without
+ *     restriction, including without limitation the rights to use,
+ *     copy, modify, merge, publish, distribute, sublicense, and/or
+ *     sell copies of the Software, and to permit persons to whom the
+ *     Software is furnished to do so, subject to the following
+ *     conditions:
+ *
+ *     The above copyright notice and this permission notice shall be
+ *     included in all copies or substantial portions of the Software.
+ *
+ *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ *     OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+/include/ "fsl-ls2085a.dtsi"
+
+/ {
+	model = "Freescale Layerscape 2085a software Simulator model";
+	compatible = "fsl,ls2085a-simu", "fsl,ls2085a";
+
+	ethernet at 2210000 {
+		compatible = "smsc,lan91c111";
+		reg = <0x0 0x2210000 0x0 0x100>;
+		interrupts = <0 58 0x1>;
+	};
+};
arch/arm64/boot/dts/fsl-ls2085a.dtsi new file +163 -0

163 lines not on this page · raw message

Signature · 1 line
1.7.9.5
#5 lore raw

PATCH v5 4/6 arm64: Add DTS support for FSL's LS2085A SoC

Quoted 22 lines · Bhupesh Sharma

This patch adds the device tree support for FSL LS2085A SoC based on ARMv8 architecture.

Following levels of DTSI/DTS files have been created for the LS2085A SoC family:

- fsl-ls2085a.dtsi:
DTS-Include file for FSL LS2085A SoC.

- fsl-ls2085a-simu.dts:
DTS file for FSL LS2085a software simulator model.

---
 arch/arm64/boot/dts/fsl-ls2085a-simu.dts |   65 ++++++++++++
 arch/arm64/boot/dts/fsl-ls2085a.dtsi     |  163 ++++++++++++++++++++++++++++++
 2 files changed, 228 insertions(+)
 create mode 100644 arch/arm64/boot/dts/fsl-ls2085a-simu.dts
 create mode 100644 arch/arm64/boot/dts/fsl-ls2085a.dtsi

[...]

Quoted 6 lines
arch/arm64/boot/dts/fsl-ls2085a.dtsi new file +0 -0
new file mode 100644
index 0000000..5ff3d77

[...]

Quoted 18 lines
arch/arm64/boot/dts/fsl-ls2085a.dtsi new file +18 -0
+	cpus {
+		#address-cells = <2>;
+		#size-cells = <0>;
+
+		/*
+		 * We expect the enable-method for cpu's to be "psci", but this
+		 * is dependent on the SoC FW, which will fill this in.
+		 *
+		 * Currently supported enable-method is psci v0.2
+		 */
+
+		/* We have 4 clusters having 2 Cortex-A57 cores each */
+		cpu at 0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-a57";
+			reg = <0x0 0x0>;
+		};
+

[...]

arch/arm64/boot/dts/fsl-ls2085a.dtsi line 139

Quoted 6 lines
arch/arm64/boot/dts/fsl-ls2085a.dtsi new file +6 -0
+	timer {
+		compatible = "arm,armv8-timer";
+ interrupts = <1 13 0x1>, /* Physical Secure PPI, edge triggered */
+ <1 14 0x1>, /* Physical Non-Secure PPI, edge triggered */
+			     <1 11 0x1>, /* Virtual PPI, edge triggered */
+			     <1 10 0x1>; /* Hypervisor PPI, edge triggered */

Are you sure about this "edge triggered"? The A57 TRM suggests otherwise:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0488g/way1382454511590.html

Thanks,

	M.
Signature · 1 line
Jazz is not dead. It just smells funny.
#6 lore raw

PATCH v5 5/6 arm64: dts/Makefile: Add support for FSL's LS2085A simulator model

In reply to Bhupesh Sharma

This patch adds build support for FSL's LS2085A simulator model in arm64 dts Makefile.

---
 arch/arm64/boot/dts/Makefile |    1 +
 1 file changed, 1 insertion(+)
arch/arm64/boot/dts/Makefile +1 -0
index f8001a6..c3b100f 100644
@@ -1,6 +1,7 @@
 dtb-$(CONFIG_ARCH_THUNDER) += thunder-88xx.dtb
 dtb-$(CONFIG_ARCH_VEXPRESS) += rtsm_ve-aemv8a.dtb foundation-v8.dtb
 dtb-$(CONFIG_ARCH_XGENE) += apm-mustang.dtb
+dtb-$(CONFIG_ARCH_FSL_LS2085A) += fsl-ls2085a-simu.dtb
 
 targets += dtbs
 targets += $(dtb-y)
Signature · 1 line
1.7.9.5
#7 lore raw

PATCH v5 6/6 arm64: Add support for FSL's LS2085A SoC in Kconfig and defconfig

In reply to Bhupesh Sharma

This patch adds support for FSL's LS2085A SoC in the arm64 Kconfig and defconfig files.

---
 arch/arm64/Kconfig           |    5 +++++
 arch/arm64/configs/defconfig |    1 +
 2 files changed, 6 insertions(+)
arch/arm64/Kconfig +5 -0
index 9532f8d..aefcdd2 100644
@@ -142,6 +142,11 @@ source "kernel/Kconfig.freezer"
 
 menu "Platform selection"
 
+config ARCH_FSL_LS2085A
+	bool "Freescale LS2085A SOC"
+	help
+	  This enables support for Freescale LS2085A SOC.
+
 config ARCH_THUNDER
 	bool "Cavium Inc. Thunder SoC Family"
 	help
arch/arm64/configs/defconfig +1 -0
index dd301be..76fc77e 100644
@@ -32,6 +32,7 @@ CONFIG_MODULES=y
 CONFIG_MODULE_UNLOAD=y
 # CONFIG_BLK_DEV_BSG is not set
 # CONFIG_IOSCHED_DEADLINE is not set
+CONFIG_ARCH_FSL_LS2085A=y
 CONFIG_ARCH_THUNDER=y
 CONFIG_ARCH_VEXPRESS=y
 CONFIG_ARCH_XGENE=y
Signature · 1 line
1.7.9.5
maintainer
#8 lore raw

v5 cover ARM64: Add support for FSL's LS2085A SoC

In reply to Bhupesh Sharma
Quoted 9 lines · On Saturday 15 November 2014 16:16:25 Bhupesh Sharma wrote:

This patchset adds the support for FSL's LS2085A SoC which is based on ARMv8 architecture.

This patchset also has patches which address DT compatible strings for nodes which appear un-documented.

The enable-method for the CPU nodes is left for the bootloader (u-boot or UEFI) to patch-up which is expected to be PSCI v0.2

Looks all good to me. Are you planning to send a pull request to arm at kernel.org, or should we pick up the patches directly (provided no more new review comments)?

Arnd

#9 lore raw

v5 cover ARM64: Add support for FSL's LS2085A SoC

Hi Arnd,

Quoted 18 lines

-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Saturday, November 15, 2014 4:32 PM
To: Sharma Bhupesh-B45370
Cc: Catalin.Marinas at arm.com; mark.rutland at arm.com; linux-arm- kernel at lists.infradead.org; grant.likely at secretlab.ca; marc.zyngier at arm.com; rob.herring at linaro.org; bhupesh.sharma at freescal.com; Yoder Stuart-B08248; arnab_basu at rocketmail.com
Subject: Re: [PATCH v5 0/6] ARM64: Add support for FSL's LS2085A SoC

Quoted 6 lines · On Saturday 15 November 2014 16:16:25 Bhupesh Sharma wrote:

This patchset adds the support for FSL's LS2085A SoC which is based on ARMv8 architecture.

This patchset also has patches which address DT compatible strings for nodes which appear un-documented.

Quoted 8 lines
Quoted 3 lines

The enable-method for the CPU nodes is left for the bootloader (u-boot or UEFI) to patch-up which is expected to be PSCI v0.2

Looks all good to me. Are you planning to send a pull request to arm at kernel.org, or should we pick up the patches directly (provided no more new review comments)?

It would be great if you can pick the patches directly (ofcourse, if there are no new comments).

Thanks for all your help.

Regards,
Bhupesh

maintainer
#10 lore raw

v5 cover ARM64: Add support for FSL's LS2085A SoC

Quoted 23 lines · On Saturday 15 November 2014 11:06:42 bhupesh.sharma at freescale.com wrote:
Quoted 23 lines

-----Original Message-----
From: Arnd Bergmann [mailto:arnd at arndb.de]
Sent: Saturday, November 15, 2014 4:32 PM
To: Sharma Bhupesh-B45370
Cc: Catalin.Marinas at arm.com; mark.rutland at arm.com; linux-arm- kernel at lists.infradead.org; grant.likely at secretlab.ca; marc.zyngier at arm.com; rob.herring at linaro.org; bhupesh.sharma at freescal.com; Yoder Stuart-B08248; arnab_basu at rocketmail.com
Subject: Re: [PATCH v5 0/6] ARM64: Add support for FSL's LS2085A SoC

Quoted 9 lines · On Saturday 15 November 2014 16:16:25 Bhupesh Sharma wrote:

This patchset adds the support for FSL's LS2085A SoC which is based on ARMv8 architecture.

This patchset also has patches which address DT compatible strings for nodes which appear un-documented.

The enable-method for the CPU nodes is left for the bootloader (u-boot or UEFI) to patch-up which is expected to be PSCI v0.2

Quoted 9 lines
Quoted 4 lines

Looks all good to me. Are you planning to send a pull request to arm at kernel.org, or should we pick up the patches directly (provided no more new review comments)?

It would be great if you can pick the patches directly (ofcourse, if there are no new comments).

Ok, let's wait a few more days then, once everyone is happy please send them "To: arm at kernel.org" with a request for us to merge them.

Arnd