meson-gx: reset RGMII PHYs and configure TX delay
Subsystems (2)
Martin Blumenstingl
reviewercover meson-gx: reset RGMII PHYs and configure TX delay
This partially fixes the 1000Mbit/s ethernet TX throughput issues (on networks which are not affected by the EEE problem, as reported here:
[1]).
The actual problem for the TX throughput issues was that the TX delay was applied twice:
- once "accidentally" by the PHY (this was fixed with [2])
- once by the MAC because there was a hardcoded TX delay (of 2ns), this will be configurable with the changes from [0]
These are the dts changes which belong to my other series (in v2 these patches were part of the other series, upon request of the net maintainers I have split the .dts changes into their own series so we are able to take both through different trees):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay": [0].
Thus this series depends on the ACK for the binding changes in the other series!
I based these changes on my other series "[PATCH v2 0/2] GXL and GXM SCPI improvements": [3]
[0] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/001834.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/001607.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/001707.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/001831.html
Martin Blumenstingl (5):
ARM64: dts: meson-gx: move the MDIO node to meson-gx
ARM64: dts: meson-gxbb-odroidc2: add reset for the ethernet PHY
ARM64: dts: meson-gxbb-p20x: add reset for the ethernet PHY
ARM64: dts: meson-gxbb-vega-s95: add reset for the ethernet PHY
ARM64: dts: amlogic: add the ethernet TX delay configuration
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 ++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts | 2 ++ 8 files changed, 63 insertions(+), 6 deletions(-)
Signature · 1 line
2.10.2
Martin Blumenstingl
reviewerPATCH 1/5 ARM64: dts: meson-gx: move the MDIO node to meson-gx
stmmac's MDIO bus is currently only defined in meson-gxl.dtsi. Move it up to meson-gx to allow us to keep the stmmac configuration for meson-gxbb similar to the configuration on meson-gxl.
--- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 ++++++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 6 ------ 2 files changed, 6 insertions(+), 6 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +6 -0
@@ -371,6 +371,12 @@ interrupt-names = "macirq"; phy-mode = "rgmii"; status = "disabled"; + + mdio0: mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + }; }; apb: apb at d0000000 {
arch/arm64/boot/dts/amlogic/meson-gxl.dtsi +0 -6
@@ -57,12 +57,6 @@ <&clkc CLKID_FCLK_DIV2>, <&clkc CLKID_MPLL2>; clock-names = "stmmaceth", "clkin0", "clkin1"; - - mdio0: mdio { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - }; }; &aobus {
Signature · 1 line
2.10.2
Martin Blumenstingl
reviewerPATCH 2/5 ARM64: dts: meson-gxbb-odroidc2: add reset for the ethernet PHY
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state. While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +15 -0
@@ -143,10 +143,25 @@ pinctrl-names = "default"; }; +&mdio0 { + ethernet_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + ðmac { status = "okay"; pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; + + phy-handle = <ðernet_phy0>; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + phy-mode = "rgmii"; }; &ir {
Signature · 1 line
2.10.2
Martin Blumenstingl
reviewerPATCH 3/5 ARM64: dts: meson-gxbb-p20x: add reset for the ethernet PHY
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state. While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +15 -0
@@ -134,10 +134,25 @@ pinctrl-names = "default"; }; +&mdio0 { + ethernet_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + ðmac { status = "okay"; pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; + + phy-handle = <ðernet_phy0>; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + phy-mode = "rgmii"; }; &ir {
Signature · 1 line
2.10.2
Jerome Brunet
reviewerPATCH 3/5 ARM64: dts: meson-gxbb-p20x: add reset for the ethernet PHY
Quoted 23 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean"
state. While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices.Signed-off-by Martin Blumenstingl <[email protected]m>
Tested-by Neil Armstrong <[email protected]>---
?arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 15
+++++++++++++++
?1 file changed, 15 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +0
-0@@ -134,10 +134,25 @@ ? pinctrl-names = "default"; ?};?
+&mdio0 {
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi line 140
Quoted 3 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +3
-0+ ethernet_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>;
Sorry for the late reply.
I just tried on the p200 and this patch (serie) breaks the network on it. The PHY is not detected anymore.
Quoted 1 line
From the KSZ9031 Datasheet : "PHY Address 0h is supported as the unique
PHY address only; it is not supported as the broadcast PHY address [...]"
So we can't just use the broadcast address here:
reg should be <3>.
Quoted 7 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +3
-0+ }; +}; +?ðmac {
? status = "okay";
? pinctrl-0 = <ð_rgmii_pins>;
? pinctrl-names = "default";
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi line 155
Quoted 8 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +8
-0+ + phy-handle = <ðernet_phy0>; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + phy-mode = "rgmii";
We can't define this in p20x. actually the p201 uses an rmii. I have not idea about gpio reset, or the phy address for the p201.
I suppose it would be better to move this to meson-gxbb_p200.dts
I don't know if anybody has a p201, but until we can confirm a working Ethernet configuration, we should probably drop it for the p201
Of course the problem was already there before this patch ...
Quoted 3 lines
?};
?
?&ir {
Martin Blumenstingl
reviewerPATCH 3/5 ARM64: dts: meson-gxbb-p20x: add reset for the ethernet PHY
Quoted 32 lines · Jerome Brunet
Quoted 19 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean"
state. While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices.Signed-off-by Martin Blumenstingl <[email protected]m>
Tested-by Neil Armstrong <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +0
-0arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi line 140
Quoted 7 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +4
-0@@ -134,10 +134,25 @@ pinctrl-names = "default"; }; +&mdio0 { + ethernet_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>;Sorry for the late reply.
I just tried on the p200 and this patch (serie) breaks the network on it. The PHY is not detected anymore.
Quoted 6 lines
From the KSZ9031 Datasheet : "PHY Address 0h is supported as the unique PHY address only; it is not supported as the broadcast PHY address [...]"
So we can't just use the broadcast address here:
reg should be <3>.
OK, I'll fix that in a follow-up. as mentioned in the other thread:
can you confirm that the PHY ID is 0x00221620?
It seems that I also broke meson-gxbb-nexbox-a95x.dts with that series (no idea why that slipped through): according to the photos from Neil's wiki [0] this seems to use an IC+ 10/100 ethernet PHY (probably an IP101A)
Quoted 19 lines
Quoted 5 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +3
-0+ }; +}; + ðmac { status = "okay";arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi line 155
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +8
-0pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; + + phy-handle = <ðernet_phy0>; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + phy-mode = "rgmii";We can't define this in p20x. actually the p201 uses an rmii. I have not idea about gpio reset, or the phy address for the p201.
Quoted 6 lines
I suppose it would be better to move this to
meson-gxbb_p200.dtsI don't know if anybody has a p201, but until we can confirm a working Ethernet configuration, we should probably drop it for the p201
Of course the problem was already there before this patch ...
indeed, that seems to be a problem.
the GXBB Nexbox A95x I mentioned above is based on the p201 board. Amlogic's .dts also toggles GPIOZ_14 for it: [1] chances are high that it also features an IP101A PHY (this is pure speculation though).
I propose four patches to fix all this situation:
- add the GPIOZ_14 reset and an ethernet_phy0 (with reg = <0>) to meson-gxbb-nexbox-a95x.dts
- add the ethernet_phy0 node with reg = <0> (and ideally I also want to include the KSZ9031 PHY ID) to meson-gxbb-p200.dtsi along with phy-mode = "rgmii"
- add the ethernet_phy0 node with reg = <0> (without any PHY ID as we don't know which one is used) to meson-gxbb-p201.dtsi along with phy-mode = "rgmii"
- remove "phy-mode" and ethernet_phy0 from meson-gxbb-p20x.dtsi and add a comment that both, the RGMII and the RMII PHY have GPIOZ_14 connected to their reset line
does that make sense?
Regards,
Martin
[0] https://github.com/superna9999/linux/wiki/Boards#nexbox-a95x-s905
[1] https://github.com/khadas/linux/blob/Vim/arch/arm64/boot/dts/amlogic/gxbb_p201.dts#L186
Jerome Brunet
reviewerPATCH 3/5 ARM64: dts: meson-gxbb-p20x: add reset for the ethernet PHY
Quoted 45 lines · Martin Blumenstingl
Quoted 43 lines · Jerome Brunet
Quoted 23 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean"
state. While here also specify the phy-handle of the ethmac node to
make the PHY configuration similar to the one we have on GXL devices.Signed-off-by Martin Blumenstingl <martin.blumenstingl@googlemail.co
m>Tested-by Neil Armstrong <[email protected]>---
?arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 15
+++++++++++++++
?1 file changed, 15 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +0
-0arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi line 140
Quoted 7 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +4
-0@@ -134,10 +134,25 @@ ??????pinctrl-names = "default"; ?}; +&mdio0 { +?????ethernet_phy0: ethernet-phy at 0 { +?????????????compatible = "ethernet-phy-ieee802.3-c22"; +?????????????reg = <0>;Sorry for the late reply.
I just tried on the p200 and this patch (serie) breaks the network on
it. The PHY is not detected anymore.From the KSZ9031 Datasheet : "PHY Address 0h is supported as the unique
PHY address only; it is not supported as the broadcast PHY address [...]"
Quoted 4 lines
Quoted 2 lines
So we can't just use the broadcast address here:
reg should be <3>.OK, I'll fix that in a follow-up. as mentioned in the other thread:
can you confirm that the PHY ID is0x00221620?
That's right.
Quoted 6 lines
It seems that I also broke
meson-gxbb-nexbox-a95x.dtswith that series
(no idea why that slipped through): according to the photos from Neil's wiki [0] this seems to use an IC+ 10/100 ethernet PHY (probably
an IP101A)
IP101GR from what I can see on the board.
Quoted 28 lines
Quoted 28 lines
Quoted 8 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +3
-0+?????}; +}; + ?ðmac { ??????status = "okay";arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi line 155
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +8
-0??????pinctrl-0 = <ð_rgmii_pins>; ??????pinctrl-names = "default"; + +?????phy-handle = <ðernet_phy0>; + +?????snps,reset-gpio = <&gpio GPIOZ_14 0>; +?????snps,reset-delays-us = <0 10000 1000000>; +?????snps,reset-active-low; + +?????phy-mode = "rgmii";We can't define this in p20x. actually the p201 uses an rmii. I have not idea about gpio reset, or the phy address for the p201.
I suppose it would be better to move this to
meson-gxbb_p200.dtsI don't know if anybody has a p201, but until we can confirm a working
Ethernet configuration, we should probably drop it for the p201
Quoted 6 lines
Quoted 1 line
Of course the problem was already there before this patch ...
indeed, that seems to be a problem.
the GXBB Nexbox A95x I mentioned above is based on the p201 board. Amlogic's .dts also togglesGPIOZ_14for it: [1] chances are high that it also features an IP101A PHY (this is pure speculation though).
Agreed, chances are high it'll be this way.
Quoted 7 lines
I propose four patches to fix all this situation:
- add theGPIOZ_14reset and anethernet_phy0(with reg = <0>) tomeson-gxbb-nexbox-a95x.dts
- add theethernet_phy0node with reg = <0> (and ideally I also want to include the KSZ9031 PHY ID) tomeson-gxbb-p200.dtsialong with phy-mode = "rgmii"
you mean with reg = <3> ?
Quoted 6 lines
- add the
ethernet_phy0node with reg = <0> (without any PHY ID as we don't know which one is used) tomeson-gxbb-p201.dtsialong with phy-mode = "rgmii"
- remove "phy-mode" andethernet_phy0frommeson-gxbb-p20x.dtsiand add a comment that both, the RGMII and the RMII PHY haveGPIOZ_14connected to their reset line
I'm not too sure about these last 2 points. As you mentioned, we are only speculating regarding the p201. I would prefer to avoid putting things we are not sure about in the DT (as much as possible).
We could disable the ethernet for p201:
1) if nobody complains, situation remains unchanged, ethernet is not working on that board
2) if someone complains, then we will be able to some facts from him/her, and get it working properly.
After all, that's not a regression. With what we had in the meson-gxbb- p20x.dtsi so far, ethernet never worked on that board.
?
Quoted 11 lines
does that make sense?
Regards,
Martin[0] https://github.com/superna9999/linux/wiki/Boards#nexbox-a95x-s905
[1] https://github.com/khadas/linux/blob/Vim/arch/arm64/boot/dts/amlo
gic/gxbb_p201.dts#L186
Martin Blumenstingl
reviewerPATCH 3/5 ARM64: dts: meson-gxbb-p20x: add reset for the ethernet PHY
Quoted 46 lines · Jerome Brunet
Quoted 45 lines · Martin Blumenstingl
Quoted 43 lines · Jerome Brunet
Quoted 23 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean"
state. While here also specify the phy-handle of the ethmac node to
make the PHY configuration similar to the one we have on GXL devices.Signed-off-by Martin Blumenstingl <martin.blumenstingl@googlemail.co
m>Tested-by Neil Armstrong <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +0
-0arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi line 140
Quoted 7 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +4
-0@@ -134,10 +134,25 @@ pinctrl-names = "default"; }; +&mdio0 { + ethernet_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <0>;Sorry for the late reply.
I just tried on the p200 and this patch (serie) breaks the network on
it. The PHY is not detected anymore.From the KSZ9031 Datasheet : "PHY Address 0h is supported as the unique
PHY address only; it is not supported as the broadcast PHY address [...]"
Quoted 6 lines
Quoted 4 lines
Quoted 2 lines
So we can't just use the broadcast address here:
reg should be <3>.OK, I'll fix that in a follow-up. as mentioned in the other thread:
can you confirm that the PHY ID is0x00221620?That's right.
thanks for confirming this
Quoted 8 lines
Quoted 6 lines
It seems that I also broke
meson-gxbb-nexbox-a95x.dtswith that series
(no idea why that slipped through): according to the photos from Neil's wiki [0] this seems to use an IC+ 10/100 ethernet PHY (probably
an IP101A)IP101GR from what I can see on the board.
thanks :)
Quoted 38 lines
Quoted 28 lines
Quoted 28 lines
Quoted 8 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +3
-0+ }; +}; + ðmac { status = "okay";arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi line 155
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +8
-0pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; + + phy-handle = <ðernet_phy0>; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + phy-mode = "rgmii";We can't define this in p20x. actually the p201 uses an rmii. I have not idea about gpio reset, or the phy address for the p201.
I suppose it would be better to move this to
meson-gxbb_p200.dtsI don't know if anybody has a p201, but until we can confirm a working
Ethernet configuration, we should probably drop it for the p201Quoted 6 lines
Quoted 1 line
Of course the problem was already there before this patch ...
indeed, that seems to be a problem.
the GXBB Nexbox A95x I mentioned above is based on the p201 board. Amlogic's .dts also togglesGPIOZ_14for it: [1] chances are high that it also features an IP101A PHY (this is pure speculation though).Agreed, chances are high it'll be this way.
Quoted 1 line
Quoted 8 lines
Quoted 6 lines
I propose four patches to fix all this situation:
- add theGPIOZ_14reset and anethernet_phy0(with reg = <0>) tomeson-gxbb-nexbox-a95x.dts
- add theethernet_phy0node with reg = <0> (and ideally I also want to include the KSZ9031 PHY ID) tomeson-gxbb-p200.dtsialong with phy-mode = "rgmii"you mean with reg = <3> ?
you're right, another typo there!
Quoted 11 lines
Quoted 6 lines
- add the
ethernet_phy0node with reg = <0> (without any PHY ID as we don't know which one is used) tomeson-gxbb-p201.dtsialong with phy-mode = "rgmii"
- remove "phy-mode" andethernet_phy0frommeson-gxbb-p20x.dtsiand add a comment that both, the RGMII and the RMII PHY haveGPIOZ_14connected to their reset lineI'm not too sure about these last 2 points. As you mentioned, we are only speculating regarding the p201. I would prefer to avoid putting things we are not sure about in the DT (as much as possible).
Quoted 8 lines
We could disable the ethernet for p201:
1) if nobody complains, situation remains unchanged, ethernet is not working on that board
2) if someone complains, then we will be able to some facts from him/her, and get it working properly.After all, that's not a regression. With what we had in the meson-gxbb-
p20x.dtsiso far, ethernet never worked on that board.
fine for me as well
Martin Blumenstingl
reviewerPATCH 4/5 ARM64: dts: meson-gxbb-vega-s95: add reset for the ethernet PHY
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state. While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +15 -0
@@ -113,10 +113,25 @@ pinctrl-names = "default"; }; +&mdio0 { + ethernet_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id001c.c916", "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; +}; + ðmac { status = "okay"; pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; + + phy-handle = <ðernet_phy0>; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + phy-mode = "rgmii"; }; &usb0_phy {
Signature · 1 line
2.10.2
Martin Blumenstingl
reviewerPATCH 5/5 ARM64: dts: amlogic: add the ethernet TX delay configuration
In reply to Martin BlumenstinglThis adds the amlogic,tx-delay-ns with the old (hardcoded) default value of 2ns to all boards which are using an RGMII ethernet PHY.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts | 2 ++ 6 files changed, 12 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +2 -0
@@ -161,6 +161,8 @@ snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low; + amlogic,tx-delay-ns = <2>; + phy-mode = "rgmii"; };
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +2 -0
@@ -152,6 +152,8 @@ snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low; + amlogic,tx-delay-ns = <2>; + phy-mode = "rgmii"; };
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +2 -0
@@ -131,6 +131,8 @@ snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low; + amlogic,tx-delay-ns = <2>; + phy-mode = "rgmii"; };
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +2 -0
@@ -64,6 +64,8 @@ snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low; + amlogic,tx-delay-ns = <2>; + /* External PHY is in RGMII */ phy-mode = "rgmii"; };
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +2 -0
@@ -156,6 +156,8 @@ snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low; + amlogic,tx-delay-ns = <2>; + /* External PHY is in RGMII */ phy-mode = "rgmii"; };
arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts +2 -0
@@ -64,6 +64,8 @@ snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low; + amlogic,tx-delay-ns = <2>; + /* External PHY is in RGMII */ phy-mode = "rgmii"; };
Signature · 1 line
2.10.2
Martin Blumenstingl
reviewercover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglHi Kevin,
Quoted 18 lines · Martin Blumenstingl
This partially fixes the 1000Mbit/s ethernet TX throughput issues (on networks which are not affected by the EEE problem, as reported here:
[1]).
The actual problem for the TX throughput issues was that the TX delay was applied twice:
- once "accidentally" by the PHY (this was fixed with [2])
- once by the MAC because there was a hardcoded TX delay (of 2ns), this will be configurable with the changes from [0]These are the dts changes which belong to my other series (in v2 these patches were part of the other series, upon request of the net maintainers I have split the .dts changes into their own series so we are able to take both through different trees):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay": [0].
Thus this series depends on the ACK for the binding changes in the other series!
Quoted 2 lines
I based these changes on my other series "[PATCH v2 0/2] GXL and GXM SCPI improvements": [3]
the DT binding changes for the meson8b-dwmac driver were ACK'ed by Rob Herring, so you can proceed with this series once you applied the SCPI patches.
Thank you!
Regards,
Martin
Kevin Hilman
maintainercover meson-gx: reset RGMII PHYs and configure TX delay
Quoted 20 lines · Martin Blumenstingl
Quoted 18 lines · Martin Blumenstingl
This partially fixes the 1000Mbit/s ethernet TX throughput issues (on networks which are not affected by the EEE problem, as reported here:
[1]).
The actual problem for the TX throughput issues was that the TX delay was applied twice:
- once "accidentally" by the PHY (this was fixed with [2])
- once by the MAC because there was a hardcoded TX delay (of 2ns), this will be configurable with the changes from [0]These are the dts changes which belong to my other series (in v2 these patches were part of the other series, upon request of the net maintainers I have split the .dts changes into their own series so we are able to take both through different trees):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay": [0].
Thus this series depends on the ACK for the binding changes in the other series!
Quoted 5 lines
Quoted 2 lines
I based these changes on my other series "[PATCH v2 0/2] GXL and GXM SCPI improvements": [3]
the DT binding changes for the meson8b-dwmac driver were ACK'ed by Rob Herring, so you can proceed with this series once you applied the SCPI patches.
Series queued for v4.11,
Thanks,
Kevin
Jerome Brunet
reviewercover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglQuoted 32 lines · Martin Blumenstingl
This partially fixes the 1000Mbit/s ethernet TX throughput issues (on networks which are not affected by the EEE problem, as reported here:
[1]).
The actual problem for the TX throughput issues was that the TX delay was applied twice:
- once "accidentally" by the PHY (this was fixed with [2])
- once by the MAC because there was a hardcoded TX delay (of 2ns), ? this will be configurable with the changes from [0]These are the dts changes which belong to my other series (in v2 these patches were part of the other series, upon request of the net maintainers I have split the .dts changes into their own series so
we are able to take both through different trees):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay": [0].
Thus this series depends on the ACK for the binding changes in the other series!I based these changes on my other series "[PATCH v2 0/2] GXL and GXM SCPI improvements": [3]
[0] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/
001834.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/
001607.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/
001707.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/
001831.html
Quoted 2 lines
Martin Blumenstingl (5):
? ARM64: dts: meson-gx: move the MDIO node to meson-gx
Sorry for the late reply, I've only been able to test this yesterday.
With "snps,dwmac-mdio" provided in meson-gx.dtsi, the mdio_node is defined in?stmmac_mdio_register and auto-detection of the PHY is disabled for all meson-gx boards.
I wonder if this is desirable ? or maybe this something we could fix in stmmac ? (perform auto-detect the mdio bus is provided without a PHY)
Also, I think bisect is broken between patch 1 and patch 4: The PHY of some boards won't be detected between these patches. Should we squash them ??
Quoted 5 lines
? ARM64: dts: meson-gxbb-odroidc2: add reset for the ethernet PHY ? ARM64: dts: meson-gxbb-p20x: add reset for the ethernet PHY ? ARM64: dts: meson-gxbb-vega-s95: add reset for the ethernet PHY ? ARM64: dts: amlogic: add the ethernet TX delay configuration
Last remark, about the use of?ethernet-phy-idXXXX.XXXX in the odroid and the vega: Isn't it better to let phylib do the autodetection of the phy id ?
If we want to specify the id in DT, we should probably add it for the Micrel PHY of the p200 as well, for consistency.
Quoted 13 lines
?arch/arm64/boot/dts/amlogic/meson-gx.dtsi????????????|??6 ++++++ ?arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts??| 17
+++++++++++++++++
?arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi?????| 17
+++++++++++++++++
?arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 17
+++++++++++++++++?arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts |??2 ++ ?arch/arm64/boot/dts/amlogic/meson-gxl.dtsi???????????|??6 ------ ?arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts??|??2 ++ ?arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts??|??2 ++?8 files changed, 63 insertions(+), 6 deletions(-)
Martin Blumenstingl
reviewercover meson-gx: reset RGMII PHYs and configure TX delay
Quoted 36 lines · Jerome Brunet
Quoted 32 lines · Martin Blumenstingl
This partially fixes the 1000Mbit/s ethernet TX throughput issues (on networks which are not affected by the EEE problem, as reported here:
[1]).
The actual problem for the TX throughput issues was that the TX delay was applied twice:
- once "accidentally" by the PHY (this was fixed with [2])
- once by the MAC because there was a hardcoded TX delay (of 2ns), this will be configurable with the changes from [0]These are the dts changes which belong to my other series (in v2 these patches were part of the other series, upon request of the net maintainers I have split the .dts changes into their own series so
we are able to take both through different trees):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay": [0].
Thus this series depends on the ACK for the binding changes in the other series!I based these changes on my other series "[PATCH v2 0/2] GXL and GXM SCPI improvements": [3]
[0] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/
001834.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/
001607.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2016-November/
001707.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/
001831.htmlQuoted 2 lines
Martin Blumenstingl (5):
ARM64: dts: meson-gx: move the MDIO node to meson-gx
Quoted 8 lines
Sorry for the late reply, I've only been able to test this yesterday.
With "snps,dwmac-mdio" provided in
meson-gx.dtsi, themdio_nodeis defined instmmac_mdio_registerand auto-detection of the PHY is disabled for all meson-gx boards.I wonder if this is desirable ? or maybe this something we could fix in stmmac ? (perform auto-detect the mdio bus is provided without a PHY)
actually it's only a "problem" when introducing support for new devices. can you please forward this question to the stmmac maintainers, as I think your idea of enabling auto-detection when there are no children in the MDIO-bus makes sense
Quoted 3 lines
Also, I think bisect is broken between patch 1 and patch 4: The PHY of some boards won't be detected between these patches. Should we squash them ?
what do you mean exactly? currently the TX-delay is hardcoded in dwmac-meson8b. patch 4 moves the hardcoded value from the dwmac-meson8b to the .dts-files.
unfortunately the corresponding dwmac-meson8b patch was not accepted yet, so at the moment patch 4 should be a no-op.
Quoted 6 lines
Quoted 5 lines
ARM64: dts: meson-gxbb-odroidc2: add reset for the ethernet PHY
ARM64: dts: meson-gxbb-p20x: add reset for the ethernet PHY
ARM64: dts: meson-gxbb-vega-s95: add reset for the ethernet PHY
ARM64: dts: amlogic: add the ethernet TX delay configuration
Quoted 6 lines
Last remark, about the use of ethernet-phy-idXXXX.XXXX in the odroid and the vega: Isn't it better to let phylib do the autodetection of the phy id ?
If we want to specify the id in DT, we should probably add it for the Micrel PHY of the p200 as well, for consistency.
this seems to be a "best practice" when the PHY ID is known, see [0] If you know the PHY ID of the Micrel PHY then please let me know, then we can include this in the fix for the p20x boards
Quoted 5 lines
Quoted 5 lines
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 ++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 17+++++++++++++++++
Quoted 8 lines
Quoted 8 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts | 2 ++ 8 files changed, 63 insertions(+), 6 deletions(-)
[0] http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/net/phy.txt#L22
Jerome Brunet
reviewercover meson-gx: reset RGMII PHYs and configure TX delay
Quoted 58 lines · Martin Blumenstingl
Quoted 56 lines · Jerome Brunet
Quoted 44 lines · Martin Blumenstingl
This partially fixes the 1000Mbit/s ethernet TX throughput issues (on
networks which are not affected by the EEE problem, as reported here:
[1]).
The actual problem for the TX throughput issues was that the TX delay
was applied twice:
- once "accidentally" by the PHY (this was fixed with [2])
- once by the MAC because there was a hardcoded TX delay (of 2ns),
? this will be configurable with the changes from [0]These are the dts changes which belong to my other series (in v2 these patches were part of the other series, upon request of the net maintainers I have split the .dts changes into their own series
so
we are able to take both through different trees):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay": [0].
Thus this series depends on the ACK for the binding changes in the
other series!I based these changes on my other series "[PATCH v2 0/2] GXL and GXM
SCPI improvements": [3][0] http://lists.infradead.org/pipermail/linux-amlogic/2016-Decem
ber/
001834.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-Novem
ber/
001607.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2016-Novem
ber/
001707.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2016-Decem
ber/
001831.htmlQuoted 2 lines
Martin Blumenstingl (5):
? ARM64: dts: meson-gx: move the MDIO node to meson-gxSorry for the late reply, I've only been able to test this yesterday.
With "snps,dwmac-mdio" provided in
meson-gx.dtsi, themdio_nodeis defined instmmac_mdio_registerand auto-detection of the PHY is disabled for all meson-gx boards.
Quoted 8 lines
Quoted 4 lines
I wonder if this is desirable ? or maybe this something we could fix in
stmmac ? (perform auto-detect the mdio bus is provided without a PHY)actually it's only a "problem" when introducing support for new devices. can you please forward this question to the stmmac maintainers, as I think your idea of enabling auto-detection when there are no children in the MDIO-bus makes sense
That's one way to address the issue, sure. I just wonder if we should keep the declaration of the mdio bus with "snps,dwmac-mdio" in the dts using it, with the phy explicitly declared ...
Otherwise, we have to make clear that you must always explicitly declare your PHY in amlogic's dts so there is no surprise.
As you mentioned, we missed the gxbb-nexbox-a95. No phy declared in that dts, but it still get the mdio bus from meson-gx.dtsi. So as of "ARM64: dts: meson-gx: move the MDIO node to meson-gx" the PHY is not detected on this board.
Quoted 7 lines
Quoted 7 lines
Also, I think bisect is broken between patch 1 and patch 4: The PHY of
some boards won't be detected between these patches. Should we squash
them ?
Quoted 5 lines
what do you mean exactly? currently the TX-delay is hardcoded in dwmac-meson8b. patch 4 moves the hardcoded value from the dwmac-meson8b to the .dts-files.
unfortunately the corresponding dwmac-meson8b patch was not accepted yet, so at the moment patch 4 should be a no-op.
Nothing related to the tx-delay ... I'm all for it ;) Thx for your work by the way
What I meant is that as of "ARM64: dts: meson-gx: move the MDIO node to meson-gx" all boards not declaring the PHY explicitly can't detect it anymore. that's more or less all gxbb boards
With "ARM64: dts: meson-gxbb-odroidc2: add reset for the ethernet PHY" the odroid gets fixed ... but the p200 and vega-s95 are still broken?
With the next patch, the p200 is/should have been fixed, then the vega- s95 is fixed?
In the end the gxbb-nexbox is still broken. To be honest I did not verify if there any other board in that case.
My point is that I think the declaration of the mdio bus in meson- gx.dtsi and the declaration of each PHY in the board dtss should be done in single commit to avoid having a (very) short part of the history with regressions
Quoted 15 lines
Quoted 15 lines
Quoted 8 lines
? ARM64: dts: meson-gxbb-odroidc2: add reset for the ethernet PHY ? ARM64: dts: meson-gxbb-p20x: add reset for the ethernet PHY ? ARM64: dts: meson-gxbb-vega-s95: add reset for the ethernet PHY ? ARM64: dts: amlogic: add the ethernet TX delay configuration
Last remark, about the use of ethernet-phy-idXXXX.XXXX in the odroid
and the vega: Isn't it better to let phylib do the autodetection of the
phy id ?
Quoted 7 lines
Quoted 3 lines
If we want to specify the id in DT, we should probably add it for the
Micrel PHY of the p200 as well, for consistency.this seems to be a "best practice" when the PHY ID is known, see [0] If you know the PHY ID of the Micrel PHY then please let me know, then
we can include this in the fix for the p20x boards
OK
Quoted 19 lines
Quoted 16 lines
Quoted 10 lines
?arch/arm64/boot/dts/amlogic/meson-gx.dtsi????????????|??6 ++++++ ?arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts??| 17
+++++++++++++++++
?arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi?????| 17
+++++++++++++++++
?arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 17
+++++++++++++++++Quoted 6 lines
?arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts |??2 ++ ?arch/arm64/boot/dts/amlogic/meson-gxl.dtsi???????????|??6 ------ ?arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts??|??2 ++ ?arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts??|??2 ++?8 files changed, 63 insertions(+), 6 deletions(-)
[0] http://lxr.free-electrons.com/source/Documentation/devicetree/bin
dings/net/phy.txt#L22
Martin Blumenstingl
reviewercover meson-gx: reset RGMII PHYs and configure TX delay
Quoted 72 lines · Jerome Brunet
Quoted 58 lines · Martin Blumenstingl
Quoted 56 lines · Jerome Brunet
Quoted 44 lines · Martin Blumenstingl
This partially fixes the 1000Mbit/s ethernet TX throughput issues (on
networks which are not affected by the EEE problem, as reported here:
[1]).
The actual problem for the TX throughput issues was that the TX delay
was applied twice:
- once "accidentally" by the PHY (this was fixed with [2])
- once by the MAC because there was a hardcoded TX delay (of 2ns),
this will be configurable with the changes from [0]These are the dts changes which belong to my other series (in v2 these patches were part of the other series, upon request of the net maintainers I have split the .dts changes into their own series
so
we are able to take both through different trees):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay": [0].
Thus this series depends on the ACK for the binding changes in the
other series!I based these changes on my other series "[PATCH v2 0/2] GXL and GXM
SCPI improvements": [3][0] http://lists.infradead.org/pipermail/linux-amlogic/2016-Decem
ber/
001834.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-Novem
ber/
001607.html
[2] http://lists.infradead.org/pipermail/linux-amlogic/2016-Novem
ber/
001707.html
[3] http://lists.infradead.org/pipermail/linux-amlogic/2016-Decem
ber/
001831.htmlQuoted 2 lines
Martin Blumenstingl (5):
ARM64: dts: meson-gx: move the MDIO node to meson-gxSorry for the late reply, I've only been able to test this yesterday.
With "snps,dwmac-mdio" provided in
meson-gx.dtsi, themdio_nodeis defined instmmac_mdio_registerand auto-detection of the PHY is disabled for all meson-gx boards.Quoted 8 lines
Quoted 4 lines
I wonder if this is desirable ? or maybe this something we could fix in
stmmac ? (perform auto-detect the mdio bus is provided without a PHY)actually it's only a "problem" when introducing support for new devices. can you please forward this question to the stmmac maintainers, as I think your idea of enabling auto-detection when there are no children in the MDIO-bus makes sense
That's one way to address the issue, sure. I just wonder if we should keep the declaration of the mdio bus with "snps,dwmac-mdio" in the dts using it, with the phy explicitly declared ...
Quoted 7 lines
Otherwise, we have to make clear that you must always explicitly declare your PHY in amlogic's dts so there is no surprise.
As you mentioned, we missed the gxbb-nexbox-a95. No phy declared in that dts, but it still get the mdio bus from
meson-gx.dtsi. So as of "ARM64: dts: meson-gx: move the MDIO node to meson-gx" the PHY is not detected on this board.
indeed, however I'd like to point out that this was already a restriction for GXL and GXM based boards before.
I'm open to any solution though as breaking things is always bad
Quoted 26 lines
Quoted 7 lines
Quoted 7 lines
Also, I think bisect is broken between patch 1 and patch 4: The PHY of
some boards won't be detected between these patches. Should we squash
them ?Quoted 5 lines
what do you mean exactly? currently the TX-delay is hardcoded in dwmac-meson8b. patch 4 moves the hardcoded value from the dwmac-meson8b to the .dts-files.
unfortunately the corresponding dwmac-meson8b patch was not accepted yet, so at the moment patch 4 should be a no-op.Nothing related to the tx-delay ... I'm all for it ;) Thx for your work by the way
What I meant is that as of "ARM64: dts: meson-gx: move the MDIO node to meson-gx" all boards not declaring the PHY explicitly can't detect it anymore. that's more or less all gxbb boards
With "ARM64: dts: meson-gxbb-odroidc2: add reset for the ethernet PHY" the odroid gets fixed ... but the p200 and vega-s95 are still broken
With the next patch, the p200 is/should have been fixed, then the vega- s95 is fixed
Quoted 7 lines
In the end the gxbb-nexbox is still broken. To be honest I did not verify if there any other board in that case.
My point is that I think the declaration of the mdio bus in meson-
gx.dtsiand the declaration of each PHY in the board dtss should be done in single commit to avoid having a (very) short part of the history with regressions
now I see the dependency, thanks for pointing this out! Depending on the decision for above problem (MDIO-bus in meson-gx.dtsi or not) I can provide a v2 with all issues addressed.
Quoted 44 lines
Quoted 15 lines
Quoted 15 lines
Quoted 8 lines
ARM64: dts: meson-gxbb-odroidc2: add reset for the ethernet PHY
ARM64: dts: meson-gxbb-p20x: add reset for the ethernet PHY
ARM64: dts: meson-gxbb-vega-s95: add reset for the ethernet PHY
ARM64: dts: amlogic: add the ethernet TX delay configurationLast remark, about the use of ethernet-phy-idXXXX.XXXX in the odroid
and the vega: Isn't it better to let phylib do the autodetection of the
phy id ?Quoted 7 lines
Quoted 3 lines
If we want to specify the id in DT, we should probably add it for the
Micrel PHY of the p200 as well, for consistency.this seems to be a "best practice" when the PHY ID is known, see [0] If you know the PHY ID of the Micrel PHY then please let me know, then
we can include this in the fix for the p20x boardsOK
Quoted 19 lines
Quoted 16 lines
Quoted 16 lines
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 6 ++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 17 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 17 +++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxl.dtsi | 6 ------ arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-s912-q200.dts | 2 ++ 8 files changed, 63 insertions(+), 6 deletions(-)[0] http://lxr.free-electrons.com/source/Documentation/devicetree/bin
dings/net/phy.txt#L22
Kevin Hilman
maintainercover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglQuoted 2 lines · Martin Blumenstingl
This partially fixes the 1000Mbit/s ethernet TX throughput issues (on networks which are not affected by the EEE problem, as reported here:
Based on the discussions with Jerome, I'm dropping this series from the v4.11/dt64 branch for now.
This series also had a small conflict with Jerome's fix[1] for the odroid-c2, so please rebase any updates here on my v4.10/fixes branch.
Kevin
[1] https://git.kernel.org/cgit/linux/kernel/git/khilman/linux-amlogic.git/commit/?h=v4.10/fixes
Martin Blumenstingl
reviewercover meson-gx: reset RGMII PHYs and configure TX delay
Kevin,
Quoted 7 lines · Kevin Hilman
Quoted 2 lines · Martin Blumenstingl
This partially fixes the 1000Mbit/s ethernet TX throughput issues (on networks which are not affected by the EEE problem, as reported here:
Based on the discussions with Jerome, I'm dropping this series from the v4.11/dt64 branch for now.
what is you opinion on having the MDIO node in meson-gx (and keeping GXBB and GXL/GXM consistent) vs not having PHY autodetection for GXBB (= not having the MDIO in meson-gx)?
I cannot send a v2 until we have a decision for this
Quoted 2 lines
This series also had a small conflict with Jerome's fix[1] for the odroid-c2, so please rebase any updates here on my v4.10/fixes branch.
will keep that in mind, noted.
Jerome Brunet
reviewercover meson-gx: reset RGMII PHYs and configure TX delay
Quoted 22 lines · Martin Blumenstingl
Kevin,
Quoted 4 lines · Kevin Hilman
Quoted 1 line · Martin Blumenstingl
Quoted 8 lines
Quoted 4 lines
This partially fixes the 1000Mbit/s ethernet TX throughput issues (on
networks which are not affected by the EEE problem, as reported here:Based on the discussions with Jerome, I'm dropping this series from the
v4.11/dt64 branch for now.what is you opinion on having the MDIO node in meson-gx (and keeping GXBB and GXL/GXM consistent) vs not having PHY autodetection for GXBB (= not having the MDIO in meson-gx)?
I cannot send a v2 until we have a decision for thisQuoted 1 line
Quoted 4 lines
Quoted 3 lines
This series also had a small conflict with Jerome's fix[1] for the odroid-c2, so please rebase any updates here on my v4.10/fixes branch.
will keep that in mind, noted.
Most this patch can go away with your patch.
Just make sure to keep "eee-broken-1000t;" in the odroidc2 dtsi and it'll be OK.
Quoted 4 lines
_______________________________________________
linux-amlogic mailing list
linux-amlogic at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
Martin Blumenstingl
reviewerv2 cover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglThis series adds the reset GPIOs for the (external) ethernet PHYs on all GXBB boards.
Additionally it provides a ethernet PHY node which can be used to specify PHY-specific properties (this may be required if more boards require the "eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts consistent I chose to add the PHY node also for boards which don't have a RTL8211F PHY.
Patch #7 from this series also removes ethernet support for the P200 board because it was broken anyways and nobody seems to have a board available for testing. This was the outcome of the discussion from [0]
Patch #8 was taken from (older versions of) my other series (see [1]):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay".
The binding changes for amlogic,tx-delay-ns were ACK'ed already.
Changes since v1:
- do not move the MDIO bus to meson-gx as this disables PHY auto-scanning in the stmmac driver (this drops patch #1 from v1)
- add the ethernet PHY reset GPIO for nexbox a95x which was forgotten in v1
- add the ethernet PHY reset GPIO for boards which were added since v1 (wetek hub and wetek play2)
- rebased to apply against the current v4.11/dt64 branch
- new in v2 (patch #7): disabled ethernet support for the P200 board (see the commit description for more information). this patch is optional
- new in v2 (patch #9): removed the phy-mode property from meson-gx (see the commit description for more information). this patch is optional
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-January/002053.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/001834.html
Martin Blumenstingl (9):
ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p201: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p20x: remove the ethernet node
ARM64: dts: amlogic: add the ethernet TX delay configuration
ARM64: dts: meson-gx: remove the phy-mode property from meson-gx
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 - .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 17 ++++++++++++++ .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 7 ++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 26 ++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 ----- .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 20 +++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 26 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 26 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ .../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 11 files changed, 128 insertions(+), 7 deletions(-)
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v2 1/9 ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
This resets the ethernet PHY during boot to get the PHY into a "clean" state. While here also explicitly specify the phy-mode instead of relying on the default-value from meson-gx.dtsi.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +5 -0
@@ -152,6 +152,11 @@ pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; mdio { compatible = "snps,dwmac-mdio";
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v2 2/9 ARM64: dts: meson-gxbb-p201: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +24 -0
@@ -50,3 +50,27 @@ compatible = "amlogic,p201", "amlogic,meson-gxbb"; model = "Amlogic Meson GXBB P201 Development Board"; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id0022.1620", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; +};
Signature · 1 line
2.11.0
PATCH v2 2/9 ARM64: dts: meson-gxbb-p201: add the ethernet PHY's reset GPIO
Quoted 34 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +14
-0@@ -50,3 +50,27 @@ compatible = "amlogic,p201", "amlogic,meson-gxbb"; model = "Amlogic Meson GXBB P201 Development Board"; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio";
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts line 76
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +10
-0+ #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id0022.1620", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; +};
Hi Martin,
It seems you mismatched the p200 and the p201, it's the p201 nobody has and uses a rmii link.
Neil
Martin Blumenstingl
reviewerPATCH v2 2/9 ARM64: dts: meson-gxbb-p201: add the ethernet PHY's reset GPIO
Quoted 48 lines · Neil Armstrong
Quoted 34 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +14
-0@@ -50,3 +50,27 @@ compatible = "amlogic,p201", "amlogic,meson-gxbb"; model = "Amlogic Meson GXBB P201 Development Board"; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio";arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts line 76
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +10
-0+ #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id0022.1620", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; +};Hi Martin,
Quoted 1 line
It seems you mismatched the p200 and the p201, it's the p201 nobody has and uses a rmii link.
ouch, good catch.
I'll send a fix for that later - thanks for spotting!
Martin Blumenstingl
reviewerPATCH v2 3/9 ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +18 -0
@@ -128,6 +128,24 @@ status = "okay"; pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; }; &usb0_phy {
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v2 4/9 ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +17 -0
@@ -164,7 +164,24 @@ status = "okay"; pinctrl-0 = <ð_rmii_pins>; pinctrl-names = "default"; + phy-handle = <ð_phy0>; phy-mode = "rmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id0243.0c54", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; }; &ir {
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v2 5/9 ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +24 -0
@@ -64,3 +64,27 @@ status = "disabled"; }; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +};
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v2 6/9 ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +24 -0
@@ -87,6 +87,30 @@ }; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + &i2c_A { status = "okay"; pinctrl-0 = <&i2c_a_pins>;
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v2 7/9 ARM64: dts: meson-gxbb-p20x: remove the ethernet node
In reply to Martin BlumenstinglThis efficively disables ethernet on the meson-gxbb-p200 board.
Amlogic's own .dts specifies that the P200 board uses a RMII PHY, however our own P200 board .dts does not override the PHY-mode (meaning that it takes the default from meson-gx, which is RGMII mode). This prevents people from thinking that ethernet is actually supported on the P200 boards. People with access to such a board can simply provide a patch which re-enables the ethmac node and adds the required properties.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 ------ 1 file changed, 6 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +0 -6
@@ -144,12 +144,6 @@ pinctrl-names = "default"; }; -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; -}; - &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>;
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v2 8/9 ARM64: dts: amlogic: add the ethernet TX delay configuration
In reply to Martin BlumenstinglThis adds the amlogic,tx-delay-ns property with the old (hardcoded) default value of 2ns to all boards which are using an RGMII ethernet PHY.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 8 files changed, 16 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +2 -0
@@ -154,6 +154,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +2 -0
@@ -58,6 +58,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +2 -0
@@ -131,6 +131,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +2 -0
@@ -72,6 +72,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +2 -0
@@ -94,6 +94,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +2 -0
@@ -59,6 +59,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + /* External PHY reset is shared with internal PHY Led signals */ snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>;
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +2 -0
@@ -162,6 +162,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +2 -0
@@ -59,6 +59,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + /* External PHY reset is shared with internal PHY Led signals */ snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>;
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v2 9/9 ARM64: dts: meson-gx: remove the phy-mode property from meson-gx
In reply to Martin BlumenstinglThe ethmac node has to be configured for each board due to different pinctrl nodes for RGMII/RMII. Thus the phy-mode should be specified at the same place (= in the board .dts), making it easier to read the board .dts file (because the phy-mode is stated explicitly, without requiring developers to read all "parent" .dtsi as well).
--- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 - 1 file changed, 1 deletion(-)
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +0 -1
@@ -395,7 +395,6 @@ 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - phy-mode = "rgmii"; status = "disabled"; };
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerv3 cover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglThis series adds the reset GPIOs for the (external) ethernet PHYs on all GXBB boards.
Additionally it provides a ethernet PHY node which can be used to specify PHY-specific properties (this may be required if more boards require the "eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts consistent I chose to add the PHY node also for boards which don't have a RTL8211F PHY.
Patch #7 from this series also removes ethernet support for the P200 board because it was broken anyways and nobody seems to have a board available for testing. This was the outcome of the discussion from [0]
Patch #8 was taken from (older versions of) my other series (see [1]):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay".
The binding changes for amlogic,tx-delay-ns were ACK'ed already.
Changes since v2:
- fixed patch #2 to really update the P200 board (as it's the P200 which actually uses a Micrel KSZ9031 RGMII PHY). Thanks to Neil Armstrong for spotting this huge mistake!
- instead of dropping ethernet support for P201 we simply re-configure it to RMII mode (replaces patch #7) without a MDIO node (which keeps PHY auto-scanning enabled). This got Neil Armstrong's ACK off-list already
Changes since v1:
- do not move the MDIO bus to meson-gx as this disables PHY auto-scanning in the stmmac driver (this drops patch #1 from v1)
- add the ethernet PHY reset GPIO for nexbox a95x which was forgotten in v1
- add the ethernet PHY reset GPIO for boards which were added since v1 (wetek hub and wetek play2)
- rebased to apply against the current v4.11/dt64 branch
- new in v2 (patch #7): disabled ethernet support for the P200 board (see the commit description for more information). this patch is optional
- new in v2 (patch #9): removed the phy-mode property from meson-gx (see the commit description for more information). this patch is optional
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-January/002053.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/001834.html
Martin Blumenstingl (9):
ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p201: fix ethernet support
ARM64: dts: amlogic: add the ethernet TX delay configuration
ARM64: dts: meson-gx: remove the phy-mode property from meson-gx
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 - .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 17 ++++++++++++++ .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 7 ++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 26 ++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 11 +++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 ----- .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 20 +++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 26 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 26 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ .../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 12 files changed, 139 insertions(+), 7 deletions(-)
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v3 1/9 ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
This resets the ethernet PHY during boot to get the PHY into a "clean" state. While here also explicitly specify the phy-mode instead of relying on the default-value from meson-gx.dtsi.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +5 -0
@@ -152,6 +152,11 @@ pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; mdio { compatible = "snps,dwmac-mdio";
Signature · 1 line
2.11.0
PATCH v3 1/9 ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
Quoted 16 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean" state. While here also explicitly specify the phy-mode instead of relying on the default-value from
meson-gx.dtsi.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 5 +++++ 1 file changed, 5 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +0
-0@@ -152,6 +152,11 @@ pinctrl-0 = <ð_rgmii_pins>;
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts line 162
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +5
-0pinctrl-names = "default"; phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; mdio { compatible = "snps,dwmac-mdio";
On Odroid-c2 rev 0.2 :
Martin Blumenstingl
reviewerPATCH v3 2/9 ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +24 -0
@@ -51,6 +51,30 @@ model = "Amlogic Meson GXBB P200 Development Board"; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id0022.1620", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; +}; + &i2c_B { status = "okay"; pinctrl-0 = <&i2c_b_pins>;
Signature · 1 line
2.11.0
PATCH v3 2/9 ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
Quoted 26 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +7
-0@@ -51,6 +51,30 @@ model = "Amlogic Meson GXBB P200 Development Board"; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; +
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts line 70
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +10
-0+ snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 {
Hi Martin
ethernet-phy at 3, because of the reg property.
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts line 73
Quoted 3 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +3
-0+ compatible = "ethernet-phy-id0022.1620", + "ethernet-phy-ieee802.3-c22"; + reg = <3>;
Andrew
PATCH v3 2/9 ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglQuoted 27 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +8
-0@@ -51,6 +51,30 @@ model = "Amlogic Meson GXBB P200 Development Board"; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>;
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts line 71
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +10
-0+ snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id0022.1620",
Hi Martin
You don't need to specify the PHY ID. You really only need this when the PHY is reporting no ID, or a wrong ID. In fact, if a new revision of the board is made, with a different PHY, you might have a problem, the wrong PHY driver is loaded.
Andrew
Martin Blumenstingl
reviewerPATCH v3 2/9 ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
Hi Andrew,
Quoted 41 lines · Andrew Lunn
Quoted 27 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +8
-0@@ -51,6 +51,30 @@ model = "Amlogic Meson GXBB P200 Development Board"; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>;arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts line 71
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +10
-0+ snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id0022.1620",Hi Martin
Quoted 6 lines
You don't need to specify the PHY ID. You really only need this when the PHY is reporting no ID, or a wrong ID. In fact, if a new revision of the board is made, with a different PHY, you might have a problem, the wrong PHY driver is loaded.
Andrew
I though that this is good practice - the documentation doesn't say that it should only be added in specific cases: [0]
my intention behind adding the PHY ID was to make it easier to see which devices uses which PHY. this is especially useful for devices with RTL8211F PHY (basically all devices with RGMII PHY except the P200) as these may need similar fixes than [1]
regarding your other mail: you're absolutely right that ethernet-phy at 0 should be ethernet-phy at 3.
[0] http://lxr.free-electrons.com/source/Documentation/devicetree/bindings/net/phy.txt
[1] https://patchwork.kernel.org/patch/9528915/
PATCH v3 2/9 ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
Quoted 2 lines · Martin Blumenstingl
I though that this is good practice - the documentation doesn't say that it should only be added in specific cases: [0]
Agreed, the text should be better, listing when it is appropriate to use.
Quoted 4 lines
my intention behind adding the PHY ID was to make it easier to see which devices uses which PHY. this is especially useful for devices with RTL8211F PHY (basically all devices with RGMII PHY except the P200) as these may need similar fixes than [1]
I would not say it is wrong to list the PHY ID, it just has consequences if the PHY ever changes.
Andrew
Martin Blumenstingl
reviewerPATCH v3 2/9 ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
Quoted 7 lines · Andrew Lunn
Quoted 2 lines · Martin Blumenstingl
I though that this is good practice - the documentation doesn't say that it should only be added in specific cases: [0]
Agreed, the text should be better, listing when it is appropriate to use.
Quoted 7 lines
Quoted 4 lines
my intention behind adding the PHY ID was to make it easier to see which devices uses which PHY. this is especially useful for devices with RTL8211F PHY (basically all devices with RGMII PHY except the P200) as these may need similar fixes than [1]
I would not say it is wrong to list the PHY ID, it just has consequences if the PHY ever changes.
thanks for pointing this out again, I'll re-spin this series and remove the PHY's "compatible" property from all patches.
I also sent a patch which hopefully makes the documentation a bit more
clear: [0]
Regards,
Martin
PATCH v3 2/9 ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglQuoted 37 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +17
-0@@ -51,6 +51,30 @@ model = "Amlogic Meson GXBB P200 Development Board"; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 {
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts line 80
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +7
-0+ compatible = "ethernet-phy-id0022.1620", + "ethernet-phy-ieee802.3-c22"; + reg = <3>; + }; + }; +}; + &i2c_B { status = "okay"; pinctrl-0 = <&i2c_b_pins>;
On Amlogic p200 :
Martin Blumenstingl
reviewerPATCH v3 3/9 ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +18 -0
@@ -128,6 +128,24 @@ status = "okay"; pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; }; &usb0_phy {
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v3 4/9 ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +17 -0
@@ -164,7 +164,24 @@ status = "okay"; pinctrl-0 = <ð_rmii_pins>; pinctrl-names = "default"; + phy-handle = <ð_phy0>; phy-mode = "rmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id0243.0c54", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; }; &ir {
Signature · 1 line
2.11.0
PATCH v3 4/9 ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
Quoted 31 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +10
-0@@ -164,7 +164,24 @@ status = "okay"; pinctrl-0 = <ð_rmii_pins>; pinctrl-names = "default"; + phy-handle = <ð_phy0>; phy-mode = "rmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>;
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts line 187
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +7
-0+ + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id0243.0c54", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; }; &ir {
On Nexbox A95X (S905) :
Martin Blumenstingl
reviewerPATCH v3 5/9 ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +24 -0
@@ -64,3 +64,27 @@ status = "disabled"; }; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +};
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v3 6/9 ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +24 -0
@@ -87,6 +87,30 @@ }; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + &i2c_A { status = "okay"; pinctrl-0 = <&i2c_a_pins>;
Signature · 1 line
2.11.0
PATCH v3 6/9 ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
Quoted 37 lines · Martin Blumenstingl
This resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.Signed-off-by Martin Blumenstingl <[email protected]>--- .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +17
-0@@ -87,6 +87,30 @@ }; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 {
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts line 116
Quoted 10 lines
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +7
-0+ compatible = "ethernet-phy-id001c.c916", + "ethernet-phy-ieee802.3-c22"; + reg = <0>; + }; + }; +}; + &i2c_A { status = "okay"; pinctrl-0 = <&i2c_a_pins>;
On Wetek Play 2 :
Martin Blumenstingl
reviewerPATCH v3 7/9 ARM64: dts: meson-gxbb-p201: fix ethernet support
In reply to Martin BlumenstinglAmlogic's own .dts specifies that the P201 board uses a RMII PHY (with the reset GPIO being GPIOZ_14).
However our P201 board .dts simply inherits the phy-mode setting from from meson-gx.dtsi where it defaults to RGMII mode.
Remove all ethernet settings from meson-gxbb-p20x.dtsi as it only specifies the RGMII pins which are only valid for the P200 board. Instead we add the ethmac node to the meson-gxbb-p201.dts and configure the pinctrl property and the phy-mode for an RMII PHY.
An MDIO node (which would also specify the PHY) is not added since we don't know which PHY is being used (and thus which PHY address would have to be used).
--- arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 11 +++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 ------ 2 files changed, 11 insertions(+), 6 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +11 -0
@@ -50,3 +50,14 @@ compatible = "amlogic,p201", "amlogic,meson-gxbb"; model = "Amlogic Meson GXBB P201 Development Board"; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rmii_pins>; + pinctrl-names = "default"; + phy-mode = "rmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; +};
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +0 -6
@@ -144,12 +144,6 @@ pinctrl-names = "default"; }; -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; -}; - &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>;
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v3 8/9 ARM64: dts: amlogic: add the ethernet TX delay configuration
In reply to Martin BlumenstinglThis adds the amlogic,tx-delay-ns property with the old (hardcoded) default value of 2ns to all boards which are using an RGMII ethernet PHY.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 8 files changed, 16 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +2 -0
@@ -154,6 +154,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +2 -0
@@ -58,6 +58,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +2 -0
@@ -131,6 +131,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +2 -0
@@ -72,6 +72,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +2 -0
@@ -94,6 +94,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +2 -0
@@ -59,6 +59,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + /* External PHY reset is shared with internal PHY Led signals */ snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>;
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +2 -0
@@ -162,6 +162,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +2 -0
@@ -59,6 +59,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + /* External PHY reset is shared with internal PHY Led signals */ snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>;
Signature · 1 line
2.11.0
PATCH v3 8/9 ARM64: dts: amlogic: add the ethernet TX delay configuration
Quoted 113 lines · Martin Blumenstingl
This adds the amlogic,tx-delay-ns property with the old (hardcoded) default value of 2ns to all boards which are using an RGMII ethernet PHY.
Signed-off-by Martin Blumenstingl <[email protected]>--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 8 files changed, 16 insertions(+)arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +2
-0@@ -154,6 +154,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +2
-0@@ -58,6 +58,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +2
-0@@ -131,6 +131,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +2
-0@@ -72,6 +72,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +2
-0@@ -94,6 +94,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +2
-0@@ -59,6 +59,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + /* External PHY reset is shared with internal PHY Led signals */ snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>;arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +2
-0@@ -162,6 +162,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +0
-0
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts line 66
Quoted 8 lines
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +2
-0@@ -59,6 +59,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + /* External PHY reset is shared with internal PHY Led signals */ snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>;
On :
- Odroid-C2 rev 0.2
- P200
- Wetek Play 2
- Amlogic P230
- Nexbox A1
Martin Blumenstingl
reviewerPATCH v3 9/9 ARM64: dts: meson-gx: remove the phy-mode property from meson-gx
In reply to Martin BlumenstinglThe ethmac node has to be configured for each board due to different pinctrl nodes for RGMII/RMII. Thus the phy-mode should be specified at the same place (= in the board .dts), making it easier to read the board .dts file (because the phy-mode is stated explicitly, without requiring developers to read all "parent" .dtsi as well).
--- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 - 1 file changed, 1 deletion(-)
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +0 -1
@@ -395,7 +395,6 @@ 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - phy-mode = "rgmii"; status = "disabled"; };
Signature · 1 line
2.11.0
Jerome Brunet
reviewerv3 cover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglQuoted 90 lines · Martin Blumenstingl
This series adds the reset GPIOs for the (external) ethernet PHYs on all
GXBB boards.
Additionally it provides a ethernet PHY node which can be used to specify
PHY-specific properties (this may be required if more boards require the
"eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts
consistent I chose to add the PHY node also for boards which don't have a
RTL8211F PHY.Patch #7 from this series also removes ethernet support for the P200 board because it was broken anyways and nobody seems to have a board available for testing. This was the outcome of the discussion from
[0]Patch #8 was taken from (older versions of) my other series (see [1]):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay".
The binding changes for amlogic,tx-delay-ns were ACK'ed already.Changes since v2:
- fixed patch #2 to really update the P200 board (as it's the P200 which
? actually uses a Micrel KSZ9031 RGMII PHY). Thanks to Neil Armstrong for
? spotting this huge mistake!
- instead of dropping ethernet support for P201 we simply re- configure it
? to RMII mode (replaces patch #7) without a MDIO node (which keeps PHY
? auto-scanning enabled). This got Neil Armstrong's ACK off-list alreadyChanges since v1:
- do not move the MDIO bus to meson-gx as this disables PHY auto- scanning
? in the stmmac driver (this drops patch #1 from v1)
- add the ethernet PHY reset GPIO for nexbox a95x which was forgotten in
? v1
- add the ethernet PHY reset GPIO for boards which were added since v1
? (wetek hub and wetek play2)
- rebased to apply against the current v4.11/dt64 branch
- new in v2 (patch #7): disabled ethernet support for the P200 board (see
? the commit description for more information). this patch is optional
- new in v2 (patch #9): removed the phy-mode property from meson-gx (see
? the commit description for more information). this patch is optional[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-January/0
02053.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/
001834.htmlMartin Blumenstingl (9):
? ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO ? ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO ? ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO ? ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
? ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO ? ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
? ARM64: dts: meson-gxbb-p201: fix ethernet support
? ARM64: dts: amlogic: add the ethernet TX delay configuration ? ARM64: dts: meson-gx: remove the phy-mode property from meson-gx?arch/arm64/boot/dts/amlogic/meson-gx.dtsi??????????|??1 - ?.../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts????| 17
++++++++++++++
?.../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts |??7 ++++++ ?arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts????| 26
++++++++++++++++++++++?arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts????| 11 +++++++++ ?arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi???|??6 ----- ?.../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi??????| 20+++++++++++++++++
?.../boot/dts/amlogic/meson-gxbb-wetek-hub.dts??????| 26
++++++++++++++++++++++
?.../boot/dts/amlogic/meson-gxbb-wetek-play2.dts????| 26
++++++++++++++++++++++
Quoted 4 lines
?.../boot/dts/amlogic/meson-gxl-s905d-p230.dts??????|??2 ++ ?.../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts |??2 ++ ?arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts?????|??2 ++?12 files changed, 139 insertions(+), 7 deletions(-)
Looks good.
Quoted 1 line
Martin Blumenstingl
reviewerv3 cover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglQuoted 53 lines · Martin Blumenstingl
This series adds the reset GPIOs for the (external) ethernet PHYs on all GXBB boards.
Additionally it provides a ethernet PHY node which can be used to specify PHY-specific properties (this may be required if more boards require the "eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts consistent I chose to add the PHY node also for boards which don't have a RTL8211F PHY.Patch #7 from this series also removes ethernet support for the P200 board because it was broken anyways and nobody seems to have a board available for testing. This was the outcome of the discussion from [0]
Patch #8 was taken from (older versions of) my other series (see [1]):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay".
The binding changes for amlogic,tx-delay-ns were ACK'ed already.Changes since v2:
- fixed patch #2 to really update the P200 board (as it's the P200 which actually uses a Micrel KSZ9031 RGMII PHY). Thanks to Neil Armstrong for spotting this huge mistake!
- instead of dropping ethernet support for P201 we simply re-configure it to RMII mode (replaces patch #7) without a MDIO node (which keeps PHY auto-scanning enabled). This got Neil Armstrong's ACK off-list alreadyChanges since v1:
- do not move the MDIO bus to meson-gx as this disables PHY auto-scanning in the stmmac driver (this drops patch #1 from v1)
- add the ethernet PHY reset GPIO for nexbox a95x which was forgotten in v1
- add the ethernet PHY reset GPIO for boards which were added since v1 (wetek hub and wetek play2)
- rebased to apply against the current v4.11/dt64 branch
- new in v2 (patch #7): disabled ethernet support for the P200 board (see the commit description for more information). this patch is optional
- new in v2 (patch #9): removed the phy-mode property from meson-gx (see the commit description for more information). this patch is optional[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-January/002053.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/001834.htmlMartin Blumenstingl (9):
ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p201: fix ethernet support
ARM64: dts: amlogic: add the ethernet TX delay configuration
ARM64: dts: meson-gx: remove the phy-mode property from meson-gx
Quoted 13 lines
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 - .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 17 ++++++++++++++ .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 7 ++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 26 ++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 11 +++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 ----- .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 20 +++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 26 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 26 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ .../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 12 files changed, 139 insertions(+), 7 deletions(-)
I totally forgot to mention:
this applies to Kevin's v4.11/dt64 branch with Jerome's Odroid-C2 ethernet fix [0] applied on top of it
Kevin Hilman
maintainerv3 cover meson-gx: reset RGMII PHYs and configure TX delay
Quoted 68 lines · Martin Blumenstingl
Quoted 53 lines · Martin Blumenstingl
This series adds the reset GPIOs for the (external) ethernet PHYs on all GXBB boards.
Additionally it provides a ethernet PHY node which can be used to specify PHY-specific properties (this may be required if more boards require the "eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts consistent I chose to add the PHY node also for boards which don't have a RTL8211F PHY.Patch #7 from this series also removes ethernet support for the P200 board because it was broken anyways and nobody seems to have a board available for testing. This was the outcome of the discussion from [0]
Patch #8 was taken from (older versions of) my other series (see [1]):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay".
The binding changes for amlogic,tx-delay-ns were ACK'ed already.Changes since v2:
- fixed patch #2 to really update the P200 board (as it's the P200 which actually uses a Micrel KSZ9031 RGMII PHY). Thanks to Neil Armstrong for spotting this huge mistake!
- instead of dropping ethernet support for P201 we simply re-configure it to RMII mode (replaces patch #7) without a MDIO node (which keeps PHY auto-scanning enabled). This got Neil Armstrong's ACK off-list alreadyChanges since v1:
- do not move the MDIO bus to meson-gx as this disables PHY auto-scanning in the stmmac driver (this drops patch #1 from v1)
- add the ethernet PHY reset GPIO for nexbox a95x which was forgotten in v1
- add the ethernet PHY reset GPIO for boards which were added since v1 (wetek hub and wetek play2)
- rebased to apply against the current v4.11/dt64 branch
- new in v2 (patch #7): disabled ethernet support for the P200 board (see the commit description for more information). this patch is optional
- new in v2 (patch #9): removed the phy-mode property from meson-gx (see the commit description for more information). this patch is optional[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-January/002053.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/001834.htmlMartin Blumenstingl (9):
ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p201: fix ethernet support
ARM64: dts: amlogic: add the ethernet TX delay configuration
ARM64: dts: meson-gx: remove the phy-mode property from meson-gxQuoted 13 lines
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 - .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 17 ++++++++++++++ .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 7 ++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 26 ++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 11 +++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 ----- .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 20 +++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 26 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 26 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ .../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 12 files changed, 139 insertions(+), 7 deletions(-)
Quoted 3 lines
I totally forgot to mention:
this applies to Kevin's v4.11/dt64 branch with Jerome's Odroid-C2 ethernet fix [0] applied on top of it
So when Jerome's fix lands in mainline (probably by -rc5, maybe -rc6) I'll rebase the dt64 branch on that and apply this series.
Kevin
Martin Blumenstingl
reviewerv4 cover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglThis series adds the reset GPIOs for the (external) ethernet PHYs on all GXBB boards.
Additionally it provides a ethernet PHY node which can be used to specify PHY-specific properties (this may be required if more boards require the "eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts consistent I chose to add the PHY node also for boards which don't have a RTL8211F PHY.
Patch #7 from this series also removes ethernet support for the P200 board because it was broken anyways and nobody seems to have a board available for testing. This was the outcome of the discussion from [0]
Patch #8 was taken from (older versions of) my other series (see [1]):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay".
The binding changes for amlogic,tx-delay-ns were ACK'ed already.
NOTE: This applies on top of Jerome's Odroid-C2 EEE patch [3] and Andreas F?rber's series "ARM64: meson: DT cleanups"
Changes since v3:
- removed "compatible" property from all PHY nodes because that would force the kernel to choose the driver for the PHY with the ID from the .dts (instead of the actual PHY ID) - see [2] for more information (thanks to Andrew Lunn for spotting this). instead the PHY IDs (and names) are added as a comment inside the corresponding .dts files.
- rebased to apply on top of Andreas F?rber's "ARM64: meson: DT cleanups" series
Changes since v2:
- fixed patch #2 to really update the P200 board (as it's the P200 which actually uses a Micrel KSZ9031 RGMII PHY). Thanks to Neil Armstrong for spotting this huge mistake!
- instead of dropping ethernet support for P201 we simply re-configure it to RMII mode (replaces patch #7) without a MDIO node (which keeps PHY auto-scanning enabled). This got Neil Armstrong's ACK off-list already
Changes since v1:
- do not move the MDIO bus to meson-gx as this disables PHY auto-scanning in the stmmac driver (this drops patch #1 from v1)
- add the ethernet PHY reset GPIO for nexbox a95x which was forgotten in v1
- add the ethernet PHY reset GPIO for boards which were added since v1 (wetek hub and wetek play2)
- rebased to apply against the current v4.11/dt64 branch
- new in v2 (patch #7): disabled ethernet support for the P200 board (see the commit description for more information). this patch is optional
- new in v2 (patch #9): removed the phy-mode property from meson-gx (see the commit description for more information). this patch is optional
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-January/002053.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/001834.html
[2] http://marc.info/?l=linux-netdev&m=148510331812986&w=2
[3] https://git.kernel.org/cgit/linux/kernel/git/khilman/linux-amlogic.git/commit/?h=v4.11/integ&id=5a2288a68582ad3f1b42ed63ae5a3ca54e000965
Martin Blumenstingl (9):
ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p201: fix ethernet support
ARM64: dts: amlogic: add the ethernet TX delay configuration
ARM64: dts: meson-gx: remove the phy-mode property from meson-gx
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 - .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 16 ++++++++++++++ .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 7 ++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 25 ++++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 11 ++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 ------ .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 20 +++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 25 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 25 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ .../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 12 files changed, 135 insertions(+), 7 deletions(-)
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v4 1/9 ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
This resets the ethernet PHY during boot to get the PHY into a "clean" state. While here also explicitly specify the phy-mode instead of relying on the default-value from meson-gx.dtsi.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +5 -0
@@ -142,6 +142,11 @@ pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; mdio { compatible = "snps,dwmac-mdio";
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v4 2/9 ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +23 -0
@@ -51,6 +51,29 @@ model = "Amlogic Meson GXBB P200 Development Board"; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 3 { + /* Micrel KSZ9031 (0x00221620) */ + reg = <3>; + }; + }; +}; + &i2c_B { status = "okay"; pinctrl-0 = <&i2c_b_pins>;
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v4 3/9 ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +18 -0
@@ -115,6 +115,24 @@ status = "okay"; pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; + + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + }; + }; }; &ir {
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v4 4/9 ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 16 ++++++++++++++++ 1 file changed, 16 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +16 -0
@@ -164,7 +164,23 @@ status = "okay"; pinctrl-0 = <ð_rmii_pins>; pinctrl-names = "default"; + phy-handle = <ð_phy0>; phy-mode = "rmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + /* IC Plus IP101GR (0x02430c54) */ + reg = <0>; + }; + }; }; &ir {
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v4 5/9 ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +23 -0
@@ -64,3 +64,26 @@ &cvbs_connector { status = "disabled"; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + }; + }; +};
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v4 6/9 ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 23 ++++++++++++++++++++++ 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +23 -0
@@ -87,6 +87,29 @@ }; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + }; + }; +}; + &i2c_A { status = "okay"; pinctrl-0 = <&i2c_a_pins>;
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v4 7/9 ARM64: dts: meson-gxbb-p201: fix ethernet support
In reply to Martin BlumenstinglAmlogic's own .dts specifies that the P201 board uses a RMII PHY (with the reset GPIO being GPIOZ_14).
However our P201 board .dts simply inherits the phy-mode setting from from meson-gx.dtsi where it defaults to RGMII mode.
Remove all ethernet settings from meson-gxbb-p20x.dtsi as it only specifies the RGMII pins which are only valid for the P200 board. Instead we add the ethmac node to the meson-gxbb-p201.dts and configure the pinctrl property and the phy-mode for an RMII PHY.
An MDIO node (which would also specify the PHY) is not added since we don't know which PHY is being used (and thus which PHY address would have to be used).
--- arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 11 +++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 ------ 2 files changed, 11 insertions(+), 6 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +11 -0
@@ -50,3 +50,14 @@ compatible = "amlogic,p201", "amlogic,meson-gxbb"; model = "Amlogic Meson GXBB P201 Development Board"; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rmii_pins>; + pinctrl-names = "default"; + phy-mode = "rmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; +};
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +0 -6
@@ -143,12 +143,6 @@ }; }; -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; -}; - &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>;
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v4 8/9 ARM64: dts: amlogic: add the ethernet TX delay configuration
In reply to Martin BlumenstinglThis adds the amlogic,tx-delay-ns property with the old (hardcoded) default value of 2ns to all boards which are using an RGMII ethernet PHY.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 8 files changed, 16 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +2 -0
@@ -148,6 +148,8 @@ snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low; + amlogic,tx-delay-ns = <2>; + mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>;
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +2 -0
@@ -58,6 +58,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +2 -0
@@ -119,6 +119,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +2 -0
@@ -72,6 +72,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +2 -0
@@ -94,6 +94,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +2 -0
@@ -59,6 +59,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + /* External PHY reset is shared with internal PHY Led signals */ snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>;
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +2 -0
@@ -117,6 +117,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +2 -0
@@ -59,6 +59,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + /* External PHY reset is shared with internal PHY Led signals */ snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>;
Signature · 1 line
2.11.0
Martin Blumenstingl
reviewerPATCH v4 9/9 ARM64: dts: meson-gx: remove the phy-mode property from meson-gx
In reply to Martin BlumenstinglThe ethmac node has to be configured for each board due to different pinctrl nodes for RGMII/RMII. Thus the phy-mode should be specified at the same place (= in the board .dts), making it easier to read the board .dts file (because the phy-mode is stated explicitly, without requiring developers to read all "parent" .dtsi as well).
--- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 - 1 file changed, 1 deletion(-)
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +0 -1
@@ -377,7 +377,6 @@ 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - phy-mode = "rgmii"; status = "disabled"; };
Signature · 1 line
2.11.0
Kevin Hilman
maintainerv4 cover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglQuoted 9 lines · Martin Blumenstingl
This series adds the reset GPIOs for the (external) ethernet PHYs on all GXBB boards.
Additionally it provides a ethernet PHY node which can be used to specify PHY-specific properties (this may be required if more boards require the "eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts consistent I chose to add the PHY node also for boards which don't have a RTL8211F PHY.Patch #7 from this series also removes ethernet support for the P200
I think you mean P201 here, right?
Kevin
Martin Blumenstingl
reviewerv4 cover meson-gx: reset RGMII PHYs and configure TX delay
Quoted 10 lines · Kevin Hilman
Quoted 8 lines · Martin Blumenstingl
This series adds the reset GPIOs for the (external) ethernet PHYs on all GXBB boards.
Additionally it provides a ethernet PHY node which can be used to specify PHY-specific properties (this may be required if more boards require the "eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts consistent I chose to add the PHY node also for boards which don't have a RTL8211F PHY.
Quoted 3 lines
Quoted 1 line
Patch #7 from this series also removes ethernet support for the P200
I think you mean P201 here, right?
indeed, that's a left-over of my P200 / P201 mixup in v2 - please ignore this :( I should have dropped that sentence completely since it's a lie in v3 (v3 states in changes since v2: "instead of dropping ethernet support for P201 we simply re-configure it to RMII mode")
Martin Blumenstingl
reviewerv5 cover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglThis series adds the reset GPIOs for the (external) ethernet PHYs on all GXBB boards.
Additionally it provides a ethernet PHY node which can be used to specify PHY-specific properties (this may be required if more boards require the "eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts consistent I chose to add the PHY node also for boards which don't have a RTL8211F PHY.
Patch #7 fixes ethernet support on the P201 reference board (this is untested though due to lack of hardware).
Patch #8 was taken from (older versions of) my other series (see [1]):
"[PATCH net-next v3 0/2] stmmac: dwmac-meson8b: configurable RGMII TX delay".
The binding changes for amlogic,tx-delay-ns were ACK'ed already.
Changes since v4:
- fixed bogus statement about patch #7 regarding the P200 board in the cover letter (reword it so it mentions what patch actually does:
fixing ethernet on the P201 board)
- rebased to apply on top of Kevin's v4.11/integ branch since it's based on v4.10-rc8 which includes Jerome's Odroid-C2 EEE patch (otherwise patch #1 would have a conflict with that patch)
Changes since v3:
- removed "compatible" property from all PHY nodes because that would force the kernel to choose the driver for the PHY with the ID from the .dts (instead of the actual PHY ID) - see [2] for more information (thanks to Andrew Lunn for spotting this). instead the PHY IDs (and names) are added as a comment inside the corresponding .dts files.
- rebased to apply on top of Andreas F?rber's "ARM64: meson: DT cleanups" series
Changes since v2:
- fixed patch #2 to really update the P200 board (as it's the P200 which actually uses a Micrel KSZ9031 RGMII PHY). Thanks to Neil Armstrong for spotting this huge mistake!
- instead of dropping ethernet support for P201 we simply re-configure it to RMII mode (replaces patch #7) without a MDIO node (which keeps PHY auto-scanning enabled). This got Neil Armstrong's ACK off-list already
Changes since v1:
- do not move the MDIO bus to meson-gx as this disables PHY auto-scanning in the stmmac driver (this drops patch #1 from v1)
- add the ethernet PHY reset GPIO for nexbox a95x which was forgotten in v1
- add the ethernet PHY reset GPIO for boards which were added since v1 (wetek hub and wetek play2)
- rebased to apply against the current v4.11/dt64 branch
- new in v2 (patch #7): disabled ethernet support for the P200 board (see the commit description for more information). this patch is optional
- new in v2 (patch #9): removed the phy-mode property from meson-gx (see the commit description for more information). this patch is optional
[0] http://lists.infradead.org/pipermail/linux-amlogic/2017-January/002053.html
[1] http://lists.infradead.org/pipermail/linux-amlogic/2016-December/001834.html
[2] http://marc.info/?l=linux-netdev&m=148510331812986&w=2
Martin Blumenstingl (9):
ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
ARM64: dts: meson-gxbb-p201: fix ethernet support
ARM64: dts: amlogic: add the ethernet TX delay configuration
ARM64: dts: meson-gx: remove the phy-mode property from meson-gx
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 - .../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 17 ++++++++++++++ .../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 7 ++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 25 +++++++++++++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 11 +++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 ----- .../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 21 ++++++++++++++++- .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 26 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 26 ++++++++++++++++++++++ .../boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ .../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 12 files changed, 138 insertions(+), 8 deletions(-)
Signature · 1 line
2.11.1
Martin Blumenstingl
reviewerPATCH v5 1/9 ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO
This resets the ethernet PHY during boot to get the PHY into a "clean" state. While here also explicitly specify the phy-mode instead of relying on the default-value from meson-gx.dtsi.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 5 +++++ 1 file changed, 5 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +5 -0
@@ -152,6 +152,11 @@ pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; mdio { compatible = "snps,dwmac-mdio";
Signature · 1 line
2.11.1
Martin Blumenstingl
reviewerPATCH v5 2/9 ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +23 -0
@@ -96,6 +96,29 @@ }; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 3 { + /* Micrel KSZ9031 (0x00221620) */ + reg = <3>; + }; + }; +}; + &i2c_B { status = "okay"; pinctrl-0 = <&i2c_b_pins>;
Signature · 1 line
2.11.1
Martin Blumenstingl
reviewerPATCH v5 3/9 ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 19 ++++++++++++++++++- 1 file changed, 18 insertions(+), 1 deletion(-)
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +18 -1
@@ -115,7 +115,6 @@ status = "okay"; pinctrl-0 = <&uart_ao_a_pins>; pinctrl-names = "default"; - }; &ir {
@@ -128,6 +127,24 @@ status = "okay"; pinctrl-0 = <ð_rgmii_pins>; pinctrl-names = "default"; + + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + }; + }; }; &usb0_phy {
Signature · 1 line
2.11.1
Martin Blumenstingl
reviewerPATCH v5 4/9 ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts +17 -0
@@ -164,7 +164,24 @@ status = "okay"; pinctrl-0 = <ð_rmii_pins>; pinctrl-names = "default"; + + phy-handle = <ð_phy0>; phy-mode = "rmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + /* IC Plus IP101GR (0x02430c54) */ + reg = <0>; + }; + }; }; &ir {
Signature · 1 line
2.11.1
Martin Blumenstingl
reviewerPATCH v5 5/9 ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- .../boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +24 -0
@@ -64,3 +64,27 @@ status = "disabled"; }; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + }; + }; +};
Signature · 1 line
2.11.1
Martin Blumenstingl
reviewerPATCH v5 6/9 ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
In reply to Martin BlumenstinglThis resets the ethernet PHY during boot to get the PHY into a "clean" state.
While here also specify the phy-handle of the ethmac node to make the PHY configuration similar to the one we have on GXL devices. This will allow us to specify OF-properties for the PHY itself.
--- .../boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 24 ++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +24 -0
@@ -87,6 +87,30 @@ }; }; +ðmac { + status = "okay"; + pinctrl-0 = <ð_rgmii_pins>; + pinctrl-names = "default"; + + phy-handle = <ð_phy0>; + phy-mode = "rgmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + eth_phy0: ethernet-phy at 0 { + /* Realtek RTL8211F (0x001cc916) */ + reg = <0>; + }; + }; +}; + &i2c_A { status = "okay"; pinctrl-0 = <&i2c_a_pins>;
Signature · 1 line
2.11.1
Martin Blumenstingl
reviewerPATCH v5 7/9 ARM64: dts: meson-gxbb-p201: fix ethernet support
In reply to Martin BlumenstinglAmlogic's own .dts specifies that the P201 board uses a RMII PHY (with the reset GPIO being GPIOZ_14).
However our P201 board .dts simply inherits the phy-mode setting from from meson-gx.dtsi where it defaults to RGMII mode.
Remove all ethernet settings from meson-gxbb-p20x.dtsi as it only specifies the RGMII pins which are only valid for the P200 board. Instead we add the ethmac node to the meson-gxbb-p201.dts and configure the pinctrl property and the phy-mode for an RMII PHY.
An MDIO node (which would also specify the PHY) is not added since we don't know which PHY is being used (and thus which PHY address would have to be used).
--- arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts | 11 +++++++++++ arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi | 6 ------ 2 files changed, 11 insertions(+), 6 deletions(-)
arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts +11 -0
@@ -50,3 +50,14 @@ compatible = "amlogic,p201", "amlogic,meson-gxbb"; model = "Amlogic Meson GXBB P201 Development Board"; }; + +ðmac { + status = "okay"; + pinctrl-0 = <ð_rmii_pins>; + pinctrl-names = "default"; + phy-mode = "rmii"; + + snps,reset-gpio = <&gpio GPIOZ_14 0>; + snps,reset-delays-us = <0 10000 1000000>; + snps,reset-active-low; +};
arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi +0 -6
@@ -144,12 +144,6 @@ pinctrl-names = "default"; }; -ðmac { - status = "okay"; - pinctrl-0 = <ð_rgmii_pins>; - pinctrl-names = "default"; -}; - &ir { status = "okay"; pinctrl-0 = <&remote_input_ao_pins>;
Signature · 1 line
2.11.1
Martin Blumenstingl
reviewerPATCH v5 8/9 ARM64: dts: amlogic: add the ethernet TX delay configuration
In reply to Martin BlumenstinglThis adds the amlogic,tx-delay-ns property with the old (hardcoded) default value of 2ns to all boards which are using an RGMII ethernet PHY.
--- arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts | 2 ++ arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts | 2 ++ 8 files changed, 16 insertions(+)
arch/arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts +2 -0
@@ -158,6 +158,8 @@ snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low; + amlogic,tx-delay-ns = <2>; + mdio { compatible = "snps,dwmac-mdio"; #address-cells = <1>;
arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts +2 -0
@@ -103,6 +103,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95.dtsi +2 -0
@@ -131,6 +131,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-hub.dts +2 -0
@@ -73,6 +73,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxbb-wetek-play2.dts +2 -0
@@ -95,6 +95,8 @@ phy-handle = <ð_phy0>; phy-mode = "rgmii"; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxl-s905d-p230.dts +2 -0
@@ -59,6 +59,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + /* External PHY reset is shared with internal PHY Led signals */ snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>;
arch/arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts +2 -0
@@ -162,6 +162,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>; snps,reset-active-low;
arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts +2 -0
@@ -59,6 +59,8 @@ /* Select external PHY by default */ phy-handle = <&external_phy>; + amlogic,tx-delay-ns = <2>; + /* External PHY reset is shared with internal PHY Led signals */ snps,reset-gpio = <&gpio GPIOZ_14 0>; snps,reset-delays-us = <0 10000 1000000>;
Signature · 1 line
2.11.1
Martin Blumenstingl
reviewerPATCH v5 9/9 ARM64: dts: meson-gx: remove the phy-mode property from meson-gx
In reply to Martin BlumenstinglThe ethmac node has to be configured for each board due to different pinctrl nodes for RGMII/RMII. Thus the phy-mode should be specified at the same place (= in the board .dts), making it easier to read the board .dts file (because the phy-mode is stated explicitly, without requiring developers to read all "parent" .dtsi as well).
--- arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 1 - 1 file changed, 1 deletion(-)
arch/arm64/boot/dts/amlogic/meson-gx.dtsi +0 -1
@@ -410,7 +410,6 @@ 0x0 0xc8834540 0x0 0x4>; interrupts = <0 8 1>; interrupt-names = "macirq"; - phy-mode = "rgmii"; status = "disabled"; };
Signature · 1 line
2.11.1
Jerome Brunet
reviewerv5 cover meson-gx: reset RGMII PHYs and configure TX delay
In reply to Martin BlumenstinglQuoted 4 lines · Martin Blumenstingl
This series adds the reset GPIOs for the (external) ethernet PHYs on all
GXBB boards.
Additionally it provides a ethernet PHY node which can be used to
Quoted 9 lines
specify
PHY-specific properties (this may be required if more boards require the
"eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts
consistent I chose to add the PHY node also for boards which don't have a
RTL8211F PHY.
Looks good to me. For the patchset:
Quoted 33 lines
Martin Blumenstingl (9):
? ARM64: dts: meson-gxbb-odroidc2: add the ethernet PHY's reset GPIO ? ARM64: dts: meson-gxbb-p200: add the ethernet PHY's reset GPIO ? ARM64: dts: meson-gxbb-vega-s95: add the ethernet PHY's reset GPIO ? ARM64: dts: meson-gxbb-nexbox-a95x: add the ethernet PHY's reset GPIO
? ARM64: dts: meson-gxbb-wetek-hub: add the ethernet PHY's reset GPIO ? ARM64: dts: meson-gxbb-wetek-play2: add the ethernet PHY's reset GPIO
? ARM64: dts: meson-gxbb-p201: fix ethernet support
? ARM64: dts: amlogic: add the ethernet TX delay configuration ? ARM64: dts: meson-gx: remove the phy-mode property from meson-gx?arch/arm64/boot/dts/amlogic/meson-gx.dtsi??????????|??1 - ?.../boot/dts/amlogic/meson-gxbb-nexbox-a95x.dts????| 17
++++++++++++++
?.../arm64/boot/dts/amlogic/meson-gxbb-odroidc2.dts |??7 ++++++ ?arch/arm64/boot/dts/amlogic/meson-gxbb-p200.dts????| 25
+++++++++++++++++++++?arch/arm64/boot/dts/amlogic/meson-gxbb-p201.dts????| 11 +++++++++ ?arch/arm64/boot/dts/amlogic/meson-gxbb-p20x.dtsi???|??6 ----- ?.../boot/dts/amlogic/meson-gxbb-vega-s95.dtsi??????| 21++++++++++++++++-
?.../boot/dts/amlogic/meson-gxbb-wetek-hub.dts??????| 26
++++++++++++++++++++++
?.../boot/dts/amlogic/meson-gxbb-wetek-play2.dts????| 26
++++++++++++++++++++++?.../boot/dts/amlogic/meson-gxl-s905d-p230.dts??????|??2 ++ ?.../arm64/boot/dts/amlogic/meson-gxm-nexbox-a1.dts |??2 ++ ?arch/arm64/boot/dts/amlogic/meson-gxm-q200.dts?????|??2 ++?12 files changed, 138 insertions(+), 8 deletions(-)
Kevin Hilman
maintainerv5 cover meson-gx: reset RGMII PHYs and configure TX delay
Quoted 15 lines · Jerome Brunet
Quoted 4 lines · Martin Blumenstingl
This series adds the reset GPIOs for the (external) ethernet PHYs on all
GXBB boards.
Additionally it provides a ethernet PHY node which can be used toQuoted 9 lines
specify
PHY-specific properties (this may be required if more boards require the
"eee-broken-1000t" for the RTL8211F ethernet PHY). To make all board .dts
consistent I chose to add the PHY node also for boards which don't have a
RTL8211F PHY.
Quoted 3 lines
Looks good to me. For the patchset:
Reviewed-by Jerome Brunet <[email protected]>
Applying to v4.12/dt64 with Jerome's review.
Thanks,
Kevin