configs: ls1021a: enable DT and DM support

---
V5:
- No change

 configs/ls1021aqds_nand_defconfig                   | 3 +++
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig        | 2 ++
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig        | 2 ++
 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++
 configs/ls1021atwr_sdcard_ifc_defconfig             | 3 +++
 5 files changed, 12 insertions(+)

configs/ls1021aqds_nand_defconfig +3 -0

index e28aa48..5c52c3f 100644
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SYS_FSL_DDR3=y

@@ -13,6 +14,7 @@ CONFIG_VIDEO=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_CONTROL=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,NAND_BOOT"
 CONFIG_NAND_BOOT=y

@@ -38,6 +40,7 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y

configs/ls1021aqds_nor_SECURE_BOOT_defconfig +2 -0

index 8b869fa..16dc8bb 100644
@@ -1,11 +1,13 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021AQDS=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-qds-duart"
 CONFIG_SYS_FSL_DDR3=y
 CONFIG_VIDEO=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_CONTROL=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SECURE_BOOT=y
 CONFIG_BOOTDELAY=3

configs/ls1021atwr_nor_SECURE_BOOT_defconfig +2 -0

index 946945f..71681a6 100644
@@ -1,11 +1,13 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_VIDEO=y
 # CONFIG_SYS_MALLOC_F is not set
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_OF_CONTROL=y
 CONFIG_SECURE_BOOT=y
 CONFIG_BOOTDELAY=3
 CONFIG_SILENT_CONSOLE=y

configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +2 -0

index 5e74645..aa8c4f9 100644
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y

@@ -12,6 +13,7 @@ CONFIG_VIDEO=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_CONTROL=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_SECURE_BOOT=y

configs/ls1021atwr_sdcard_ifc_defconfig +3 -0

index 22be22c..1c79d58 100644
@@ -1,5 +1,6 @@
 CONFIG_ARM=y
 CONFIG_TARGET_LS1021ATWR=y
+CONFIG_DEFAULT_DEVICE_TREE="ls1021a-twr-duart"
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SPL_I2C_SUPPORT=y

@@ -11,6 +12,7 @@ CONFIG_VIDEO=y
 CONFIG_FIT=y
 CONFIG_FIT_VERBOSE=y
 CONFIG_OF_BOARD_SETUP=y
+CONFIG_OF_CONTROL=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
 CONFIG_SYS_EXTRA_OPTIONS="RAMBOOT_PBL,SPL_FSL_PBL,SD_BOOT"
 CONFIG_SD_BOOT=y

@@ -35,6 +37,7 @@ CONFIG_CMD_MII=y
 CONFIG_CMD_PING=y
 CONFIG_CMD_EXT2=y
 CONFIG_CMD_FAT=y
+CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_PCI=y

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #1 lore raw

PATCH v5 2/17 dm: pci: return the real controller in pci_bus_to_hose()

From: Minghuan Lian <[email protected]>

for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus.

---
V5:
- No change

 drivers/pci/pci_compat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

drivers/pci/pci_compat.c +1 -1

index ddaf358..25bc095 100644
@@ -49,5 +49,5 @@ struct pci_controller *pci_bus_to_hose(int busnum)
 		return NULL;
 	}
 
-	return dev_get_uclass_priv(bus);
+	return dev_get_uclass_priv(pci_get_controller(bus));
 }

Signature · 1 line

2.1.0.27.g96db324

Bin Meng

2016-12-13 07:47 UTC #2 lore raw

PATCH v5 2/17 dm: pci: return the real controller in pci_bus_to_hose()

Quoted 10 lines · Zhiqiang Hou

From: Minghuan Lian <[email protected]>
for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus.
Signed-off-by Minghuan Lian <[email protected]>
Signed-off-by Hou Zhiqiang <[email protected]>
Reviewed-by Simon Glass <[email protected]>

Quoted 7 lines

---
V5:
- No change

 drivers/pci/pci_compat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Reviewed-by Bin Meng <[email protected]>

Z.Q. Hou

author

2016-12-14 02:38 UTC #3 lore raw

PATCH v5 2/17 dm: pci: return the real controller in pci_bus_to_hose()

Hi Bin,

Thanks for your review!

B.R
Zhiqiang

Quoted 34 lines

-----Original Message-----
From: Bin Meng [mailto:bmeng.cn at gmail.com]
Sent: 2016?12?13? 15:48
To: Z.Q. Hou <[email protected]>
Cc: U-Boot Mailing List <[email protected]>; Albert ARIBAUD <[email protected]>; Prabhakar Kushwaha <[email protected]>; Alison Wang <[email protected]>; Sumit Garg <[email protected]>; Ruchika Gupta <[email protected]>; york sun <[email protected]>; M.H. Lian <[email protected]>; Simon Glass <[email protected]>; Mingkai Hu <[email protected]>
Subject: Re: [PATCHv5 02/17] dm: pci: return the real controller in pci_bus_to_hose()
Quoted 10 lines · Zhiqiang Hou
From: Minghuan Lian <[email protected]>
for the legacy PCI driver, the function pci_bus_to_hose() returns the real PCIe controller. To keep consistency, this function is changed to return the PCIe controller pointer of the root bus instead of the current PCIe bus.
Signed-off-by Minghuan Lian <[email protected]>
Signed-off-by Hou Zhiqiang <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Quoted 7 lines
---
V5:
- No change
 drivers/pci/pci_compat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by Bin Meng <[email protected]>

Zhiqiang Hou

author

2016-12-13 06:54 UTC #4 lore raw

PATCH v5 3/17 dm: pci: remove pci_bus_to_hose(0) calling

From: Minghuan Lian <[email protected]>

There may be multiple PCIe controllers in a SoC.
It is not correct that always calling pci_bus_to_hose(0) to get the first PCIe controller for the PCIe device connected other controllers. We just remove this calling because hose always point the correct PCIe controller.

---
V5:
- No change

 drivers/pci/pci_common.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

drivers/pci/pci_common.c +7 ~~-10~~

index 1755914..6526de8 100644
@@ -181,11 +181,6 @@ phys_addr_t pci_hose_bus_to_phys(struct pci_controller *hose,
 		return phys_addr;
 	}
 
-#ifdef CONFIG_DM_PCI
-	/* The root controller has the region information */
-	hose = pci_bus_to_hose(0);
-#endif
-
 	/*
 	 * if PCI_REGION_MEM is set we do a two pass search with preference
 	 * on matches that don't have PCI_REGION_SYS_MEMORY set

@@ -236,6 +231,13 @@ int __pci_hose_phys_to_bus(struct pci_controller *hose,
 	return 1;
 }
 
+/*
+ * pci_hose_phys_to_bus(): Convert physical address to bus address
+ * @hose:	PCI hose of the root PCI controller
+ * @phys_addr:	physical address to convert
+ * @flags:	flags of pci regions
+ * @return bus address if OK, 0 on error
+ */
 pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
 				phys_addr_t phys_addr,
 				unsigned long flags)

@@ -248,11 +250,6 @@ pci_addr_t pci_hose_phys_to_bus(struct pci_controller *hose,
 		return bus_addr;
 	}
 
-#ifdef CONFIG_DM_PCI
-	/* The root controller has the region information */
-	hose = pci_bus_to_hose(0);
-#endif
-
 	/*
 	 * if PCI_REGION_MEM is set we do a two pass search with preference
 	 * on matches that don't have PCI_REGION_SYS_MEMORY set

Signature · 1 line

2.1.0.27.g96db324

Bin Meng

2016-12-13 07:48 UTC #5 lore raw

PATCH v5 3/17 dm: pci: remove pci_bus_to_hose(0) calling

Quoted 11 lines · Zhiqiang Hou

From: Minghuan Lian <[email protected]>
There may be multiple PCIe controllers in a SoC.
It is not correct that always calling pci_bus_to_hose(0) to get the first PCIe controller for the PCIe device connected other controllers. We just remove this calling because hose always point the correct PCIe controller.
Signed-off-by Minghuan Lian <[email protected]>
Signed-off-by Hou Zhiqiang <[email protected]>
Reviewed-by Simon Glass <[email protected]>

Quoted 7 lines

---
V5:
- No change

 drivers/pci/pci_common.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)

Reviewed-by Bin Meng <[email protected]>

Z.Q. Hou

author

2016-12-14 02:38 UTC #6 lore raw

PATCH v5 3/17 dm: pci: remove pci_bus_to_hose(0) calling

Hi Bin,

Thanks for your review!

B.R
Zhiqiang

Quoted 34 lines

-----Original Message-----
From: Bin Meng [mailto:bmeng.cn at gmail.com]
Sent: 2016?12?13? 15:48
To: Z.Q. Hou <[email protected]>
Cc: U-Boot Mailing List <[email protected]>; Albert ARIBAUD <[email protected]>; Prabhakar Kushwaha <[email protected]>; Alison Wang <[email protected]>; Sumit Garg <[email protected]>; Ruchika Gupta <[email protected]>; york sun <[email protected]>; M.H. Lian <[email protected]>; Simon Glass <[email protected]>; Mingkai Hu <[email protected]>
Subject: Re: [PATCHv5 03/17] dm: pci: remove pci_bus_to_hose(0) calling
Quoted 11 lines · Zhiqiang Hou
From: Minghuan Lian <[email protected]>
There may be multiple PCIe controllers in a SoC.
It is not correct that always calling pci_bus_to_hose(0) to get the first PCIe controller for the PCIe device connected other controllers. We just remove this calling because hose always point the correct PCIe controller.
Signed-off-by Minghuan Lian <[email protected]>
Signed-off-by Hou Zhiqiang <[email protected]>
Reviewed-by Simon Glass <[email protected]>
Quoted 7 lines
---
V5:
- No change
 drivers/pci/pci_common.c | 17 +++++++----------
 1 file changed, 7 insertions(+), 10 deletions(-)
Reviewed-by Bin Meng <[email protected]>

Zhiqiang Hou

author

2016-12-13 06:54 UTC #7 lore raw

PATCH v5 4/17 arm: ls1021a: add PCIe dts node

From: Minghuan Lian <[email protected]>

---
V5:
- No change

 arch/arm/dts/ls1021a.dtsi | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

arch/arm/dts/ls1021a.dtsi +31 -0

index 37be169..c40d87c 100644
@@ -374,5 +374,36 @@
 			interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
 			dr_mode = "host";
 		};
+
+		pcie at 3400000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x03400000 0x20000   /* dbi registers */
+			       0x01570000 0x10000   /* pf controls registers */
+			       0x24000000 0x20000>; /* configuration space */
+			reg-names = "dbi", "ctrl", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x24020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x28000000 0x28000000 0x0 0x08000000>; /* non-prefetchable memory */
+		};
+
+		pcie at 3500000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x03500000 0x10000    /* dbi registers */
+			       0x01570000 0x10000    /* pf controls registers */
+			       0x34000000 0x20000>;  /* configuration space */
+			reg-names = "dbi", "ctrl", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <2>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x34020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x38000000 0x38000000 0x0 0x08000000>; /* non-prefetchable memory */
+		};
 	};
 };

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #8 lore raw

PATCH v5 5/17 arm: ls1012a: add PCIe dts node

From: Minghuan Lian <[email protected]>

---
V5:
- No change

 arch/arm/dts/fsl-ls1012a.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

arch/arm/dts/fsl-ls1012a.dtsi +15 -0

index 024527e..c4ca9c1 100644
@@ -103,5 +103,20 @@
 			status = "disabled";
 		};
 
+		pcie at 3400000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
+			       0x00 0x03480000 0x0 0x40000   /* lut registers */
+			       0x00 0x034c0000 0x0 0x40000   /* pf controls registers */
+			       0x40 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "ctrl", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
 	};
 };

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #9 lore raw

PATCH v5 6/17 armv8: ls1043a: add PCIe dts node

From: Minghuan Lian <[email protected]>

---
V5:
- No change

 arch/arm/dts/fsl-ls1043a.dtsi | 46 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 46 insertions(+)

arch/arm/dts/fsl-ls1043a.dtsi +46 -0

index f038f96..fe6698f 100644
@@ -236,5 +236,51 @@
 			interrupts = <0 63 0x4>;
 			dr_mode = "host";
 		};
+
+		pcie at 3400000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x10000   /* dbi registers */
+			       0x00 0x03410000 0x0 0x10000   /* lut registers */
+			       0x40 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
+
+		pcie at 3500000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03500000 0x0 0x10000   /* dbi registers */
+			       0x00 0x03510000 0x0 0x10000   /* lut registers */
+			       0x48 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <2>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
+
+		pcie at 3600000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03600000 0x0 0x10000   /* dbi registers */
+			       0x00 0x03610000 0x0 0x10000   /* lut registers */
+			       0x50 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
 	};
 };

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #10 lore raw

PATCH v5 7/17 armv8: ls1046a: add PCIe dts node

From: Minghuan Lian <[email protected]>

---
V5:
- No change

 arch/arm/dts/fsl-ls1046a.dtsi | 49 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

arch/arm/dts/fsl-ls1046a.dtsi +49 -0

index 359a9d1..aaf0ae9 100644
@@ -216,5 +216,54 @@
 			big-endian;
 			status = "disabled";
 		};
+
+		pcie at 3400000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
+			       0x00 0x03480000 0x0 0x40000   /* lut registers */
+			       0x00 0x034c0000 0x0 0x40000   /* pf controls registers */
+			       0x40 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "ctrl", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x40 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
+
+		pcie at 3500000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
+			       0x00 0x03580000 0x0 0x40000   /* lut registers */
+			       0x00 0x035c0000 0x0 0x40000   /* pf controls registers */
+			       0x48 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "ctrl", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			num-lanes = <2>;
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x48 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
+
+		pcie at 3600000 {
+			compatible = "fsl,ls-pcie", "snps,dw-pcie";
+			reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
+			       0x00 0x03680000 0x0 0x40000   /* lut registers */
+			       0x00 0x036c0000 0x0 0x40000   /* pf controls registers */
+			       0x50 0x00000000 0x0 0x20000>; /* configuration space */
+			reg-names = "dbi", "lut", "ctrl", "config";
+			big-endian;
+			#address-cells = <3>;
+			#size-cells = <2>;
+			device_type = "pci";
+			bus-range = <0x0 0xff>;
+			ranges = <0x81000000 0x0 0x00000000 0x50 0x00020000 0x0 0x00010000   /* downstream I/O */
+				  0x82000000 0x0 0x40000000 0x50 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+		};
 	};
 };

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #11 lore raw

PATCH v5 8/17 armv8: ls2080a: add PCIe dts node

From: Minghuan Lian <[email protected]>

---
V5:
- No change

 arch/arm/dts/fsl-ls2080a.dtsi | 60 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 60 insertions(+)

arch/arm/dts/fsl-ls2080a.dtsi +60 -0

index f76e981..79047d5 100644
@@ -89,4 +89,64 @@
 		interrupts = <0 81 0x4>; /* Level high type */
 		dr_mode = "host";
 	};
+
+	pcie at 3400000 {
+		compatible = "fsl,ls-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03400000 0x0 0x80000   /* dbi registers */
+		       0x00 0x03480000 0x0 0x80000   /* lut registers */
+		       0x10 0x00000000 0x0 0x20000>; /* configuration space */
+		reg-names = "dbi", "lut", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x10 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x10 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3500000 {
+		compatible = "fsl,ls-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03500000 0x0 0x80000   /* dbi registers */
+		       0x00 0x03580000 0x0 0x80000   /* lut registers */
+		       0x12 0x00000000 0x0 0x20000>; /* configuration space */
+		reg-names = "dbi", "lut", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x12 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x12 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3600000 {
+		compatible = "fsl,ls-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03600000 0x0 0x80000   /* dbi registers */
+		       0x00 0x03680000 0x0 0x80000   /* lut registers */
+		       0x14 0x00000000 0x0 0x20000>; /* configuration space */
+		reg-names = "dbi", "lut", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <8>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x14 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x14 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
+
+	pcie at 3700000 {
+		compatible = "fsl,ls-pcie", "snps,dw-pcie";
+		reg = <0x00 0x03700000 0x0 0x80000   /* dbi registers */
+		       0x00 0x03780000 0x0 0x80000   /* lut registers */
+		       0x16 0x00000000 0x0 0x20000>; /* configuration space */
+		reg-names = "dbi", "lut", "config";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		device_type = "pci";
+		num-lanes = <4>;
+		bus-range = <0x0 0xff>;
+		ranges = <0x81000000 0x0 0x00000000 0x16 0x00020000 0x0 0x00010000   /* downstream I/O */
+			  0x82000000 0x0 0x40000000 0x16 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+	};
 };

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #12 lore raw

PATCH v5 9/17 pci: layerscape: move kernel DT fixup to a separate file

From: Hou Zhiqiang <[email protected]>

To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c.

---
V5:
- New patch

 drivers/pci/Makefile                |   1 +
 drivers/pci/pcie_layerscape.c       | 314 +-----------------------------------
 drivers/pci/pcie_layerscape.h       | 135 ++++++++++++++++
 drivers/pci/pcie_layerscape_fixup.c | 204 +++++++++++++++++++++++
 4 files changed, 343 insertions(+), 311 deletions(-)
 create mode 100644 drivers/pci/pcie_layerscape.h
 create mode 100644 drivers/pci/pcie_layerscape_fixup.c

drivers/pci/Makefile +1 -0

index 86717a4..42174f9 100644
@@ -32,4 +32,5 @@ obj-$(CONFIG_TSI108_PCI) += tsi108_pci.o
 obj-$(CONFIG_WINBOND_83C553) += w83c553f.o
 obj-$(CONFIG_PCIE_DW_MVEBU) += pcie_dw_mvebu.o
 obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape.o
+obj-$(CONFIG_PCIE_LAYERSCAPE) += pcie_layerscape_fixup.o
 obj-$(CONFIG_PCI_XILINX) += pcie_xilinx.o

drivers/pci/pcie_layerscape.c +3 ~~-311~~

332 lines not on this page · raw message

drivers/pci/pcie_layerscape.h new file +135 -0

135 lines not on this page · raw message

drivers/pci/pcie_layerscape_fixup.c new file +204 -0

204 lines not on this page · raw message

Signature · 1 line

2.1.0.27.g96db324

Simon Glass

2016-12-17 22:46 UTC #13 lore raw

PATCH v5 9/17 pci: layerscape: move kernel DT fixup to a separate file

Quoted 10 lines · Zhiqiang Hou

From: Hou Zhiqiang <[email protected]>
To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c.
Signed-off-by Hou Zhiqiang <[email protected]>
---
V5:
- New patch

Quoted 7 lines

 drivers/pci/Makefile                |   1 +
 drivers/pci/pcie_layerscape.c       | 314 +-----------------------------------
 drivers/pci/pcie_layerscape.h       | 135 ++++++++++++++++
 drivers/pci/pcie_layerscape_fixup.c | 204 +++++++++++++++++++++++
 4 files changed, 343 insertions(+), 311 deletions(-)
 create mode 100644 drivers/pci/pcie_layerscape.h
 create mode 100644 drivers/pci/pcie_layerscape_fixup.c

Z.Q. Hou

author

2016-12-19 02:44 UTC #14 lore raw

PATCH v5 9/17 pci: layerscape: move kernel DT fixup to a separate file

Hi Simon,

Thanks a lot for your review!

B.R
Zhiqiang

Quoted 34 lines

-----Original Message-----
From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
Sent: 2016?12?18? 6:47
To: Z.Q. Hou <[email protected]>
Cc: U-Boot Mailing List <[email protected]>; Albert ARIBAUD <[email protected]>; Prabhakar Kushwaha <[email protected]>; Alison Wang <[email protected]>; Sumit Garg <[email protected]>; Ruchika Gupta <[email protected]>; york sun <[email protected]>; M.H. Lian <[email protected]>; Bin Meng <[email protected]>; Mingkai Hu <[email protected]>
Subject: Re: [PATCHv5 09/17] pci: layerscape: move kernel DT fixup to a separate file
Quoted 10 lines · Zhiqiang Hou
From: Hou Zhiqiang <[email protected]>
To make the layerscape pcie driver clear, move the kernel DT fixup code from pcie_layerscape.c to pcie_layerscape_fixup.c.
Signed-off-by Hou Zhiqiang <[email protected]>
---
V5:
- New patch
Quoted 7 lines
 drivers/pci/Makefile                |   1 +
 drivers/pci/pcie_layerscape.c       | 314 +-----------------------------------
 drivers/pci/pcie_layerscape.h       | 135 ++++++++++++++++
 drivers/pci/pcie_layerscape_fixup.c | 204 +++++++++++++++++++++++
 4 files changed, 343 insertions(+), 311 deletions(-)  create mode
100644 drivers/pci/pcie_layerscape.h create mode 100644 drivers/pci/pcie_layerscape_fixup.c
Reviewed-by Simon Glass <[email protected]>

Zhiqiang Hou

author

2016-12-13 06:54 UTC #15 lore raw

PATCH v5 10/17 pci: layerscape: add pci driver based on DM

From: Minghuan Lian <[email protected]>

There are more than five kinds of Layerscape SoCs. unfortunately, PCIe controller of each SoC is a little bit different. In order to avoid too many macro definitions, the patch addes a new implementation of PCIe driver based on DM. PCIe dts node is used to describe the difference.

---
V5:
- Generated the patch base on the separated pci driver file and kernel DT fixup file.

 drivers/pci/Kconfig                 |   8 +
 drivers/pci/pcie_layerscape.c       | 540 ++++++++++++++++++++++++++++++++++++
 drivers/pci/pcie_layerscape.h       |  56 ++++
 drivers/pci/pcie_layerscape_fixup.c | 150 ++++++++++
 4 files changed, 754 insertions(+)

drivers/pci/Kconfig +8 -0

index ff2c370..e5791ec 100644
@@ -71,4 +71,12 @@ config PCI_XILINX
 	  Enable support for the Xilinx AXI bridge for PCI express, an IP block
 	  which can be used on some generations of Xilinx FPGAs.
 
+config PCIE_LAYERSCAPE
+	bool "Layerscape PCIe support"
+	depends on DM_PCI
+	help
+	  Support Layerscape PCIe. The Layerscape SoC may have one or several
+	  PCIe controllers. The PCIe may works in RC or EP mode according to
+	  RCW[HOST_AGT_PEX] setting.
+
 endif

drivers/pci/pcie_layerscape.c +540 -0

555 lines not on this page · raw message

drivers/pci/pcie_layerscape.h +56 -0

66 lines not on this page · raw message

drivers/pci/pcie_layerscape_fixup.c +150 -0

163 lines not on this page · raw message

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #16 lore raw

PATCH v5 11/17 arm: ls1021a: Enable PCIe in defconfigs

From: Minghuan Lian <[email protected]>

The patch enables PCIe in ls1021a defconfigs and
removes unused PCIe related macro defines.

---
V5:
- No change

 configs/ls1021aiot_qspi_defconfig                   |  4 ++++
 configs/ls1021aiot_sdcard_defconfig                 |  4 ++++
 configs/ls1021aqds_ddr4_nor_defconfig               |  5 ++++-
 configs/ls1021aqds_ddr4_nor_lpuart_defconfig        |  5 ++++-
 configs/ls1021aqds_nand_defconfig                   |  5 ++++-
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig        |  5 ++++-
 configs/ls1021aqds_nor_defconfig                    |  5 ++++-
 configs/ls1021aqds_nor_lpuart_defconfig             |  5 ++++-
 configs/ls1021aqds_qspi_defconfig                   |  5 ++++-
 configs/ls1021aqds_sdcard_ifc_defconfig             |  5 ++++-
 configs/ls1021aqds_sdcard_qspi_defconfig            |  5 ++++-
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig        |  5 ++++-
 configs/ls1021atwr_nor_defconfig                    |  5 ++++-
 configs/ls1021atwr_nor_lpuart_defconfig             |  5 ++++-
 configs/ls1021atwr_qspi_defconfig                   |  5 ++++-
 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig |  5 ++++-
 configs/ls1021atwr_sdcard_ifc_defconfig             |  5 ++++-
 configs/ls1021atwr_sdcard_qspi_defconfig            |  5 ++++-
 include/configs/ls1021aiot.h                        | 19 -------------------
 include/configs/ls1021aqds.h                        | 16 ----------------
 include/configs/ls1021atwr.h                        | 16 ----------------
 21 files changed, 72 insertions(+), 67 deletions(-)

configs/ls1021aiot_qspi_defconfig +4 -0

index 6c9140b..9b0fcef 100644
@@ -13,3 +13,7 @@ CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
 CONFIG_TARGET_LS1021AIOT=y
 CONFIG_DEFAULT_DEVICE_TREE="ls1021a-iot-duart"
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021aiot_sdcard_defconfig +4 -0

index a5a391d..04332d0 100644
@@ -17,3 +17,7 @@ CONFIG_FSL_QSPI=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021aqds_ddr4_nor_defconfig +4 -1

index 95930f3..64ca746 100644
@@ -29,7 +29,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

@@ -38,3 +37,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021aqds_ddr4_nor_lpuart_defconfig +4 -1

index 27ef79d..4f1b0d1 100644
@@ -30,7 +30,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_USB=y

@@ -39,3 +38,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021aqds_nand_defconfig +4 -1

index 5c52c3f..0342aca 100644
@@ -43,7 +43,6 @@ CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

@@ -51,3 +50,7 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021aqds_nor_SECURE_BOOT_defconfig +4 -1

index 16dc8bb..e553bac 100644
@@ -31,7 +31,6 @@ CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

@@ -41,3 +40,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021aqds_nor_defconfig +4 -1

index 12205ea..a4534f3 100644
@@ -29,7 +29,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

@@ -38,3 +37,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021aqds_nor_lpuart_defconfig +4 -1

index 4d910cd..6cecc04 100644
@@ -30,7 +30,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_USB=y

@@ -39,3 +38,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021aqds_qspi_defconfig +4 -1

index 79eb9fe..8a7f145 100644
@@ -35,7 +35,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

@@ -45,3 +44,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021aqds_sdcard_ifc_defconfig +4 -1

index beed9ac..795e112 100644
@@ -41,10 +41,13 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021aqds_sdcard_qspi_defconfig +4 -1

index d6b08de..e16f1a9 100644
@@ -45,7 +45,6 @@ CONFIG_SPI_FLASH=y
 CONFIG_SPI_FLASH_SPANSION=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

@@ -55,3 +54,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021atwr_nor_SECURE_BOOT_defconfig +4 -1

index 71681a6..2c44b58 100644
@@ -30,7 +30,6 @@ CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

@@ -40,3 +39,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021atwr_nor_defconfig +4 -1

index 2b351aa..98d7a5d 100644
@@ -28,7 +28,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y

@@ -36,3 +35,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021atwr_nor_lpuart_defconfig +4 -1

index daede61..9443598 100644
@@ -29,7 +29,6 @@ CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_USB=y

@@ -37,3 +36,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021atwr_qspi_defconfig +4 -1

index 05793e9..ec35138 100644
@@ -35,7 +35,6 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

@@ -45,3 +44,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +4 -1

index aa8c4f9..81cdaf6 100644
@@ -44,7 +44,6 @@ CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

@@ -54,3 +53,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_OF_LIBFDT=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021atwr_sdcard_ifc_defconfig +4 -1

index 1c79d58..5297361 100644
@@ -40,7 +40,6 @@ CONFIG_CMD_FAT=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y

@@ -48,3 +47,7 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
 CONFIG_OF_LIBFDT=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls1021atwr_sdcard_qspi_defconfig +4 -1

index 80329fc..d465363 100644
@@ -45,7 +45,6 @@ CONFIG_SPI_FLASH_ATMEL=y
 CONFIG_SPI_FLASH_STMICRO=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

@@ -55,3 +54,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 # CONFIG_VIDEO_SW_CURSOR is not set
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

include/configs/ls1021aiot.h +0 ~~-19~~

index 7af4bc4..3a3bcb5 100644
@@ -233,31 +233,12 @@
 #endif
 
 /* PCIe */
-#define CONFIG_PCI		/* Enable PCI/PCIE */
 #define CONFIG_PCIE1		/* PCIE controler 1 */
 #define CONFIG_PCIE2		/* PCIE controler 2 */
 
-/* Use common FSL Layerscape PCIe code */
-#define CONFIG_PCIE_LAYERSCAPE
 #define FSL_PCIE_COMPAT		"fsl,ls1021a-pcie"
 
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS		0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE	0x08000000	/* 128M */
-
 #ifdef CONFIG_PCI
-#define CONFIG_PCI_PNP
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_CMD_PCI
 #endif

include/configs/ls1021aqds.h +0 ~~-16~~

index 128da8a..ef8a43c 100644
@@ -501,24 +501,8 @@ unsigned long get_board_ddr_clk(void);
 /* PCIe */
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
-#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS		0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE	0x08000000	/* 128M */
-
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_CMD_PCI

include/configs/ls1021atwr.h +0 ~~-16~~

index 1458332..0e87319 100644
@@ -371,24 +371,8 @@
 /* PCIe */
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
-#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS		0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE	0x08000000	/* 128M */
-
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_CMD_PCI

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #17 lore raw

PATCH v5 12/17 arm: ls1012a: Enable PCIe and E1000 in defconfigs

From: Minghuan Lian <[email protected]>

The patch enables PCIe and E1000 in ls1012a defconfigs and removes unused PCIe related macro defines

---
V5:
- No change

 configs/ls1012afrdm_qspi_defconfig |  5 +++++
 configs/ls1012aqds_qspi_defconfig  |  5 ++++-
 configs/ls1012ardb_qspi_defconfig  |  5 ++++-
 include/configs/ls1012aqds.h       | 16 ----------------
 include/configs/ls1012ardb.h       | 16 ----------------
 5 files changed, 13 insertions(+), 34 deletions(-)

configs/ls1012afrdm_qspi_defconfig +5 -0

index c83b2eb..6513bde 100644
@@ -28,10 +28,15 @@ CONFIG_DM=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
+CONFIG_E1000=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_QSPI_AHB_INIT=y

configs/ls1012aqds_qspi_defconfig +4 -1

index 27bccd1..2b184e2 100644
@@ -30,7 +30,6 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

@@ -38,4 +37,8 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_QSPI_AHB_INIT=y

configs/ls1012ardb_qspi_defconfig +4 -1

index 459682d..6137a12 100644
@@ -30,7 +30,6 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

@@ -38,4 +37,8 @@ CONFIG_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
 CONFIG_QSPI_AHB_INIT=y

include/configs/ls1012aqds.h +0 ~~-16~~

index 0cc1791..0e4f6e3 100644
@@ -155,24 +155,8 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 #define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
-
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_CMD_PCI

include/configs/ls1012ardb.h +0 ~~-16~~

index 15410dd..d5573ba 100644
@@ -68,24 +68,8 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 #define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS         0x08000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF    0x04000000
-#define CONFIG_SYS_PCIE_MEM_SIZE        0x80000000      /* 128M */
-
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_CMD_PCI

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #18 lore raw

PATCH v5 13/17 armv8: ls1043a: Enable PCIe and E1000 in defconfigs

From: Minghuan Lian <[email protected]>

The patch enables PCIe and E1000 in ls1043a defconfigs and removes unused PCIe related macro defines.

---
V5:
- No change

 configs/ls1043aqds_defconfig             |  7 ++++++-
 configs/ls1043aqds_lpuart_defconfig      |  7 ++++++-
 configs/ls1043aqds_nand_defconfig        |  7 ++++++-
 configs/ls1043aqds_nor_ddr3_defconfig    |  7 ++++++-
 configs/ls1043aqds_qspi_defconfig        |  7 ++++++-
 configs/ls1043aqds_sdcard_ifc_defconfig  |  7 ++++++-
 configs/ls1043aqds_sdcard_qspi_defconfig |  7 ++++++-
 configs/ls1043ardb_SECURE_BOOT_defconfig |  7 ++++++-
 configs/ls1043ardb_defconfig             |  7 ++++++-
 configs/ls1043ardb_nand_defconfig        |  7 ++++++-
 configs/ls1043ardb_sdcard_defconfig      |  7 ++++++-
 include/configs/ls1043a_common.h         | 17 -----------------
 12 files changed, 66 insertions(+), 28 deletions(-)

configs/ls1043aqds_defconfig +6 -1

index 6ddd54c..78875eb 100644
@@ -25,7 +25,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

@@ -33,3 +32,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1043aqds_lpuart_defconfig +6 -1

index dce9bda..589d373 100644
@@ -26,7 +26,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
 CONFIG_DM_SPI=y

@@ -35,3 +34,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1043aqds_nand_defconfig +6 -1

index ac6da0e..1ed7e4f 100644
@@ -39,7 +39,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

@@ -47,3 +46,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1043aqds_nor_ddr3_defconfig +6 -1

index 454701a..6585851 100644
@@ -25,7 +25,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

@@ -33,3 +32,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1043aqds_qspi_defconfig +6 -1

index f76a698..f85ee1f 100644
@@ -28,7 +28,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

@@ -36,3 +35,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1043aqds_sdcard_ifc_defconfig +6 -1

index 22faf71..5f292e9 100644
@@ -39,7 +39,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

@@ -47,3 +46,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1043aqds_sdcard_qspi_defconfig +6 -1

index e8e31b6..a6c2b82 100644
@@ -40,7 +40,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

@@ -48,3 +47,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1043ardb_SECURE_BOOT_defconfig +6 -1

index b892e35..956235b 100644
@@ -22,7 +22,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

@@ -32,3 +31,9 @@ CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1043ardb_defconfig +6 -1

index 9042ac7..9b81a8d 100644
@@ -21,7 +21,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

@@ -29,3 +28,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1043ardb_nand_defconfig +6 -1

index 9f0c491..60fec6c 100644
@@ -35,7 +35,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

@@ -43,3 +42,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1043ardb_sdcard_defconfig +6 -1

index 0b3f247..ef749cf 100644
@@ -35,7 +35,6 @@ CONFIG_CMD_FAT=y
 CONFIG_OF_CONTROL=y
 CONFIG_DM=y
 CONFIG_SPI_FLASH=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_USB=y

@@ -43,3 +42,9 @@ CONFIG_DM_USB=y
 CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

include/configs/ls1043a_common.h +0 ~~-17~~

index c1e3ec6..3600c4a 100644
@@ -118,27 +118,10 @@
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
-#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 #define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS		0x40000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x40000000
-#define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */
-
 #ifdef CONFIG_PCI
 #define CONFIG_NET_MULTI
-#define CONFIG_E1000
 #define CONFIG_PCI_SCAN_SHOW
 #define CONFIG_CMD_PCI
 #endif

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #19 lore raw

PATCH v5 14/17 armv8: ls1046a: Enable PCIe and E1000 in defconfigs

From: Minghuan Lian <[email protected]>

The patch enables PCIe and E1000 in ls1046a related defconfigs.

---
V5:
- No change

 configs/ls1046aqds_defconfig             | 6 ++++++
 configs/ls1046aqds_nand_defconfig        | 6 ++++++
 configs/ls1046aqds_qspi_defconfig        | 6 ++++++
 configs/ls1046aqds_sdcard_ifc_defconfig  | 6 ++++++
 configs/ls1046aqds_sdcard_qspi_defconfig | 6 ++++++
 configs/ls1046ardb_emmc_defconfig        | 6 ++++++
 configs/ls1046ardb_qspi_defconfig        | 6 ++++++
 configs/ls1046ardb_sdcard_defconfig      | 6 ++++++
 8 files changed, 48 insertions(+)

configs/ls1046aqds_defconfig +6 -0

index 2cc1a0b..e80cc4d 100644
@@ -26,3 +26,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1046aqds_nand_defconfig +6 -0

index 74fcd4a..fcdd905 100644
@@ -30,3 +30,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1046aqds_qspi_defconfig +6 -0

index c8a68fa..b1ef63b 100644
@@ -29,3 +29,9 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1046aqds_sdcard_ifc_defconfig +6 -0

index fe9ad0e..5e528eb 100644
@@ -30,3 +30,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1046aqds_sdcard_qspi_defconfig +6 -0

index 1700082..71ef181 100644
@@ -32,3 +32,9 @@ CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1046ardb_emmc_defconfig +6 -0

index fd21959..1fe376f 100644
@@ -27,3 +27,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

configs/ls1046ardb_qspi_defconfig +6 -0

index fa17373..e881f61 100644
@@ -24,4 +24,10 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y
 CONFIG_QSPI_AHB_INIT=y

configs/ls1046ardb_sdcard_defconfig +6 -0

index 0b810d3..d099625 100644
@@ -27,3 +27,9 @@ CONFIG_SPI_FLASH=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y
+CONFIG_NETDEVICES=y
+CONFIG_E1000=y

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #20 lore raw

PATCH v5 15/17 armv8: ls2080a: Enable PCIe in defconfigs

From: Minghuan Lian <[email protected]>

The patch enables PCIe in ls2080a defconfigs and
removes unused PCIe related macro defines.

---
V5:
- No change

 .../include/asm/arch-fsl-layerscape/immap_lsch3.h  |  8 --------
 configs/ls2080aqds_SECURE_BOOT_defconfig           |  5 ++++-
 configs/ls2080aqds_defconfig                       |  5 ++++-
 configs/ls2080aqds_nand_defconfig                  |  5 ++++-
 configs/ls2080aqds_qspi_defconfig                  |  5 ++++-
 configs/ls2080ardb_SECURE_BOOT_defconfig           |  5 ++++-
 configs/ls2080ardb_defconfig                       |  5 ++++-
 configs/ls2080ardb_nand_defconfig                  |  5 ++++-
 include/configs/ls2080a_common.h                   | 22 ----------------------
 include/configs/ls2080aqds.h                       |  1 -
 include/configs/ls2080ardb.h                       |  1 -
 11 files changed, 28 insertions(+), 39 deletions(-)

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +0 -8

index e18dcbd..f613efa 100644
@@ -107,14 +107,6 @@
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x1200000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x1400000000ULL
 #define CONFIG_SYS_PCIE4_PHYS_ADDR		0x1600000000ULL
-/* LUT registers */
-#define PCIE_LUT_BASE				0x80000
-#define PCIE_LUT_LCTRL0				0x7F8
-#define PCIE_LUT_DBG				0x7FC
-#define PCIE_LUT_UDR(n)         (0x800 + (n) * 8)
-#define PCIE_LUT_LDR(n)         (0x804 + (n) * 8)
-#define PCIE_LUT_ENABLE         (1 << 31)
-#define PCIE_LUT_ENTRY_COUNT    32
 
 /* Device Configuration */
 #define DCFG_BASE		0x01e00000

configs/ls2080aqds_SECURE_BOOT_defconfig +4 -1

index 0c70f92..2af54a7 100644
@@ -22,7 +22,6 @@ CONFIG_DM=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

@@ -34,3 +33,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls2080aqds_defconfig +4 -1

index 63a15ee..7405f3d 100644
@@ -21,7 +21,6 @@ CONFIG_DM=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

@@ -31,3 +30,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls2080aqds_nand_defconfig +4 -1

index 4500c13..ccd2c62 100644
@@ -30,7 +30,6 @@ CONFIG_DM=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

@@ -40,3 +39,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls2080aqds_qspi_defconfig +4 -1

index 0e92ad4..9d9f7e6 100644
@@ -22,7 +22,6 @@ CONFIG_DM=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_QSPI=y

@@ -32,3 +31,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls2080ardb_SECURE_BOOT_defconfig +4 -1

index 1d20175..344e400 100644
@@ -22,7 +22,6 @@ CONFIG_DM=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

@@ -34,3 +33,7 @@ CONFIG_USB_STORAGE=y
 CONFIG_RSA=y
 CONFIG_SPL_RSA=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls2080ardb_defconfig +4 -1

index 4718ab3..d754eac 100644
@@ -21,7 +21,6 @@ CONFIG_DM=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_DM_SPI=y
 CONFIG_FSL_DSPI=y

@@ -31,3 +30,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

configs/ls2080ardb_nand_defconfig +4 -1

index b79e4e4..979c02e 100644
@@ -27,7 +27,6 @@ CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_NETDEVICES=y
 CONFIG_E1000=y
-CONFIG_PCI=y
 CONFIG_SYS_NS16550=y
 CONFIG_USB=y
 CONFIG_DM_USB=y

@@ -35,3 +34,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_XHCI_DWC3=y
 CONFIG_USB_STORAGE=y
 CONFIG_EFI_LOADER_BOUNCE_BUFFER=y
+CONFIG_PCI=y
+CONFIG_DM_PCI=y
+CONFIG_DM_PCI_COMPAT=y
+CONFIG_PCIE_LAYERSCAPE=y

include/configs/ls2080a_common.h +0 ~~-22~~

index 2cae966..805457d 100644
@@ -171,29 +171,7 @@ unsigned long long get_qixis_addr(void);
 #endif
 
 /* PCIe */
-#define CONFIG_PCIE1		/* PCIE controller 1 */
-#define CONFIG_PCIE2		/* PCIE controller 2 */
-#define CONFIG_PCIE3		/* PCIE controller 3 */
-#define CONFIG_PCIE4		/* PCIE controller 4 */
-#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
-#ifdef CONFIG_LS2080A
 #define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
-#endif
-
-#define CONFIG_SYS_PCI_64BIT
-
-#define CONFIG_SYS_PCIE_CFG0_PHYS_OFF	0x00000000
-#define CONFIG_SYS_PCIE_CFG0_SIZE	0x00001000	/* 4k */
-#define CONFIG_SYS_PCIE_CFG1_PHYS_OFF	0x00001000
-#define CONFIG_SYS_PCIE_CFG1_SIZE	0x00001000	/* 4k */
-
-#define CONFIG_SYS_PCIE_IO_BUS		0x00000000
-#define CONFIG_SYS_PCIE_IO_PHYS_OFF	0x00010000
-#define CONFIG_SYS_PCIE_IO_SIZE		0x00010000	/* 64k */
-
-#define CONFIG_SYS_PCIE_MEM_BUS		0x40000000
-#define CONFIG_SYS_PCIE_MEM_PHYS_OFF	0x40000000
-#define CONFIG_SYS_PCIE_MEM_SIZE	0x40000000	/* 1G */
 
 /* Command line configuration */
 #define CONFIG_CMD_ENV

include/configs/ls2080aqds.h +0 -1

index 838568f..e96994e 100644
@@ -347,7 +347,6 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
 #define CONFIG_FSL_MEMAC
-#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_SCAN_SHOW

include/configs/ls2080ardb.h +0 -1

index 31df781..7386080 100644
@@ -291,7 +291,6 @@ unsigned long get_board_sys_clk(void);
 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 
 #define CONFIG_FSL_MEMAC
-#define CONFIG_PCIE_LAYERSCAPE	/* Use common FSL Layerscape PCIe code */
 
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_SCAN_SHOW

Signature · 1 line

2.1.0.27.g96db324

Scott Wood

2017-01-28 02:23 UTC #21 lore raw

PATCH v5 15/17 armv8: ls2080a: Enable PCIe in defconfigs

Quoted 10 lines · Zhiqiang Hou

From: Minghuan Lian <[email protected]>
The patch enables PCIe in ls2080a defconfigs and
removes unused PCIe related macro defines.
Signed-off-by Minghuan Lian <[email protected]>
Signed-off-by Hou Zhiqiang <[email protected]>
---
V5:
?- No change

As of this patch, PCIe ethernet stopped working in Linux (4.10-rc2) on ls2080ardb. ?The e1000e does get probed, but no interrupts are ever seen.

-Scott

Zhiqiang Hou

author

2016-12-13 06:54 UTC #22 lore raw

PATCH v5 16/17 pci: layerscape: remove unnecessary legacy code

From: Minghuan Lian <[email protected]>

All Layerscape SoCs have supported new PCIe driver based on DM. The lagecy PCIe driver code is unused and can be removed.

---
V5:
- No change

 drivers/pci/pcie_layerscape.c       | 497 ------------------------------------
 drivers/pci/pcie_layerscape.h       |  53 +---
 drivers/pci/pcie_layerscape_fixup.c | 167 ------------
 3 files changed, 1 insertion(+), 716 deletions(-)

drivers/pci/pcie_layerscape.c +0 ~~-497~~

index 62a0316..90b9fe2 100644
@@ -12,506 +12,10 @@
 #include <errno.h>
 #include <malloc.h>
 #include <dm.h>
-#ifndef CONFIG_LS102XA
-#include <asm/arch/fdt.h>
-#include <asm/arch/soc.h>
-#else
-#include <asm/arch/immap_ls102xa.h>
-#endif
 #include "pcie_layerscape.h"
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifndef CONFIG_DM_PCI
-#ifdef CONFIG_LS102XA
-/* PEX1/2 Misc Ports Status Register */
-#define LTSSM_STATE_SHIFT	20
-
-static int ls_pcie_link_state(struct ls_pcie *pcie)
-{
-	u32 state;
-	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-
-	state = in_be32(&scfg->pexmscportsr[pcie->idx]);
-	state = (state >> LTSSM_STATE_SHIFT) & LTSSM_STATE_MASK;
-	if (state < LTSSM_PCIE_L0) {
-		debug("....PCIe link error. LTSSM=0x%02x.\n", state);
-		return 0;
-	}
-
-	return 1;
-}
-#else
-static int ls_pcie_link_state(struct ls_pcie *pcie)
-{
-	u32 state;
-
-	state = pex_lut_in32(pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_DBG) &
-		LTSSM_STATE_MASK;
-	if (state < LTSSM_PCIE_L0) {
-		debug("....PCIe link error. LTSSM=0x%02x.\n", state);
-		return 0;
-	}
-
-	return 1;
-}
-#endif
-
-static int ls_pcie_link_up(struct ls_pcie *pcie)
-{
-	int state;
-	u32 cap;
-
-	state = ls_pcie_link_state(pcie);
-	if (state)
-		return state;
-
-	/* Try to download speed to gen1 */
-	cap = readl(pcie->dbi + PCIE_LINK_CAP);
-	writel((cap & (~PCIE_LINK_SPEED_MASK)) | 1, pcie->dbi + PCIE_LINK_CAP);
-	/*
-	 * Notice: the following delay has critical impact on link training
-	 * if too short (<30ms) the link doesn't get up.
-	 */
-	mdelay(100);
-	state = ls_pcie_link_state(pcie);
-	if (state)
-		return state;
-
-	writel(cap, pcie->dbi + PCIE_LINK_CAP);
-
-	return 0;
-}
-
-static void ls_pcie_cfg0_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
-	writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
-	       pcie->dbi + PCIE_ATU_VIEWPORT);
-	writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_cfg1_set_busdev(struct ls_pcie *pcie, u32 busdev)
-{
-	writel(PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
-	       pcie->dbi + PCIE_ATU_VIEWPORT);
-	writel(busdev, pcie->dbi + PCIE_ATU_LOWER_TARGET);
-}
-
-static void ls_pcie_iatu_outbound_set(struct ls_pcie *pcie, int idx, int type,
-				      u64 phys, u64 bus_addr, pci_size_t size)
-{
-	writel(PCIE_ATU_REGION_OUTBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
-	writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_BASE);
-	writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_BASE);
-	writel(phys + size - 1, pcie->dbi + PCIE_ATU_LIMIT);
-	writel((u32)bus_addr, pcie->dbi + PCIE_ATU_LOWER_TARGET);
-	writel(bus_addr >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
-	writel(type, pcie->dbi + PCIE_ATU_CR1);
-	writel(PCIE_ATU_ENABLE, pcie->dbi + PCIE_ATU_CR2);
-}
-
-/* Use bar match mode and MEM type as default */
-static void ls_pcie_iatu_inbound_set(struct ls_pcie *pcie, int idx,
-				     int bar, u64 phys)
-{
-	writel(PCIE_ATU_REGION_INBOUND | idx, pcie->dbi + PCIE_ATU_VIEWPORT);
-	writel((u32)phys, pcie->dbi + PCIE_ATU_LOWER_TARGET);
-	writel(phys >> 32, pcie->dbi + PCIE_ATU_UPPER_TARGET);
-	writel(PCIE_ATU_TYPE_MEM, pcie->dbi + PCIE_ATU_CR1);
-	writel(PCIE_ATU_ENABLE | PCIE_ATU_BAR_MODE_ENABLE |
-	       PCIE_ATU_BAR_NUM(bar), pcie->dbi + PCIE_ATU_CR2);
-}
-
-static void ls_pcie_setup_atu(struct ls_pcie *pcie, struct ls_pcie_info *info)
-{
-#ifdef DEBUG
-	int i;
-#endif
-
-	/* ATU 0 : OUTBOUND : CFG0 */
-	ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
-				  PCIE_ATU_TYPE_CFG0,
-				  info->cfg0_phys,
-				  0,
-				  info->cfg0_size);
-	/* ATU 1 : OUTBOUND : CFG1 */
-	ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX1,
-				  PCIE_ATU_TYPE_CFG1,
-				  info->cfg1_phys,
-				  0,
-				  info->cfg1_size);
-	/* ATU 2 : OUTBOUND : MEM */
-	ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX2,
-				  PCIE_ATU_TYPE_MEM,
-				  info->mem_phys,
-				  info->mem_bus,
-				  info->mem_size);
-	/* ATU 3 : OUTBOUND : IO */
-	ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX3,
-				  PCIE_ATU_TYPE_IO,
-				  info->io_phys,
-				  info->io_bus,
-				  info->io_size);
-
-#ifdef DEBUG
-	for (i = 0; i <= PCIE_ATU_REGION_INDEX3; i++) {
-		writel(PCIE_ATU_REGION_OUTBOUND | i,
-		       pcie->dbi + PCIE_ATU_VIEWPORT);
-		debug("iATU%d:\n", i);
-		debug("\tLOWER PHYS 0x%08x\n",
-		      readl(pcie->dbi + PCIE_ATU_LOWER_BASE));
-		debug("\tUPPER PHYS 0x%08x\n",
-		      readl(pcie->dbi + PCIE_ATU_UPPER_BASE));
-		debug("\tLOWER BUS  0x%08x\n",
-		      readl(pcie->dbi + PCIE_ATU_LOWER_TARGET));
-		debug("\tUPPER BUS  0x%08x\n",
-		      readl(pcie->dbi + PCIE_ATU_UPPER_TARGET));
-		debug("\tLIMIT      0x%08x\n",
-		      readl(pcie->dbi + PCIE_ATU_LIMIT));
-		debug("\tCR1        0x%08x\n",
-		      readl(pcie->dbi + PCIE_ATU_CR1));
-		debug("\tCR2        0x%08x\n",
-		      readl(pcie->dbi + PCIE_ATU_CR2));
-	}
-#endif
-}
-
-int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev)
-{
-	/* Do not skip controller */
-	return 0;
-}
-
-static int ls_pcie_addr_valid(struct pci_controller *hose, pci_dev_t d)
-{
-	if (PCI_DEV(d) > 0)
-		return -EINVAL;
-
-	/* Controller does not support multi-function in RC mode */
-	if ((PCI_BUS(d) == hose->first_busno) && (PCI_FUNC(d) > 0))
-		return -EINVAL;
-
-	return 0;
-}
-
-static int ls_pcie_read_config(struct pci_controller *hose, pci_dev_t d,
-			       int where, u32 *val)
-{
-	struct ls_pcie *pcie = hose->priv_data;
-	u32 busdev, *addr;
-
-	if (ls_pcie_addr_valid(hose, d)) {
-		*val = 0xffffffff;
-		return 0;
-	}
-
-	if (PCI_BUS(d) == hose->first_busno) {
-		addr = pcie->dbi + (where & ~0x3);
-	} else {
-		busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
-			 PCIE_ATU_DEV(PCI_DEV(d)) |
-			 PCIE_ATU_FUNC(PCI_FUNC(d));
-
-		if (PCI_BUS(d) == hose->first_busno + 1) {
-			ls_pcie_cfg0_set_busdev(pcie, busdev);
-			addr = pcie->va_cfg0 + (where & ~0x3);
-		} else {
-			ls_pcie_cfg1_set_busdev(pcie, busdev);
-			addr = pcie->va_cfg1 + (where & ~0x3);
-		}
-	}
-
-	*val = readl(addr);
-
-	return 0;
-}
-
-static int ls_pcie_write_config(struct pci_controller *hose, pci_dev_t d,
-				int where, u32 val)
-{
-	struct ls_pcie *pcie = hose->priv_data;
-	u32 busdev, *addr;
-
-	if (ls_pcie_addr_valid(hose, d))
-		return -EINVAL;
-
-	if (PCI_BUS(d) == hose->first_busno) {
-		addr = pcie->dbi + (where & ~0x3);
-	} else {
-		busdev = PCIE_ATU_BUS(PCI_BUS(d)) |
-			 PCIE_ATU_DEV(PCI_DEV(d)) |
-			 PCIE_ATU_FUNC(PCI_FUNC(d));
-
-		if (PCI_BUS(d) == hose->first_busno + 1) {
-			ls_pcie_cfg0_set_busdev(pcie, busdev);
-			addr = pcie->va_cfg0 + (where & ~0x3);
-		} else {
-			ls_pcie_cfg1_set_busdev(pcie, busdev);
-			addr = pcie->va_cfg1 + (where & ~0x3);
-		}
-	}
-
-	writel(val, addr);
-
-	return 0;
-}
-
-static void ls_pcie_setup_ctrl(struct ls_pcie *pcie,
-			       struct ls_pcie_info *info)
-{
-	struct pci_controller *hose = &pcie->hose;
-	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
-
-	ls_pcie_setup_atu(pcie, info);
-
-	pci_hose_write_config_dword(hose, dev, PCI_BASE_ADDRESS_0, 0);
-
-	/* program correct class for RC */
-	writel(1, pcie->dbi + PCIE_DBI_RO_WR_EN);
-	pci_hose_write_config_word(hose, dev, PCI_CLASS_DEVICE,
-				   PCI_CLASS_BRIDGE_PCI);
-#ifndef CONFIG_LS102XA
-	writel(0, pcie->dbi + PCIE_DBI_RO_WR_EN);
-#endif
-}
-
-static void ls_pcie_ep_setup_atu(struct ls_pcie *pcie,
-				 struct ls_pcie_info *info)
-{
-	u64 phys = CONFIG_SYS_PCI_EP_MEMORY_BASE;
-
-	/* ATU 0 : INBOUND : map BAR0 */
-	ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX0, 0, phys);
-	/* ATU 1 : INBOUND : map BAR1 */
-	phys += PCIE_BAR1_SIZE;
-	ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX1, 1, phys);
-	/* ATU 2 : INBOUND : map BAR2 */
-	phys += PCIE_BAR2_SIZE;
-	ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX2, 2, phys);
-	/* ATU 3 : INBOUND : map BAR4 */
-	phys = CONFIG_SYS_PCI_EP_MEMORY_BASE + PCIE_BAR4_SIZE;
-	ls_pcie_iatu_inbound_set(pcie, PCIE_ATU_REGION_INDEX3, 4, phys);
-
-	/* ATU 0 : OUTBOUND : map 4G MEM */
-	ls_pcie_iatu_outbound_set(pcie, PCIE_ATU_REGION_INDEX0,
-				  PCIE_ATU_TYPE_MEM,
-				  info->phys_base,
-				  0,
-				  4 * 1024 * 1024 * 1024ULL);
-}
-
-/* BAR0 and BAR1 are 32bit BAR2 and BAR4 are 64bit */
-static void ls_pcie_ep_setup_bar(void *bar_base, int bar, u32 size)
-{
-	if (size < 4 * 1024)
-		return;
-
-	switch (bar) {
-	case 0:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_0);
-		break;
-	case 1:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_1);
-		break;
-	case 2:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_2);
-		writel(0, bar_base + PCI_BASE_ADDRESS_3);
-		break;
-	case 4:
-		writel(size - 1, bar_base + PCI_BASE_ADDRESS_4);
-		writel(0, bar_base + PCI_BASE_ADDRESS_5);
-		break;
-	default:
-		break;
-	}
-}
-
-static void ls_pcie_ep_setup_bars(void *bar_base)
-{
-	/* BAR0 - 32bit - 4K configuration */
-	ls_pcie_ep_setup_bar(bar_base, 0, PCIE_BAR0_SIZE);
-	/* BAR1 - 32bit - 8K MSIX*/
-	ls_pcie_ep_setup_bar(bar_base, 1, PCIE_BAR1_SIZE);
-	/* BAR2 - 64bit - 4K MEM desciptor */
-	ls_pcie_ep_setup_bar(bar_base, 2, PCIE_BAR2_SIZE);
-	/* BAR4 - 64bit - 1M MEM*/
-	ls_pcie_ep_setup_bar(bar_base, 4, PCIE_BAR4_SIZE);
-}
-
-static void ls_pcie_setup_ep(struct ls_pcie *pcie, struct ls_pcie_info *info)
-{
-	struct pci_controller *hose = &pcie->hose;
-	pci_dev_t dev = PCI_BDF(hose->first_busno, 0, 0);
-	int sriov;
-
-	sriov = pci_hose_find_ext_capability(hose, dev, PCI_EXT_CAP_ID_SRIOV);
-	if (sriov) {
-		int pf, vf;
-
-		for (pf = 0; pf < PCIE_PF_NUM; pf++) {
-			for (vf = 0; vf <= PCIE_VF_NUM; vf++) {
-#ifndef CONFIG_LS102XA
-				writel(PCIE_LCTRL0_VAL(pf, vf),
-				       pcie->dbi + PCIE_LUT_BASE +
-				       PCIE_LUT_LCTRL0);
-#endif
-				ls_pcie_ep_setup_bars(pcie->dbi);
-				ls_pcie_ep_setup_atu(pcie, info);
-			}
-		}
-
-		/* Disable CFG2 */
-#ifndef CONFIG_LS102XA
-		writel(0, pcie->dbi + PCIE_LUT_BASE + PCIE_LUT_LCTRL0);
-#endif
-	} else {
-		ls_pcie_ep_setup_bars(pcie->dbi + PCIE_NO_SRIOV_BAR_BASE);
-		ls_pcie_ep_setup_atu(pcie, info);
-	}
-}
-
-int ls_pcie_init_ctrl(int busno, enum srds_prtcl dev, struct ls_pcie_info *info)
-{
-	struct ls_pcie *pcie;
-	struct pci_controller *hose;
-	int num = dev - PCIE1;
-	pci_dev_t pdev = PCI_BDF(busno, 0, 0);
-	int i, linkup, ep_mode;
-	u8 header_type;
-	u16 temp16;
-
-	if (!is_serdes_configured(dev)) {
-		printf("PCIe%d: disabled\n", num + 1);
-		return busno;
-	}
-
-	pcie = malloc(sizeof(*pcie));
-	if (!pcie)
-		return busno;
-	memset(pcie, 0, sizeof(*pcie));
-
-	hose = &pcie->hose;
-	hose->priv_data = pcie;
-	hose->first_busno = busno;
-	pcie->idx = num;
-	pcie->dbi = map_physmem(info->regs, PCIE_DBI_SIZE, MAP_NOCACHE);
-	pcie->va_cfg0 = map_physmem(info->cfg0_phys,
-				    info->cfg0_size,
-				    MAP_NOCACHE);
-	pcie->va_cfg1 = map_physmem(info->cfg1_phys,
-				    info->cfg1_size,
-				    MAP_NOCACHE);
-	pcie->next_lut_index = 0;
-
-	/* outbound memory */
-	pci_set_region(&hose->regions[0],
-		       (pci_size_t)info->mem_bus,
-		       (phys_size_t)info->mem_phys,
-		       (pci_size_t)info->mem_size,
-		       PCI_REGION_MEM);
-
-	/* outbound io */
-	pci_set_region(&hose->regions[1],
-		       (pci_size_t)info->io_bus,
-		       (phys_size_t)info->io_phys,
-		       (pci_size_t)info->io_size,
-		       PCI_REGION_IO);
-
-	/* System memory space */
-	pci_set_region(&hose->regions[2],
-		       CONFIG_SYS_PCI_MEMORY_BUS,
-		       CONFIG_SYS_PCI_MEMORY_PHYS,
-		       CONFIG_SYS_PCI_MEMORY_SIZE,
-		       PCI_REGION_SYS_MEMORY);
-
-	hose->region_count = 3;
-
-	for (i = 0; i < hose->region_count; i++)
-		debug("PCI reg:%d %016llx:%016llx %016llx %08lx\n",
-		      i,
-		      (u64)hose->regions[i].phys_start,
-		      (u64)hose->regions[i].bus_start,
-		      (u64)hose->regions[i].size,
-		      hose->regions[i].flags);
-
-	pci_set_ops(hose,
-		    pci_hose_read_config_byte_via_dword,
-		    pci_hose_read_config_word_via_dword,
-		    ls_pcie_read_config,
-		    pci_hose_write_config_byte_via_dword,
-		    pci_hose_write_config_word_via_dword,
-		    ls_pcie_write_config);
-
-	pci_hose_read_config_byte(hose, pdev, PCI_HEADER_TYPE, &header_type);
-	ep_mode = (header_type & 0x7f) == PCI_HEADER_TYPE_NORMAL;
-	printf("PCIe%u: %s ", info->pci_num,
-	       ep_mode ? "Endpoint" : "Root Complex");
-
-	if (ep_mode)
-		ls_pcie_setup_ep(pcie, info);
-	else
-		ls_pcie_setup_ctrl(pcie, info);
-
-	linkup = ls_pcie_link_up(pcie);
-
-	if (!linkup) {
-		/* Let the user know there's no PCIe link */
-		printf("no link, regs @ 0x%lx\n", info->regs);
-		hose->last_busno = hose->first_busno;
-		return busno;
-	}
-
-	/* Print the negotiated PCIe link width */
-	pci_hose_read_config_word(hose, pdev, PCIE_LINK_STA, &temp16);
-	printf("x%d gen%d, regs @ 0x%lx\n", (temp16 & 0x3f0) >> 4,
-	       (temp16 & 0xf), info->regs);
-
-	if (ep_mode)
-		return busno;
-
-	pci_register_hose(hose);
-
-	hose->last_busno = pci_hose_scan(hose);
-
-	printf("PCIe%x: Bus %02x - %02x\n",
-	       info->pci_num, hose->first_busno, hose->last_busno);
-
-	return hose->last_busno + 1;
-}
-
-int ls_pcie_init_board(int busno)
-{
-	struct ls_pcie_info info;
-
-#ifdef CONFIG_PCIE1
-	SET_LS_PCIE_INFO(info, 1);
-	busno = ls_pcie_init_ctrl(busno, PCIE1, &info);
-#endif
-
-#ifdef CONFIG_PCIE2
-	SET_LS_PCIE_INFO(info, 2);
-	busno = ls_pcie_init_ctrl(busno, PCIE2, &info);
-#endif
-
-#ifdef CONFIG_PCIE3
-	SET_LS_PCIE_INFO(info, 3);
-	busno = ls_pcie_init_ctrl(busno, PCIE3, &info);
-#endif
-
-#ifdef CONFIG_PCIE4
-	SET_LS_PCIE_INFO(info, 4);
-	busno = ls_pcie_init_ctrl(busno, PCIE4, &info);
-#endif
-
-	return busno;
-}
-
-void pci_init_board(void)
-{
-	ls_pcie_init_board(0);
-}
-
-#else
 LIST_HEAD(ls_pcie_list);
 
 static unsigned int dbi_readl(struct ls_pcie *pcie, unsigned int offset)

@@ -1045,4 +549,3 @@ U_BOOT_DRIVER(pci_layerscape) = {
 	.probe	= ls_pcie_probe,
 	.priv_auto_alloc_size = sizeof(struct ls_pcie),
 };
-#endif /* CONFIG_DM_PCI */

drivers/pci/pcie_layerscape.h +1 ~~-52~~

69 lines not on this page · raw message

drivers/pci/pcie_layerscape_fixup.c +0 ~~-167~~

180 lines not on this page · raw message

Signature · 1 line

2.1.0.27.g96db324

Zhiqiang Hou

author

2016-12-13 06:54 UTC #23 lore raw

PATCH v5 17/17 kconfig: move FSL_PCIE_COMPAT to platform Kconfig

From: Hou Zhiqiang <[email protected]>

---
V5:
- No change

 arch/arm/cpu/armv7/ls102xa/Kconfig        |  8 ++++++++
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 11 +++++++++++
 drivers/pci/pcie_layerscape_fixup.c       |  8 ++++----
 include/configs/ls1012aqds.h              |  1 -
 include/configs/ls1012ardb.h              |  1 -
 include/configs/ls1021aqds.h              |  1 -
 include/configs/ls1021atwr.h              |  1 -
 include/configs/ls1043a_common.h          |  1 -
 include/configs/ls2080a_common.h          |  3 ---
 9 files changed, 23 insertions(+), 12 deletions(-)

arch/arm/cpu/armv7/ls102xa/Kconfig +8 -0

index f94568a..8b6e50d 100644
@@ -92,4 +92,12 @@ config SYS_FSL_IFC_BANK_COUNT
 	depends on ARCH_LS1021A
 	default 8
 
+config FSL_PCIE_COMPAT
+	string "PCIe compatible of Kernel DT"
+	depends on PCIE_LAYERSCAPE
+	default "fsl,ls1021a-pcie" if ARCH_LS1021A
+	help
+	  This compatible is used to find pci controller node in Kernel DT
+	  to complete fixup.
+
 endmenu

arch/arm/cpu/armv8/fsl-layerscape/Kconfig +11 -0

index 6772584..b2fced1 100644
@@ -147,4 +147,15 @@ config SYS_FSL_DDR4
 	help
 	  Enable Freescale DDR4 controller.
 
+config FSL_PCIE_COMPAT
+	string "PCIe compatible of Kernel DT"
+	depends on PCIE_LAYERSCAPE
+	default "fsl,ls1012a-pcie" if ARCH_LS1012A
+	default "fsl,ls1043a-pcie" if ARCH_LS1043A
+	default "fsl,ls1046a-pcie" if ARCH_LS1046A
+	default "fsl,ls2080a-pcie" if ARCH_LS2080A
+	help
+	  This compatible is used to find pci controller node in Kernel DT
+	  to complete fixup.
+
 endmenu

drivers/pci/pcie_layerscape_fixup.c +4 -4

index 47e621f..19ede2f 100644
@@ -77,9 +77,9 @@ static void fdt_pcie_set_msi_map_entry(void *blob, struct ls_pcie *pcie,
 	nodeoffset = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
 						   pcie->dbi_res.start);
 	if (nodeoffset < 0) {
-#ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		nodeoffset = fdt_node_offset_by_compat_reg(blob,
-				FSL_PCIE_COMPAT, pcie->dbi_res.start);
+				CONFIG_FSL_PCIE_COMPAT, pcie->dbi_res.start);
 		if (nodeoffset < 0)
 			return;
 #else

@@ -150,9 +150,9 @@ static void ft_pcie_ls_setup(void *blob, struct ls_pcie *pcie)
 	off = fdt_node_offset_by_compat_reg(blob, "fsl,ls-pcie",
 					    pcie->dbi_res.start);
 	if (off < 0) {
-#ifdef FSL_PCIE_COMPAT /* Compatible with older version of dts node */
+#ifdef CONFIG_FSL_PCIE_COMPAT /* Compatible with older version of dts node */
 		off = fdt_node_offset_by_compat_reg(blob,
-						    FSL_PCIE_COMPAT,
+						    CONFIG_FSL_PCIE_COMPAT,
 						    pcie->dbi_res.start);
 		if (off < 0)
 			return;

include/configs/ls1012aqds.h +0 -1

index 0e4f6e3..cb30d10 100644
@@ -155,7 +155,6 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 #define CONFIG_PCIE1		/* PCIE controller 1 */
-#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_SCAN_SHOW

include/configs/ls1012ardb.h +0 -1

index d5573ba..3d9820d 100644
@@ -68,7 +68,6 @@
 #define CONFIG_SYS_SCSI_MAX_DEVICE		(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
 						CONFIG_SYS_SCSI_MAX_LUN)
 #define CONFIG_PCIE1		/* PCIE controller 1 */
-#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 
 #define CONFIG_NET_MULTI
 #define CONFIG_PCI_SCAN_SHOW

include/configs/ls1021aqds.h +0 -1

index ef8a43c..f362f43 100644
@@ -501,7 +501,6 @@ unsigned long get_board_ddr_clk(void);
 /* PCIe */
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
-#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_SCAN_SHOW

include/configs/ls1021atwr.h +0 -1

index 0e87319..e3f658e 100644
@@ -371,7 +371,6 @@
 /* PCIe */
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
-#define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 
 #ifdef CONFIG_PCI
 #define CONFIG_PCI_SCAN_SHOW

include/configs/ls1043a_common.h +0 -1

index 3600c4a..c89fd55 100644
@@ -118,7 +118,6 @@
 #define CONFIG_PCIE1		/* PCIE controller 1 */
 #define CONFIG_PCIE2		/* PCIE controller 2 */
 #define CONFIG_PCIE3		/* PCIE controller 3 */
-#define FSL_PCIE_COMPAT "fsl,ls1043a-pcie"
 
 #ifdef CONFIG_PCI
 #define CONFIG_NET_MULTI

include/configs/ls2080a_common.h +0 -3

index 805457d..eb628fd 100644
@@ -170,9 +170,6 @@ unsigned long long get_qixis_addr(void);
 #define CONFIG_SYS_MC_RSV_MEM_ALIGN			(512UL * 1024 * 1024)
 #endif
 
-/* PCIe */
-#define FSL_PCIE_COMPAT "fsl,ls2080a-pcie"
-
 /* Command line configuration */
 #define CONFIG_CMD_ENV

Signature · 1 line

2.1.0.27.g96db324

Simon Glass

2016-12-17 22:46 UTC #24 lore raw

PATCH v5 17/17 kconfig: move FSL_PCIE_COMPAT to platform Kconfig

Quoted 7 lines · Zhiqiang Hou

From: Hou Zhiqiang <[email protected]>
Signed-off-by Hou Zhiqiang <[email protected]>
---
V5:
- No change

Quoted 10 lines

 arch/arm/cpu/armv7/ls102xa/Kconfig        |  8 ++++++++
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 11 +++++++++++
 drivers/pci/pcie_layerscape_fixup.c       |  8 ++++----
 include/configs/ls1012aqds.h              |  1 -
 include/configs/ls1012ardb.h              |  1 -
 include/configs/ls1021aqds.h              |  1 -
 include/configs/ls1021atwr.h              |  1 -
 include/configs/ls1043a_common.h          |  1 -
 include/configs/ls2080a_common.h          |  3 ---
 9 files changed, 23 insertions(+), 12 deletions(-)

I wonder if anyone would really want to change this?

Z.Q. Hou

author

2016-12-19 02:51 UTC #25 lore raw

PATCH v5 17/17 kconfig: move FSL_PCIE_COMPAT to platform Kconfig

Hi Simon,

Thanks a lot for your review!

Quoted 33 lines

-----Original Message-----
From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
Sent: 2016?12?18? 6:47
To: Z.Q. Hou <[email protected]>
Cc: U-Boot Mailing List <[email protected]>; Albert ARIBAUD <[email protected]>; Prabhakar Kushwaha <[email protected]>; Alison Wang <[email protected]>; Sumit Garg <[email protected]>; Ruchika Gupta <[email protected]>; york sun <[email protected]>; M.H. Lian <[email protected]>; Bin Meng <[email protected]>; Mingkai Hu <[email protected]>
Subject: Re: [PATCHv5 17/17] kconfig: move FSL_PCIE_COMPAT to platform Kconfig
Quoted 7 lines · Zhiqiang Hou
From: Hou Zhiqiang <[email protected]>
Signed-off-by Hou Zhiqiang <[email protected]>
---
V5:
- No change
Quoted 10 lines
 arch/arm/cpu/armv7/ls102xa/Kconfig        |  8 ++++++++
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 11 +++++++++++
 drivers/pci/pcie_layerscape_fixup.c       |  8 ++++----
 include/configs/ls1012aqds.h              |  1 -
 include/configs/ls1012ardb.h              |  1 -
 include/configs/ls1021aqds.h              |  1 -
 include/configs/ls1021atwr.h              |  1 -
 include/configs/ls1043a_common.h          |  1 -
 include/configs/ls2080a_common.h          |  3 ---
 9 files changed, 23 insertions(+), 12 deletions(-)

Quoted 3 lines

Reviewed-by Simon Glass <[email protected]>
I wonder if anyone would really want to change this?

Anyway, better to use Kconfig.

Thanks,
Zhiqiang

Simon Glass

2016-12-17 22:46 UTC #26 lore raw

PATCH v5 1/17 configs: ls1021a: enable DT and DM support

Quoted 9 lines · Zhiqiang Hou

From: Hou Zhiqiang <[email protected]>
Enable DT to support Driver Model.
Signed-off-by Hou Zhiqiang <[email protected]>
---
V5:
- No change

Quoted 6 lines

 configs/ls1021aqds_nand_defconfig                   | 3 +++
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig        | 2 ++
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig        | 2 ++
 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++
 configs/ls1021atwr_sdcard_ifc_defconfig             | 3 +++
 5 files changed, 12 insertions(+)

Z.Q. Hou

author

2016-12-19 02:43 UTC #27 lore raw

PATCH v5 1/17 configs: ls1021a: enable DT and DM support

Hi Simon,

Thanks a lot for your review!

B.R
Zhiqiang

Quoted 31 lines

-----Original Message-----
From: sjg at google.com [mailto:sjg at google.com] On Behalf Of Simon Glass
Sent: 2016?12?18? 6:47
To: Z.Q. Hou <[email protected]>
Cc: U-Boot Mailing List <[email protected]>; Albert ARIBAUD <[email protected]>; Prabhakar Kushwaha <[email protected]>; Alison Wang <[email protected]>; Sumit Garg <[email protected]>; Ruchika Gupta <[email protected]>; york sun <[email protected]>; M.H. Lian <[email protected]>; Bin Meng <[email protected]>; Mingkai Hu <[email protected]>
Subject: Re: [PATCHv5 01/17] configs: ls1021a: enable DT and DM support
Quoted 9 lines · Zhiqiang Hou
From: Hou Zhiqiang <[email protected]>
Enable DT to support Driver Model.
Signed-off-by Hou Zhiqiang <[email protected]>
---
V5:
- No change
Quoted 6 lines
 configs/ls1021aqds_nand_defconfig                   | 3 +++
 configs/ls1021aqds_nor_SECURE_BOOT_defconfig        | 2 ++
 configs/ls1021atwr_nor_SECURE_BOOT_defconfig        | 2 ++
 configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 2 ++
 configs/ls1021atwr_sdcard_ifc_defconfig             | 3 +++
 5 files changed, 12 insertions(+)
Reviewed-by Simon Glass <[email protected]>

york sun

2017-01-19 17:27 UTC #28 lore raw

PATCH v5 1/17 configs: ls1021a: enable DT and DM support