drm/msm: Fixes for 4.11

PATCH New Jordan Crouse 2 participants 5 messages Mar 7, 2017 1 message not in the archive

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Jordan Crouse

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2017-03-07 16:50 UTC #0 lore raw

cover drm/msm: Fixes for 4.11

Hey Rob, here are a handful of things that might be fixable for 4.11 but if not consider them for -next.

Jordan

Jordan Crouse (4):
drm/msm: Fix wrong pointer check in a5xx_destroy
drm/msm: Don't increase priv->num_aspaces until we know that it fits drm/msm: Pass interrupt status to a5xx_rbbm_err_irq() drm/msm: Support 64 bit iova in RD_CMDSTREAM_ADDR

 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 22 +++++++++++++++-------
 drivers/gpu/drm/msm/msm_drv.c         |  7 +++----
 drivers/gpu/drm/msm/msm_rd.c          |  4 ++--
 3 files changed, 20 insertions(+), 13 deletions(-)

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Jordan Crouse

2017-03-07 16:50 UTC #2 lore raw

PATCH 1/4 drm/msm: Fix wrong pointer check in a5xx_destroy

Instead of checking for a5xx_gpu->gpmu_iova during destroy we accidently check a5xx_gpu->gpmu_bo.

Signed-off-by Jordan Crouse <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/gpu/drm/msm/adreno/a5xx_gpu.c +2 -2

index 71b30dd..cd30088 100644
@@ -1,4 +1,4 @@
-/* Copyright (c) 2016 The Linux Foundation. All rights reserved.
+/* Copyright (c) 2016-2017 The Linux Foundation. All rights reserved.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License version 2 and

@@ -768,7 +768,7 @@ static void a5xx_destroy(struct msm_gpu *gpu)
 	}
 
 	if (a5xx_gpu->gpmu_bo) {
-		if (a5xx_gpu->gpmu_bo)
+		if (a5xx_gpu->gpmu_iova)
 			msm_gem_put_iova(a5xx_gpu->gpmu_bo, gpu->id);
 		drm_gem_object_unreference_unlocked(a5xx_gpu->gpmu_bo);
 	}

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Jordan Crouse

2017-03-07 16:50 UTC #3 lore raw

PATCH 2/4 drm/msm: Don't increase priv->num_aspaces until we know that it fits

In reply to a message not in the archive

priv->num_aspaces is increased and then checked to see if it still fits in the priv->aspace array. If it doesn't, we warn and exit but priv->num_aspaces remains incremented.

Don't incremement the count until we know that it fits in the array.

Signed-off-by Jordan Crouse <[email protected]>

---
 drivers/gpu/drm/msm/msm_drv.c | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

drivers/gpu/drm/msm/msm_drv.c +3 -4

index 70226ea..a9a520f 100644
@@ -55,14 +55,13 @@ int msm_register_address_space(struct drm_device *dev,
 		struct msm_gem_address_space *aspace)
 {
 	struct msm_drm_private *priv = dev->dev_private;
-	int idx = priv->num_aspaces++;
 
-	if (WARN_ON(idx >= ARRAY_SIZE(priv->aspace)))
+	if (WARN_ON(priv->num_aspaces >= ARRAY_SIZE(priv->aspace)))
 		return -EINVAL;
 
-	priv->aspace[idx] = aspace;
+	priv->aspace[priv->num_aspaces] = aspace;
 
-	return idx;
+	return priv->num_aspaces++;
 }
 
 #ifdef CONFIG_DRM_MSM_REGISTER_LOGGING

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Jordan Crouse

2017-03-07 16:50 UTC #4 lore raw

PATCH 3/4 drm/msm: Pass interrupt status to a5xx_rbbm_err_irq()

In reply to a message not in the archive

The interrupt status was being cleared before processing the handlers. a5xx_rbbm_err_irq() was checking the interrupt status again, which would likely turn out bad because the interrupt status would be 0 (or at least different). Pass the original status to the function instead.

Also, skip clearing RBBM_AHB_ERROR from the interrupt status. The interrupt will keep firing until the error source is cleared. Skip the clear to avoid a storm until the error is cleared in a5xx_rbbm_err_irq().

Signed-off-by Jordan Crouse <[email protected]>

---
 drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 18 +++++++++++++-----
 1 file changed, 13 insertions(+), 5 deletions(-)

drivers/gpu/drm/msm/adreno/a5xx_gpu.c +13 -5

index cd30088..dfc9734 100644
@@ -872,10 +872,8 @@ static void a5xx_cp_err_irq(struct msm_gpu *gpu)
 	}
 }
 
-static void a5xx_rbbm_err_irq(struct msm_gpu *gpu)
+static void a5xx_rbbm_err_irq(struct msm_gpu *gpu, u32 status)
 {
-	u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS);
-
 	if (status & A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR) {
 		u32 val = gpu_read(gpu, REG_A5XX_RBBM_AHB_ERROR_STATUS);

@@ -887,6 +885,10 @@ static void a5xx_rbbm_err_irq(struct msm_gpu *gpu)
 
 		/* Clear the error */
 		gpu_write(gpu, REG_A5XX_RBBM_AHB_CMD, (1 << 4));
+
+		/* Clear the interrupt */
+		gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD,
+			A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR);
 	}
 
 	if (status & A5XX_RBBM_INT_0_MASK_RBBM_TRANSFER_TIMEOUT)

@@ -938,10 +940,16 @@ static irqreturn_t a5xx_irq(struct msm_gpu *gpu)
 {
 	u32 status = gpu_read(gpu, REG_A5XX_RBBM_INT_0_STATUS);
 
-	gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD, status);
+	/*
+	 * Clear all the interrupts except RBBM_AHB_ERROR - if we clear it
+	 * before the source is cleared the interrupt will storm.
+	 */
+	gpu_write(gpu, REG_A5XX_RBBM_INT_CLEAR_CMD,
+		status & ~A5XX_RBBM_INT_0_MASK_RBBM_AHB_ERROR);
 
+	/* Pass status to a5xx_rbbm_err_irq because we've already cleared it */
 	if (status & RBBM_ERROR_MASK)
-		a5xx_rbbm_err_irq(gpu);
+		a5xx_rbbm_err_irq(gpu, status);
 
 	if (status & A5XX_RBBM_INT_0_MASK_CP_HW_ERROR)
 		a5xx_cp_err_irq(gpu);

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Jordan Crouse

2017-03-07 16:50 UTC #5 lore raw

PATCH 4/4 drm/msm: Support 64 bit iova in RD_CMDSTREAM_ADDR

In reply to a message not in the archive

Output the upper 32 bits of a 64 bit iova in the RD_CMDSTREAM_ADDR section while maintaining backwards compatibility for tools that only understand 32 bit iovas.

Signed-off-by Jordan Crouse <[email protected]>

---
 drivers/gpu/drm/msm/msm_rd.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

drivers/gpu/drm/msm/msm_rd.c +2 -2

index 6607456..1e23132 100644
@@ -348,7 +348,7 @@ void msm_rd_dump_submit(struct msm_gem_submit *submit)
 	}
 
 	for (i = 0; i < submit->nr_cmds; i++) {
-		uint32_t iova = submit->cmd[i].iova;
+		uint64_t iova = submit->cmd[i].iova;
 		uint32_t szd  = submit->cmd[i].size; /* in dwords */
 
 		/* snapshot cmdstream bo's (if we haven't already): */

@@ -367,7 +367,7 @@ void msm_rd_dump_submit(struct msm_gem_submit *submit)
 		case MSM_SUBMIT_CMD_CTX_RESTORE_BUF:
 		case MSM_SUBMIT_CMD_BUF:
 			rd_write_section(rd, RD_CMDSTREAM_ADDR,
-					(uint32_t[2]){ iova, szd }, 8);
+				(uint32_t[3]){ iova, szd, iova >> 32 }, 12);
 			break;
 		}
 	}

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