iommu/arm-smmu: Add runtime pm/sleep support

The MMU400x/500 is the implementation of the SMMUv2 arch specification. It is split in to two blocks TBU, TCU. TBU caches the page table, instantiated for each master locally, clocked by the TBUn_clk. TCU manages the address translation with PTW and has the programming interface as well, clocked using the TCU_CLK. The TBU can also be sharing the same clock domain as TCU, in which case both are clocked using the TCU_CLK.

This defines the clock bindings for the same and adds the init, enable and disable functions for handling the clocks.

Signed-off-by Sricharan R <[email protected]>

---
 .../devicetree/bindings/iommu/arm,smmu.txt         | 27 ++++++
 drivers/iommu/arm-smmu.c                           | 95 +++++++++++++++++++++-
 2 files changed, 121 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/iommu/arm,smmu.txt +0 -0

index 6cdf32d..b369c13 100644

Documentation/devicetree/bindings/iommu/arm,smmu.txt +14 -0

+
+- clocks:         Phandles for respective clocks described by clock-names.
+
+- power-domains:  Phandles to SMMU's power domain specifier. This is
+                  required even if SMMU belongs to the master's power
+                  domain, as the SMMU will have to be enabled and
+                  accessed before master gets enabled and linked to its
+                  SMMU.
+
 ** Deprecated properties:
 
 - mmu-masters (deprecated in favour of the generic "iommus" binding) :

@@ -84,6 +106,11 @@ conditions.
                              <0 36 4>,
                              <0 37 4>;
                 #iommu-cells = <1>;
+                clocks = <&gcc GCC_SMMU_CFG_CLK>,
+                         <&gcc GCC_APSS_TCU_CLK>,
+			 <&gcc GCC_MDP_TBU_CLK>;
+
+		clock-names = "cfg_clk", "tcu_clk", "tbu_clk";
         };
 
         /* device with two stream IDs, 0 and 7 */

drivers/iommu/arm-smmu.c +94 -1

index f7e11d3..720a1ef 100644
@@ -341,6 +341,12 @@ struct arm_smmu_master_cfg {
 #define for_each_cfg_sme(fw, i, idx) \
 	for (i = 0; idx = fwspec_smendx(fw, i), i < fw->num_ids; ++i)
 
+struct mmu500_clk {
+	struct clk *cfg_clk;
+	struct clk *tcu_clk;
+	struct clk *tbu_clk;
+};
+
 struct arm_smmu_clks {
 	void *clks;
 	int (*init_clocks)(struct arm_smmu_device *smmu);

@@ -455,6 +461,92 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
 	return container_of(dom, struct arm_smmu_domain, domain);
 }
 
+static int mmu500_enable_clocks(struct arm_smmu_device *smmu)
+{
+	int ret = 0;
+	struct mmu500_clk *sclks = smmu->smmu_clks.clks;
+
+	if (!sclks)
+		return 0;
+
+	ret = clk_prepare_enable(sclks->cfg_clk);
+	if (ret) {
+		dev_err(smmu->dev, "Couldn't enable cfg_clk");
+		return ret;
+	}
+
+	ret = clk_prepare_enable(sclks->tcu_clk);
+	if (ret) {
+		dev_err(smmu->dev, "Couldn't enable tcu_clk");
+		clk_disable_unprepare(sclks->cfg_clk);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(sclks->tbu_clk);
+	if (ret) {
+		dev_err(smmu->dev, "Couln't enable tbu_clk");
+		clk_disable_unprepare(sclks->tcu_clk);
+		clk_disable_unprepare(sclks->cfg_clk);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void mmu500_disable_clocks(struct arm_smmu_device *smmu)
+{
+	struct mmu500_clk *sclks = smmu->smmu_clks.clks;
+
+	if (!sclks) {
+		clk_disable_unprepare(sclks->tbu_clk);
+		clk_disable_unprepare(sclks->tcu_clk);
+		clk_disable_unprepare(sclks->cfg_clk);
+	}
+}
+
+static int mmu500_init_clocks(struct arm_smmu_device *smmu)
+{
+	struct device *dev = smmu->dev;
+	struct mmu500_clk *sclks;
+	int err;
+
+	if (!of_find_property(dev->of_node, "clocks", NULL))
+		return 0;
+
+	sclks = devm_kzalloc(dev, sizeof(*sclks), GFP_KERNEL);
+	if (!sclks)
+		return -ENOMEM;
+
+	sclks->cfg_clk = devm_clk_get(dev, "cfg_clk");
+	if (IS_ERR(sclks->cfg_clk)) {
+		err = PTR_ERR(sclks->cfg_clk);
+		/* Ignore all, except -EPROBE_DEFER for optional clocks */
+		if (err == -EPROBE_DEFER)
+			return err;
+		else
+			sclks->cfg_clk = NULL;
+	}
+
+	sclks->tcu_clk = devm_clk_get(dev, "tcu_clk");
+	if (IS_ERR(sclks->tcu_clk)) {
+		dev_err(dev, "Couldn't get tcu_clk");
+		return PTR_ERR(sclks->tcu_clk);
+	}
+
+	sclks->tbu_clk = devm_clk_get(dev, "tbu_clk");
+	if (IS_ERR(sclks->tbu_clk)) {
+		err = PTR_ERR(sclks->tbu_clk);
+		/* Ignore all, ecept -EPROBE_DEFER for optional clocks */
+		if (err == -EPROBE_DEFER)
+			return err;
+		else
+			sclks->tbu_clk = NULL;
+	}
+
+	smmu->smmu_clks.clks = sclks;
+	return 0;
+}
+
 static void parse_driver_options(struct arm_smmu_device *smmu)
 {
 	int i = 0;

@@ -1981,7 +2073,8 @@ struct arm_smmu_match_data {
 		    NULL, NULL, NULL);
 ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU,
 		    NULL, NULL, NULL);
-ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500, NULL, NULL, NULL);
+ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500, mmu500_init_clocks,
+		    mmu500_enable_clocks, mmu500_disable_clocks);
 ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2,
 		    NULL, NULL, NULL);
 

Signature · 1 line

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Quoted 28 lines · Sricharan R

The MMU400x/500 is the implementation of the SMMUv2 arch specification. It is split in to two blocks TBU, TCU. TBU caches the page table, instantiated for each master locally, clocked by the TBUn_clk. TCU manages the address translation with PTW and has the programming interface as well, clocked using the TCU_CLK. The TBU can also be sharing the same clock domain as TCU, in which case both are clocked using the TCU_CLK.

This defines the clock bindings for the same and adds the init, enable and disable functions for handling the clocks.

Signed-off-by Sricharan R <[email protected]>

---
 .../devicetree/bindings/iommu/arm,smmu.txt         | 27 ++++++
 drivers/iommu/arm-smmu.c                           | 95 +++++++++++++++++++++-
 2 files changed, 121 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/iommu/arm,smmu.txt +0 -0

index 6cdf32d..b369c13 100644
@@ -60,6 +60,28 @@ conditions.
                   aliases of secure registers have to be used during
                   SMMU configuration.
 

Documentation/devicetree/bindings/iommu/arm,smmu.txt conditions. · line 63

Quoted 1 line

Documentation/devicetree/bindings/iommu/arm,smmu.txt +1 -0

+- clock-names:    Should be "tbu_clk" and "tcu_clk" and "cfg_clk" for

_clk is redundant

Documentation/devicetree/bindings/iommu/arm,smmu.txt conditions. · line 75

Quoted 13 lines

Documentation/devicetree/bindings/iommu/arm,smmu.txt +12 -0

+                  "arm,mmu-400", "arm,mmu-401" and "arm,mmu-500"
+
+                  "tcu_clk" is required for smmu's register access using the
+                  programming interface and ptw for downstream bus access.
+
+                  "tbu_clk" is required for access to the TBU connected to the
+                  master locally. This clock is optional and not required when
+                  TBU is in the same clock domain as the TCU or when the TBU is
+                  clocked along with the master.
+
+                  "cfg_clk" is optional if required to access the TCU's programming
+                  interface, apart from the "tcu_clk".

Clocks generally shouldn't be optional. Either the h/w has a clock or it doesn't.

Quoted 147 lines

Documentation/devicetree/bindings/iommu/arm,smmu.txt +14 -0

+
+- clocks:         Phandles for respective clocks described by clock-names.
+
+- power-domains:  Phandles to SMMU's power domain specifier. This is
+                  required even if SMMU belongs to the master's power
+                  domain, as the SMMU will have to be enabled and
+                  accessed before master gets enabled and linked to its
+                  SMMU.
+
 ** Deprecated properties:
 
 - mmu-masters (deprecated in favour of the generic "iommus" binding) :

@@ -84,6 +106,11 @@ conditions.
                              <0 36 4>,
                              <0 37 4>;
                 #iommu-cells = <1>;
+                clocks = <&gcc GCC_SMMU_CFG_CLK>,
+                         <&gcc GCC_APSS_TCU_CLK>,
+			 <&gcc GCC_MDP_TBU_CLK>;
+
+		clock-names = "cfg_clk", "tcu_clk", "tbu_clk";
         };
 
         /* device with two stream IDs, 0 and 7 */

drivers/iommu/arm-smmu.c +94 -2

index f7e11d3..720a1ef 100644
@@ -341,6 +341,12 @@ struct arm_smmu_master_cfg {
 #define for_each_cfg_sme(fw, i, idx) \
 	for (i = 0; idx = fwspec_smendx(fw, i), i < fw->num_ids; ++i)
 
+struct mmu500_clk {
+	struct clk *cfg_clk;
+	struct clk *tcu_clk;
+	struct clk *tbu_clk;
+};
+
 struct arm_smmu_clks {
 	void *clks;
 	int (*init_clocks)(struct arm_smmu_device *smmu);

@@ -455,6 +461,92 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
 	return container_of(dom, struct arm_smmu_domain, domain);
 }
 
+static int mmu500_enable_clocks(struct arm_smmu_device *smmu)
+{
+	int ret = 0;
+	struct mmu500_clk *sclks = smmu->smmu_clks.clks;
+
+	if (!sclks)
+		return 0;
+
+	ret = clk_prepare_enable(sclks->cfg_clk);
+	if (ret) {
+		dev_err(smmu->dev, "Couldn't enable cfg_clk");
+		return ret;
+	}
+
+	ret = clk_prepare_enable(sclks->tcu_clk);
+	if (ret) {
+		dev_err(smmu->dev, "Couldn't enable tcu_clk");
+		clk_disable_unprepare(sclks->cfg_clk);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(sclks->tbu_clk);
+	if (ret) {
+		dev_err(smmu->dev, "Couln't enable tbu_clk");
+		clk_disable_unprepare(sclks->tcu_clk);
+		clk_disable_unprepare(sclks->cfg_clk);
+		return ret;
+	}
+
+	return 0;
+}
+
+static void mmu500_disable_clocks(struct arm_smmu_device *smmu)
+{
+	struct mmu500_clk *sclks = smmu->smmu_clks.clks;
+
+	if (!sclks) {
+		clk_disable_unprepare(sclks->tbu_clk);
+		clk_disable_unprepare(sclks->tcu_clk);
+		clk_disable_unprepare(sclks->cfg_clk);
+	}
+}
+
+static int mmu500_init_clocks(struct arm_smmu_device *smmu)
+{
+	struct device *dev = smmu->dev;
+	struct mmu500_clk *sclks;
+	int err;
+
+	if (!of_find_property(dev->of_node, "clocks", NULL))
+		return 0;
+
+	sclks = devm_kzalloc(dev, sizeof(*sclks), GFP_KERNEL);
+	if (!sclks)
+		return -ENOMEM;
+
+	sclks->cfg_clk = devm_clk_get(dev, "cfg_clk");
+	if (IS_ERR(sclks->cfg_clk)) {
+		err = PTR_ERR(sclks->cfg_clk);
+		/* Ignore all, except -EPROBE_DEFER for optional clocks */
+		if (err == -EPROBE_DEFER)
+			return err;
+		else
+			sclks->cfg_clk = NULL;
+	}
+
+	sclks->tcu_clk = devm_clk_get(dev, "tcu_clk");
+	if (IS_ERR(sclks->tcu_clk)) {
+		dev_err(dev, "Couldn't get tcu_clk");
+		return PTR_ERR(sclks->tcu_clk);
+	}
+
+	sclks->tbu_clk = devm_clk_get(dev, "tbu_clk");
+	if (IS_ERR(sclks->tbu_clk)) {
+		err = PTR_ERR(sclks->tbu_clk);
+		/* Ignore all, ecept -EPROBE_DEFER for optional clocks */
+		if (err == -EPROBE_DEFER)
+			return err;
+		else
+			sclks->tbu_clk = NULL;
+	}
+
+	smmu->smmu_clks.clks = sclks;
+	return 0;
+}
+
 static void parse_driver_options(struct arm_smmu_device *smmu)
 {
 	int i = 0;

@@ -1981,7 +2073,8 @@ struct arm_smmu_match_data {
 		    NULL, NULL, NULL);
 ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU,
 		    NULL, NULL, NULL);
-ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500, NULL, NULL, NULL);
+ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500, mmu500_init_clocks,
+		    mmu500_enable_clocks, mmu500_disable_clocks);
 ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2,
 		    NULL, NULL, NULL);
 
--

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

The MMU400x/500 is the implementation of the SMMUv2 arch specification. It is split in to two blocks TBU, TCU. TBU caches the page table, instantiated for each master locally, clocked by the TBUn_clk. TCU manages the address translation with PTW and has the programming interface as well, clocked using the TCU_CLK. The TBU can also be sharing the same clock domain as TCU, in which case both are clocked using the TCU_CLK.

This defines the clock bindings for the same and adds the init, enable and disable functions for handling the clocks.

Signed-off-by Sricharan R <[email protected]>

---
 .../devicetree/bindings/iommu/arm,smmu.txt         | 27 ++++++
 drivers/iommu/arm-smmu.c                           | 95 +++++++++++++++++++++-
 2 files changed, 121 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/iommu/arm,smmu.txt +0 -0

index 6cdf32d..b369c13 100644

Documentation/devicetree/bindings/iommu/arm,smmu.txt +24 -0

+                  "tcu_clk" is required for smmu's register access using the
+                  programming interface and ptw for downstream bus access.
+
+                  "tbu_clk" is required for access to the TBU connected to the
+                  master locally. This clock is optional and not required when
+                  TBU is in the same clock domain as the TCU or when the TBU is
+                  clocked along with the master.
+
+                  "cfg_clk" is optional if required to access the TCU's programming
+                  interface, apart from the "tcu_clk".
+
+- clocks:         Phandles for respective clocks described by clock-names.
+
+- power-domains:  Phandles to SMMU's power domain specifier. This is
+                  required even if SMMU belongs to the master's power
+                  domain, as the SMMU will have to be enabled and
+                  accessed before master gets enabled and linked to its
+                  SMMU.
+
 ** Deprecated properties:
 
 - mmu-masters (deprecated in favour of the generic "iommus" binding) :

@@ -84,6 +106,11 @@ conditions.
                              <0 36 4>,
                              <0 37 4>;
                 #iommu-cells = <1>;
+                clocks = <&gcc GCC_SMMU_CFG_CLK>,
+                         <&gcc GCC_APSS_TCU_CLK>,
+                        <&gcc GCC_MDP_TBU_CLK>;
+
+               clock-names = "cfg_clk", "tcu_clk", "tbu_clk";
         };
 
         /* device with two stream IDs, 0 and 7 */

drivers/iommu/arm-smmu.c +94 -2

index f7e11d3..720a1ef 100644
@@ -341,6 +341,12 @@ struct arm_smmu_master_cfg {
 #define for_each_cfg_sme(fw, i, idx) \
        for (i = 0; idx = fwspec_smendx(fw, i), i < fw->num_ids; ++i)
 
+struct mmu500_clk {
+       struct clk *cfg_clk;
+       struct clk *tcu_clk;
+       struct clk *tbu_clk;
+};
+
 struct arm_smmu_clks {
        void *clks;
        int (*init_clocks)(struct arm_smmu_device *smmu);

@@ -455,6 +461,92 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
        return container_of(dom, struct arm_smmu_domain, domain);
 }
 
+static int mmu500_enable_clocks(struct arm_smmu_device *smmu)
+{
+       int ret = 0;
+       struct mmu500_clk *sclks = smmu->smmu_clks.clks;
+
+       if (!sclks)
+               return 0;
+
+       ret = clk_prepare_enable(sclks->cfg_clk);
+       if (ret) {
+               dev_err(smmu->dev, "Couldn't enable cfg_clk");
+               return ret;
+       }
+
+       ret = clk_prepare_enable(sclks->tcu_clk);
+       if (ret) {
+               dev_err(smmu->dev, "Couldn't enable tcu_clk");
+               clk_disable_unprepare(sclks->cfg_clk);
+               return ret;
+       }
+
+       ret = clk_prepare_enable(sclks->tbu_clk);
+       if (ret) {
+               dev_err(smmu->dev, "Couln't enable tbu_clk");
+               clk_disable_unprepare(sclks->tcu_clk);
+               clk_disable_unprepare(sclks->cfg_clk);
+               return ret;
+       }
+
+       return 0;
+}
+
+static void mmu500_disable_clocks(struct arm_smmu_device *smmu)
+{
+       struct mmu500_clk *sclks = smmu->smmu_clks.clks;
+
+       if (!sclks) {
+               clk_disable_unprepare(sclks->tbu_clk);
+               clk_disable_unprepare(sclks->tcu_clk);
+               clk_disable_unprepare(sclks->cfg_clk);
+       }
+}
+
+static int mmu500_init_clocks(struct arm_smmu_device *smmu)
+{
+       struct device *dev = smmu->dev;
+       struct mmu500_clk *sclks;
+       int err;
+
+       if (!of_find_property(dev->of_node, "clocks", NULL))
+               return 0;
+
+       sclks = devm_kzalloc(dev, sizeof(*sclks), GFP_KERNEL);
+       if (!sclks)
+               return -ENOMEM;
+
+       sclks->cfg_clk = devm_clk_get(dev, "cfg_clk");
+       if (IS_ERR(sclks->cfg_clk)) {
+               err = PTR_ERR(sclks->cfg_clk);
+               /* Ignore all, except -EPROBE_DEFER for optional clocks */
+               if (err == -EPROBE_DEFER)
+                       return err;
+               else
+                       sclks->cfg_clk = NULL;
+       }
+
+       sclks->tcu_clk = devm_clk_get(dev, "tcu_clk");
+       if (IS_ERR(sclks->tcu_clk)) {
+               dev_err(dev, "Couldn't get tcu_clk");
+               return PTR_ERR(sclks->tcu_clk);
+       }
+
+       sclks->tbu_clk = devm_clk_get(dev, "tbu_clk");
+       if (IS_ERR(sclks->tbu_clk)) {
+               err = PTR_ERR(sclks->tbu_clk);
+               /* Ignore all, ecept -EPROBE_DEFER for optional clocks */
+               if (err == -EPROBE_DEFER)
+                       return err;
+               else
+                       sclks->tbu_clk = NULL;
+       }
+
+       smmu->smmu_clks.clks = sclks;
+       return 0;
+}
+
 static void parse_driver_options(struct arm_smmu_device *smmu)
 {
        int i = 0;

@@ -1981,7 +2073,8 @@ struct arm_smmu_match_data {
                    NULL, NULL, NULL);
 ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU,
                    NULL, NULL, NULL);
-ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500, NULL, NULL, NULL);
+ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500, mmu500_init_clocks,
+                   mmu500_enable_clocks, mmu500_disable_clocks);
 ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2,
                    NULL, NULL, NULL);
 
--

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

_______________________________________________
iommu mailing list
iommu at lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

Quoted 25 lines · Sricharan R

The MMU400x/500 is the implementation of the SMMUv2 arch specification. It is split in to two blocks TBU, TCU. TBU caches the page table, instantiated for each master locally, clocked by the TBUn_clk. TCU manages the address translation with PTW and has the programming interface as well, clocked using the TCU_CLK. The TBU can also be sharing the same clock domain as TCU, in which case both are clocked using the TCU_CLK.

This defines the clock bindings for the same and adds the init, enable and disable functions for handling the clocks.

Signed-off-by Sricharan R <[email protected]>

---
 .../devicetree/bindings/iommu/arm,smmu.txt         | 27 ++++++
 drivers/iommu/arm-smmu.c                           | 95 +++++++++++++++++++++-
 2 files changed, 121 insertions(+), 1 deletion(-)

Documentation/devicetree/bindings/iommu/arm,smmu.txt +0 -0

index 6cdf32d..b369c13 100644

Documentation/devicetree/bindings/iommu/arm,smmu.txt conditions. · line 64

Quoted 5 lines

Documentation/devicetree/bindings/iommu/arm,smmu.txt +2 -0

@@ -60,6 +60,28 @@ conditions.
                   aliases of secure registers have to be used during
                   SMMU configuration.
 
+- clock-names:    Should be "tbu_clk" and "tcu_clk" and "cfg_clk" for
+                  "arm,mmu-400", "arm,mmu-401" and "arm,mmu-500"

I guess that should be: "Should be "tbu_clk" *or* "tcu_clk" and "cfg_clk" for..."

Also, possibly we should define our own compat strings for various SoC's that require these clks so we can properly describe when they are required? I guess that would address Rob H's comment.

BR,
-R

Quoted 157 lines

Documentation/devicetree/bindings/iommu/arm,smmu.txt +24 -0

+                  "tcu_clk" is required for smmu's register access using the
+                  programming interface and ptw for downstream bus access.
+
+                  "tbu_clk" is required for access to the TBU connected to the
+                  master locally. This clock is optional and not required when
+                  TBU is in the same clock domain as the TCU or when the TBU is
+                  clocked along with the master.
+
+                  "cfg_clk" is optional if required to access the TCU's programming
+                  interface, apart from the "tcu_clk".
+
+- clocks:         Phandles for respective clocks described by clock-names.
+
+- power-domains:  Phandles to SMMU's power domain specifier. This is
+                  required even if SMMU belongs to the master's power
+                  domain, as the SMMU will have to be enabled and
+                  accessed before master gets enabled and linked to its
+                  SMMU.
+
 ** Deprecated properties:
 
 - mmu-masters (deprecated in favour of the generic "iommus" binding) :

@@ -84,6 +106,11 @@ conditions.
                              <0 36 4>,
                              <0 37 4>;
                 #iommu-cells = <1>;
+                clocks = <&gcc GCC_SMMU_CFG_CLK>,
+                         <&gcc GCC_APSS_TCU_CLK>,
+                        <&gcc GCC_MDP_TBU_CLK>;
+
+               clock-names = "cfg_clk", "tcu_clk", "tbu_clk";
         };
 
         /* device with two stream IDs, 0 and 7 */

drivers/iommu/arm-smmu.c +94 -2

index f7e11d3..720a1ef 100644
@@ -341,6 +341,12 @@ struct arm_smmu_master_cfg {
 #define for_each_cfg_sme(fw, i, idx) \
        for (i = 0; idx = fwspec_smendx(fw, i), i < fw->num_ids; ++i)
 
+struct mmu500_clk {
+       struct clk *cfg_clk;
+       struct clk *tcu_clk;
+       struct clk *tbu_clk;
+};
+
 struct arm_smmu_clks {
        void *clks;
        int (*init_clocks)(struct arm_smmu_device *smmu);

@@ -455,6 +461,92 @@ static struct arm_smmu_domain *to_smmu_domain(struct iommu_domain *dom)
        return container_of(dom, struct arm_smmu_domain, domain);
 }
 
+static int mmu500_enable_clocks(struct arm_smmu_device *smmu)
+{
+       int ret = 0;
+       struct mmu500_clk *sclks = smmu->smmu_clks.clks;
+
+       if (!sclks)
+               return 0;
+
+       ret = clk_prepare_enable(sclks->cfg_clk);
+       if (ret) {
+               dev_err(smmu->dev, "Couldn't enable cfg_clk");
+               return ret;
+       }
+
+       ret = clk_prepare_enable(sclks->tcu_clk);
+       if (ret) {
+               dev_err(smmu->dev, "Couldn't enable tcu_clk");
+               clk_disable_unprepare(sclks->cfg_clk);
+               return ret;
+       }
+
+       ret = clk_prepare_enable(sclks->tbu_clk);
+       if (ret) {
+               dev_err(smmu->dev, "Couln't enable tbu_clk");
+               clk_disable_unprepare(sclks->tcu_clk);
+               clk_disable_unprepare(sclks->cfg_clk);
+               return ret;
+       }
+
+       return 0;
+}
+
+static void mmu500_disable_clocks(struct arm_smmu_device *smmu)
+{
+       struct mmu500_clk *sclks = smmu->smmu_clks.clks;
+
+       if (!sclks) {
+               clk_disable_unprepare(sclks->tbu_clk);
+               clk_disable_unprepare(sclks->tcu_clk);
+               clk_disable_unprepare(sclks->cfg_clk);
+       }
+}
+
+static int mmu500_init_clocks(struct arm_smmu_device *smmu)
+{
+       struct device *dev = smmu->dev;
+       struct mmu500_clk *sclks;
+       int err;
+
+       if (!of_find_property(dev->of_node, "clocks", NULL))
+               return 0;
+
+       sclks = devm_kzalloc(dev, sizeof(*sclks), GFP_KERNEL);
+       if (!sclks)
+               return -ENOMEM;
+
+       sclks->cfg_clk = devm_clk_get(dev, "cfg_clk");
+       if (IS_ERR(sclks->cfg_clk)) {
+               err = PTR_ERR(sclks->cfg_clk);
+               /* Ignore all, except -EPROBE_DEFER for optional clocks */
+               if (err == -EPROBE_DEFER)
+                       return err;
+               else
+                       sclks->cfg_clk = NULL;
+       }
+
+       sclks->tcu_clk = devm_clk_get(dev, "tcu_clk");
+       if (IS_ERR(sclks->tcu_clk)) {
+               dev_err(dev, "Couldn't get tcu_clk");
+               return PTR_ERR(sclks->tcu_clk);
+       }
+
+       sclks->tbu_clk = devm_clk_get(dev, "tbu_clk");
+       if (IS_ERR(sclks->tbu_clk)) {
+               err = PTR_ERR(sclks->tbu_clk);
+               /* Ignore all, ecept -EPROBE_DEFER for optional clocks */
+               if (err == -EPROBE_DEFER)
+                       return err;
+               else
+                       sclks->tbu_clk = NULL;
+       }
+
+       smmu->smmu_clks.clks = sclks;
+       return 0;
+}
+
 static void parse_driver_options(struct arm_smmu_device *smmu)
 {
        int i = 0;

@@ -1981,7 +2073,8 @@ struct arm_smmu_match_data {
                    NULL, NULL, NULL);
 ARM_SMMU_MATCH_DATA(arm_mmu401, ARM_SMMU_V1_64K, GENERIC_SMMU,
                    NULL, NULL, NULL);
-ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500, NULL, NULL, NULL);
+ARM_SMMU_MATCH_DATA(arm_mmu500, ARM_SMMU_V2, ARM_MMU500, mmu500_init_clocks,
+                   mmu500_enable_clocks, mmu500_disable_clocks);
 ARM_SMMU_MATCH_DATA(cavium_smmuv2, ARM_SMMU_V2, CAVIUM_SMMUV2,
                    NULL, NULL, NULL);
 
--

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Quoted 4 lines

_______________________________________________
iommu mailing list
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https://lists.linuxfoundation.org/mailman/listinfo/iommu

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The QCOM_SMMUV2 is an implementation of the arm,smmu-v2 architecture. The qcom,smmu is instantiated for each of the multimedia cores (for eg) Venus (video encoder/decoder), mdp (display) etc, and they are connected to the Multimedia Aggregator Interconnect (MMAGIC). So the access to any of the MMU's registers, as well as MMU's downstream bus access, requires the specified MMAGIC clocks to be enabled. So adding a new binding for the qcom,smmu-v2 and the required mmagic clock bindings for the same. Also adding the support for enabling the qcom,smmu-v2 clocks in the driver.

               -------------  ---------
               |   VENUS   |  | MDP   |
	       |	   |  |       |
	       -------------  --------
		     |           |
		     |           |
                  ------      ---------
                  |SMMU |     | SMMU  |
                  |	|     |       |
                  ------      --------
		    |            |
		    |            |
       -----------------------------------------
       |	MMAGIC INTERCONNECT (MMSS NOC) |
       |                                       |
       -----------------------------------------
                   |                 |
		   |           ----------------------------------
                 -----         | 	SYSTEM NOC		|
                 |DDR|	       |				|
                 -----         ---------------------------------
		   |		    |
                   |               ------
		   |<-------------| CPU|
				  ------

Signed-off-by Sricharan R <[email protected]>

---
 .../devicetree/bindings/iommu/arm,smmu.txt         |   8 ++
 drivers/iommu/arm-smmu.c                           | 124 +++++++++++++++++++++
 2 files changed, 132 insertions(+)

Documentation/devicetree/bindings/iommu/arm,smmu.txt +0 -0

index b369c13..88e02d6 100644

Documentation/devicetree/bindings/iommu/arm,smmu.txt +4 -0

+
+		  "mmagic_core_axi_clk" is required for smmu's access to the
+                   downstream bus and rest for the smmu's register group access.
+
 - clocks:         Phandles for respective clocks described by clock-names.
 
 - power-domains:  Phandles to SMMU's power domain specifier. This is

Quoted 42 lines · Sricharan R

The QCOM_SMMUV2 is an implementation of the arm,smmu-v2 architecture. The qcom,smmu is instantiated for each of the multimedia cores (for eg) Venus (video encoder/decoder), mdp (display) etc, and they are connected to the Multimedia Aggregator Interconnect (MMAGIC). So the access to any of the MMU's registers, as well as MMU's downstream bus access, requires the specified MMAGIC clocks to be enabled. So adding a new binding for the qcom,smmu-v2 and the required mmagic clock bindings for the same. Also adding the support for enabling the qcom,smmu-v2 clocks in the driver.

               -------------  ---------
               |   VENUS   |  | MDP   |
	       |	   |  |       |
	       -------------  --------
		     |           |
		     |           |
                  ------      ---------
                  |SMMU |     | SMMU  |
                  |	|     |       |
                  ------      --------
		    |            |
		    |            |
       -----------------------------------------
       |	MMAGIC INTERCONNECT (MMSS NOC) |
       |                                       |
       -----------------------------------------
                   |                 |
		   |           ----------------------------------
                 -----         | 	SYSTEM NOC		|
                 |DDR|	       |				|
                 -----         ---------------------------------
		   |		    |
                   |               ------
		   |<-------------| CPU|
				  ------

Signed-off-by Sricharan R <[email protected]>

---
 .../devicetree/bindings/iommu/arm,smmu.txt         |   8 ++
 drivers/iommu/arm-smmu.c                           | 124 +++++++++++++++++++++
 2 files changed, 132 insertions(+)

Documentation/devicetree/bindings/iommu/arm,smmu.txt conditions. · line 20

Quoted 9 lines

Documentation/devicetree/bindings/iommu/arm,smmu.txt +1 -0

index b369c13..88e02d6 100644
@@ -17,6 +17,7 @@ conditions.
                         "arm,mmu-401"
                         "arm,mmu-500"
                         "cavium,smmu-v2"
+			"qcom,smmu-v2"

I know Cavium did it, but I'd prefer to see SoC specific compatibles here.

Quoted 8 lines

Documentation/devicetree/bindings/iommu/arm,smmu.txt +0 -0

                   depending on the particular implementation and/or the
                   version of the architecture implemented.

@@ -74,6 +75,13 @@ conditions.
                   "cfg_clk" is optional if required to access the TCU's programming
                   interface, apart from the "tcu_clk".
 

Documentation/devicetree/bindings/iommu/arm,smmu.txt conditions. · line 80

Quoted 3 lines

Documentation/devicetree/bindings/iommu/arm,smmu.txt +3 -0

+		  Should have "mmagic_ahb_clk", "mmagic_cfg_ahb_clk",
+                              "smmu_core_ahb_clk", "smmu_core_axi_clk",
+                              "mmagic_core_axi_clk" for "qcom,smmu-v2"

This is instead of the above clocks?

Are these clocks all really part of the SMMU or are the mmagic clocks working around no proper driver for the mmagic?

Documentation/devicetree/bindings/iommu/arm,smmu.txt conditions. · line 87

Quoted 7 lines

Documentation/devicetree/bindings/iommu/arm,smmu.txt +4 -0

+
+		  "mmagic_core_axi_clk" is required for smmu's access to the
+                   downstream bus and rest for the smmu's register group access.
+
 - clocks:         Phandles for respective clocks described by clock-names.
 
 - power-domains:  Phandles to SMMU's power domain specifier. This is

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel at lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

This series provides the support for turning on the arm-smmu's clocks/power domains using runtime pm. This is done using the recently introduced device links patches, which lets the symmu's runtime to follow the master's runtime pm, so the smmu remains powered only when the masters use it.

Took some reference from the exynos runtime patches [2]. Tested this with MDP, GPU, VENUS devices on apq8096-db820c board.

Previous version of the patchset [1].

[V3]
* Reworked the patches to keep the clocks init/enabling function seperately for each compatible.

* Added clocks bindings for MMU40x/500.

* Added a new compatible for qcom,smmu-v2 implementation and the clock bindings for the same.

* Rebased on top of 4.11-rc1

[V2]
* Split the patches little differently.

* Addressed comments.

* Removed the patch #4 [3] from previous post for arm-smmu context save restore. Planning to post this separately after reworking/addressing Robin's feedback.

* Reversed the sequence to disable clocks than enabling. This was required for those cases where the clocks are populated in a dependent order from DT.

[1] https://www.spinics.net/lists/linux-arm-msm/msg23870.html
[2] https://lkml.org/lkml/2016/10/20/70
[3] https://patchwork.kernel.org/patch/9389717/

Sricharan R (5):
iommu/arm-smmu: Add pm_runtime/sleep ops iommu/arm-smmu: Add support for MMU40x/500 clocks
drivers: arm-smmu: Add clock support for QCOM_SMMUV2 iommu/arm-smmu: Invoke pm_runtime during probe, add/remove device iommu/arm-smmu: Add the device_link between masters and smmu

 .../devicetree/bindings/iommu/arm,smmu.txt         |  35 +++
 drivers/iommu/arm-smmu.c                           | 349 ++++++++++++++++++++-
 2 files changed, 373 insertions(+), 11 deletions(-)

Signature · 1 line

QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

Quoted 5 lines · Sricharan R

This series provides the support for turning on the arm-smmu's clocks/power domains using runtime pm. This is done using the recently introduced device links patches, which lets the symmu's runtime to follow the master's runtime pm, so the smmu remains powered only when the masters use it.

Do you have any numbers for the power savings you achieve with this? How often do we actually manage to stop the SMMU clocks on an SoC with a handful of masters?

In other words, is this too coarse-grained to be useful, or is it common that all the devices upstream of the SMMU are suspended?

Thanks,

Will

Quoted 42 lines

Took some reference from the exynos runtime patches [2]. Tested this with MDP, GPU, VENUS devices on apq8096-db820c board.

Previous version of the patchset [1].

[V3]
* Reworked the patches to keep the clocks init/enabling function seperately for each compatible.

* Added clocks bindings for MMU40x/500.

* Added a new compatible for qcom,smmu-v2 implementation and the clock bindings for the same.

* Rebased on top of 4.11-rc1

[V2]
* Split the patches little differently.

* Addressed comments.

* Removed the patch #4 [3] from previous post for arm-smmu context save restore. Planning to post this separately after reworking/addressing Robin's feedback.

* Reversed the sequence to disable clocks than enabling. This was required for those cases where the clocks are populated in a dependent order from DT.

[1] https://www.spinics.net/lists/linux-arm-msm/msg23870.html
[2] https://lkml.org/lkml/2016/10/20/70
[3] https://patchwork.kernel.org/patch/9389717/

Sricharan R (5):
iommu/arm-smmu: Add pm_runtime/sleep ops iommu/arm-smmu: Add support for MMU40x/500 clocks
drivers: arm-smmu: Add clock support for QCOM_SMMUV2 iommu/arm-smmu: Invoke pm_runtime during probe, add/remove device iommu/arm-smmu: Add the device_link between masters and smmu

Quoted 7 lines

 .../devicetree/bindings/iommu/arm,smmu.txt         |  35 +++
 drivers/iommu/arm-smmu.c                           | 349 ++++++++++++++++++++-
 2 files changed, 373 insertions(+), 11 deletions(-)

--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation

_______________________________________________
iommu mailing list
iommu at lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

Quoted 11 lines · Will Deacon

Quoted 5 lines · Sricharan R

This series provides the support for turning on the arm-smmu's clocks/power domains using runtime pm. This is done using the recently introduced device links patches, which lets the symmu's runtime to follow the master's runtime pm, so the smmu remains powered only when the masters use it.

Do you have any numbers for the power savings you achieve with this? How often do we actually manage to stop the SMMU clocks on an SoC with a handful of masters?

Quoted 2 lines

In other words, is this too coarse-grained to be useful, or is it common that all the devices upstream of the SMMU are suspended?

well, if you think about a phone/tablet with a command mode panel, pretty much all devices will be suspended most of the time ;-)

Quoted 15 lines · Rob Clark

Quoted 13 lines · Will Deacon

Quoted 5 lines · Sricharan R

This series provides the support for turning on the arm-smmu's clocks/power domains using runtime pm. This is done using the recently introduced device links patches, which lets the symmu's runtime to follow the master's runtime pm, so the smmu remains powered only when the masters use it.

Do you have any numbers for the power savings you achieve with this? How often do we actually manage to stop the SMMU clocks on an SoC with a handful of masters?

In other words, is this too coarse-grained to be useful, or is it common that all the devices upstream of the SMMU are suspended?

Quoted 2 lines

well, if you think about a phone/tablet with a command mode panel, pretty much all devices will be suspended most of the time ;-)

Well, that's really what I was asking about. I assumed that periodic modem/radio transactions would keep the SMMU clocked, so would like to get a rough idea of the power savings achieved with this coarse-grained approach.

Quoted 15 lines · Rob Clark

Quoted 13 lines · Will Deacon

Quoted 5 lines · Sricharan R

This series provides the support for turning on the arm-smmu's clocks/power domains using runtime pm. This is done using the recently introduced device links patches, which lets the symmu's runtime to follow the master's runtime pm, so the smmu remains powered only when the masters use it.

Do you have any numbers for the power savings you achieve with this? How often do we actually manage to stop the SMMU clocks on an SoC with a handful of masters?

In other words, is this too coarse-grained to be useful, or is it common that all the devices upstream of the SMMU are suspended?

Quoted 2 lines

well, if you think about a phone/tablet with a command mode panel, pretty much all devices will be suspended most of the time ;-)

Well, that's really what I was asking about. I assumed that periodic modem/radio transactions would keep the SMMU clocked, so would like to get a rough idea of the power savings achieved with this coarse-grained approach.

Quoted 16 lines · Will Deacon

Quoted 15 lines · Rob Clark

Quoted 13 lines · Will Deacon

Quoted 5 lines · Sricharan R

This series provides the support for turning on the arm-smmu's clocks/power domains using runtime pm. This is done using the recently introduced device links patches, which lets the symmu's runtime to follow the master's runtime pm, so the smmu remains powered only when the masters use it.

Do you have any numbers for the power savings you achieve with this? How often do we actually manage to stop the SMMU clocks on an SoC with a handful of masters?

In other words, is this too coarse-grained to be useful, or is it common that all the devices upstream of the SMMU are suspended?

Quoted 6 lines

Quoted 2 lines

well, if you think about a phone/tablet with a command mode panel, pretty much all devices will be suspended most of the time ;-)

Well, that's really what I was asking about. I assumed that periodic modem/radio transactions would keep the SMMU clocked, so would like to get a rough idea of the power savings achieved with this coarse-grained approach.

Sometimes we distribute SMMUs to each IP block in the system and let each one of those live in their own clock + power domain. In these cases, the SMMU can be powered down along with the only IP block that uses it. Furthermore, sometimes we put the IP block and the SMMU inside the same power domain to really tie the two together, so we definitely have cases where all devices (device?) upstream of the SMMU are suspended. And in the case of multimedia, it could be very often that something like the camera app isn't open and thus the SMMU dedicated for the camera can be powered down.

Other times we have two SMMUs in the system where one is dedicated to GPU and the other is "everything else". Even in these cases, we can suspend the GPU one when the GPU is inactive because it's the only consumer. The other SMMU might not be as fine grained, but I think we still power it down quite often because the consumers are mostly multimedia devices that aren't active when the display is off.

Quoted 35 lines · Stephen Boyd

Quoted 16 lines · Will Deacon

Quoted 15 lines · Rob Clark

Quoted 13 lines · Will Deacon

Quoted 5 lines · Sricharan R

This series provides the support for turning on the arm-smmu's clocks/power domains using runtime pm. This is done using the recently introduced device links patches, which lets the symmu's runtime to follow the master's runtime pm, so the smmu remains powered only when the masters use it.

Do you have any numbers for the power savings you achieve with this? How often do we actually manage to stop the SMMU clocks on an SoC with a handful of masters?

In other words, is this too coarse-grained to be useful, or is it common that all the devices upstream of the SMMU are suspended?

Quoted 6 lines

Quoted 2 lines

well, if you think about a phone/tablet with a command mode panel, pretty much all devices will be suspended most of the time ;-)

Well, that's really what I was asking about. I assumed that periodic modem/radio transactions would keep the SMMU clocked, so would like to get a rough idea of the power savings achieved with this coarse-grained approach.

Sometimes we distribute SMMUs to each IP block in the system and let each one of those live in their own clock + power domain. In these cases, the SMMU can be powered down along with the only IP block that uses it. Furthermore, sometimes we put the IP block and the SMMU inside the same power domain to really tie the two together, so we definitely have cases where all devices (device?) upstream of the SMMU are suspended. And in the case of multimedia, it could be very often that something like the camera app isn't open and thus the SMMU dedicated for the camera can be powered down.

Quoted 7 lines

Other times we have two SMMUs in the system where one is dedicated to GPU and the other is "everything else". Even in these cases, we can suspend the GPU one when the GPU is inactive because it's the only consumer. The other SMMU might not be as fine grained, but I think we still power it down quite often because the consumers are mostly multimedia devices that aren't active when the display is off.

And just to confuse things even further: with per-instance pagetables we have an interest in forcing the SMMU clocks *on* because we don't know when the GPU might try to hit the registers to switch a pagetable and if somebody in the pipeline is actively trying to do power management at the same time hilarity will ensue.

The alternative to pm_runtime is the downstream driver that probes the SMMU clocks from DT and frobs them itself. I think we can agree that is far less reasonable.