FAILED: patch "[PATCH] drm/nouveau/pci/g92: Fix rearm" failed to apply to 4.10-stable tree

From 5112abc6a43372b2c1934717ed9bf132a427c46c Mon Sep 17 00:00:00 2001

The patch below does not apply to the 4.10-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

From 5112abc6a43372b2c1934717ed9bf132a427c46c Mon Sep 17 00:00:00 2001
From: Karol Herbst <[email protected]>
Date: Sat, 11 Feb 2017 12:58:17 +0100
Subject: [PATCH] drm/nouveau/pci/g92: Fix rearm

704a6c008b7942bb7f30bb43d2a6bcad7f543662 broke pci msi rearm for g92 GPUs.

g92 needs the nv46_pci_msi_rearm, where g94+ gpus used nv40_pci_msi_rearm.

Reported-by Andrew Randrianasulu <[email protected]>

Signed-off-by Karol Herbst <[email protected]>

Signed-off-by Ben Skeggs <[email protected]>

Cc [email protected]

drivers/gpu/drm/nouveau/include/nvkm/subdev/pci.h +1 -0

index 2592d86a787b..ac2a695963c1 100644
@@ -44,6 +44,7 @@ int nv46_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int nv4c_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int g84_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int g92_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
+int g94_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int gf100_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int gf106_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
 int gk104_pci_new(struct nvkm_device *, int, struct nvkm_pci **);

drivers/gpu/drm/nouveau/nvkm/engine/device/base.c +10 -10

index f40273cd94e3..273562dd6bbd 100644
@@ -1025,7 +1025,7 @@ nv94_chipset = {
        .mc = g84_mc_new,
        .mmu = nv50_mmu_new,
        .mxm = nv50_mxm_new,
-       .pci = g92_pci_new,
+       .pci = g94_pci_new,
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,

@@ -1057,7 +1057,7 @@ nv96_chipset = {
        .mc = g84_mc_new,
        .mmu = nv50_mmu_new,
        .mxm = nv50_mxm_new,
-       .pci = g92_pci_new,
+       .pci = g94_pci_new,
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,

@@ -1089,7 +1089,7 @@ nv98_chipset = {
        .mc = g98_mc_new,
        .mmu = nv50_mmu_new,
        .mxm = nv50_mxm_new,
-       .pci = g92_pci_new,
+       .pci = g94_pci_new,
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,

@@ -1121,7 +1121,7 @@ nva0_chipset = {
        .mc = g84_mc_new,
        .mmu = nv50_mmu_new,
        .mxm = nv50_mxm_new,
-       .pci = g92_pci_new,
+       .pci = g94_pci_new,
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,

@@ -1153,7 +1153,7 @@ nva3_chipset = {
        .mc = gt215_mc_new,
        .mmu = nv50_mmu_new,
        .mxm = nv50_mxm_new,
-       .pci = g92_pci_new,
+       .pci = g94_pci_new,
        .pmu = gt215_pmu_new,
        .therm = gt215_therm_new,
        .timer = nv41_timer_new,

@@ -1187,7 +1187,7 @@ nva5_chipset = {
        .mc = gt215_mc_new,
        .mmu = nv50_mmu_new,
        .mxm = nv50_mxm_new,
-       .pci = g92_pci_new,
+       .pci = g94_pci_new,
        .pmu = gt215_pmu_new,
        .therm = gt215_therm_new,
        .timer = nv41_timer_new,

@@ -1220,7 +1220,7 @@ nva8_chipset = {
        .mc = gt215_mc_new,
        .mmu = nv50_mmu_new,
        .mxm = nv50_mxm_new,
-       .pci = g92_pci_new,
+       .pci = g94_pci_new,
        .pmu = gt215_pmu_new,
        .therm = gt215_therm_new,
        .timer = nv41_timer_new,

@@ -1253,7 +1253,7 @@ nvaa_chipset = {
        .mc = g98_mc_new,
        .mmu = nv50_mmu_new,
        .mxm = nv50_mxm_new,
-       .pci = g92_pci_new,
+       .pci = g94_pci_new,
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,

@@ -1285,7 +1285,7 @@ nvac_chipset = {
        .mc = g98_mc_new,
        .mmu = nv50_mmu_new,
        .mxm = nv50_mxm_new,
-       .pci = g92_pci_new,
+       .pci = g94_pci_new,
        .therm = g84_therm_new,
        .timer = nv41_timer_new,
        .volt = nv40_volt_new,

@@ -1317,7 +1317,7 @@ nvaf_chipset = {
        .mc = gt215_mc_new,
        .mmu = nv50_mmu_new,
        .mxm = nv50_mxm_new,
-       .pci = g92_pci_new,
+       .pci = g94_pci_new,
        .pmu = gt215_pmu_new,
        .therm = gt215_therm_new,
        .timer = nv41_timer_new,

drivers/gpu/drm/nouveau/nvkm/subdev/pci/Kbuild +1 -0

index cdb7ce227aed..87bf41cef0c6 100644
@@ -7,6 +7,7 @@ nvkm-y += nvkm/subdev/pci/nv46.o
 nvkm-y += nvkm/subdev/pci/nv4c.o
 nvkm-y += nvkm/subdev/pci/g84.o
 nvkm-y += nvkm/subdev/pci/g92.o
+nvkm-y += nvkm/subdev/pci/g94.o
 nvkm-y += nvkm/subdev/pci/gf100.o
 nvkm-y += nvkm/subdev/pci/gf106.o
 nvkm-y += nvkm/subdev/pci/gk104.o

drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.c +1 -1

index 654607e0faf3..48874359d5f6 100644
@@ -37,7 +37,7 @@ g92_pci_func = {
        .rd32 = nv40_pci_rd32,
        .wr08 = nv40_pci_wr08,
        .wr32 = nv40_pci_wr32,
-       .msi_rearm = nv40_pci_msi_rearm,
+       .msi_rearm = nv46_pci_msi_rearm,
 
        .pcie.init = g84_pcie_init,
        .pcie.set_link = g84_pcie_set_link,

drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.c new file +49 -0

new file mode 100644
index 000000000000..09adb37a5664
@@ -0,0 +1,49 @@
+/*
+ * Copyright 2015 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs <[email protected]>
+ */
+#include "priv.h"
+
+static const struct nvkm_pci_func
+g94_pci_func = {
+       .init = g84_pci_init,
+       .rd32 = nv40_pci_rd32,
+       .wr08 = nv40_pci_wr08,
+       .wr32 = nv40_pci_wr32,
+       .msi_rearm = nv40_pci_msi_rearm,
+
+       .pcie.init = g84_pcie_init,
+       .pcie.set_link = g84_pcie_set_link,
+
+       .pcie.max_speed = g84_pcie_max_speed,
+       .pcie.cur_speed = g84_pcie_cur_speed,
+
+       .pcie.set_version = g84_pcie_set_version,
+       .pcie.version = g84_pcie_version,
+       .pcie.version_supported = g92_pcie_version_supported,
+};
+
+int
+g94_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+{
+       return nvkm_pci_new_(&g94_pci_func, device, index, ppci);
+}