Revert "drm/amdgpu: update tile table for oland/hainan"

PATCH Applied Jean Delvare 4 participants 6 messages Mar 2, 2017 – Mar 12, 2017

Subsystems (3)

Stable branch DRM drivers Radeon and amdgpu DRM drivers

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Jean Delvare

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2017-03-02 17:33 UTC #0 lore raw

PATCH 1/1 Revert "drm/amdgpu: update tile table for oland/hainan"

Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan") as it is causing ugly visual artifacts on at least Oland. This is only an optimization so we can live without it.

This fixes kernel bug #194761:
amdgpu driver breaks on Oland (SI)
https://bugzilla.kernel.org/show_bug.cgi?id=194761

Signed-off-by Jean Delvare <[email protected]>

Fixes f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")

Cc Flora Cui <[email protected]>

Cc Junwei Zhang <[email protected]>

Cc Alex Deucher <[email protected]>

---
Note: This is for stable v4.10 branch only. v4.11 and later have a different fix, but it's much larger and more intrusive so not suitable for a stable branch.

 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  330 ++++++++++++++--------------------
 1 file changed, 139 insertions(+), 191 deletions(-)

drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +139 ~~-191~~

@@ -708,290 +708,238 @@ static void gfx_v6_0_tiling_mode_table_i
 		for (reg_offset = 0; reg_offset < num_tile_mode_states; reg_offset++) {
 			switch (reg_offset) {
 			case 0:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-						 NUM_BANKS(ADDR_SURF_16_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 				break;
 			case 1:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-						 NUM_BANKS(ADDR_SURF_16_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 				break;
 			case 2:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-						 NUM_BANKS(ADDR_SURF_16_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 				break;
 			case 3:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_8_BANK) |
-						 TILE_SPLIT(split_equal_to_row_size));
+						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 				break;
 			case 4:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2));
+				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
+						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 5:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
-						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+						 TILE_SPLIT(split_equal_to_row_size) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_8_BANK));
+						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 6:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
-						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+						 TILE_SPLIT(split_equal_to_row_size) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_8_BANK));
+						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 7:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
-						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+						 TILE_SPLIT(split_equal_to_row_size) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_4_BANK));
+						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 				break;
 			case 8:
-				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
+				gb_tile_moden = (ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
+						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 9:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2));
+				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
+						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 10:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-						 NUM_BANKS(ADDR_SURF_16_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 				break;
 			case 11:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-						 NUM_BANKS(ADDR_SURF_16_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 12:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-						 NUM_BANKS(ADDR_SURF_16_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 13:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2));
+				gb_tile_moden = (ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
+						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 14:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-						 NUM_BANKS(ADDR_SURF_16_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 15:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-						 NUM_BANKS(ADDR_SURF_16_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 16:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-						 NUM_BANKS(ADDR_SURF_16_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 17:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
-						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-						 NUM_BANKS(ADDR_SURF_16_BANK) |
-						 TILE_SPLIT(split_equal_to_row_size));
-				break;
-			case 18:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-						 PIPE_CONFIG(ADDR_SURF_P2));
-				break;
-			case 19:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
-						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+						 TILE_SPLIT(split_equal_to_row_size) |
 						 NUM_BANKS(ADDR_SURF_16_BANK) |
-						 TILE_SPLIT(split_equal_to_row_size));
-				break;
-			case 20:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-						 NUM_BANKS(ADDR_SURF_16_BANK) |
-						 TILE_SPLIT(split_equal_to_row_size));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 21:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_8_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 22:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_8_BANK));
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
+						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
 				break;
 			case 23:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_8_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 24:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+						 NUM_BANKS(ADDR_SURF_16_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_8_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
 				break;
 			case 25:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
+				gb_tile_moden = (ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+						 MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+						 PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
 						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_4_BANK));
-				break;
-			case 26:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
-						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_4_BANK));
-				break;
-			case 27:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
-						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_4_BANK));
-				break;
-			case 28:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
-						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_4_BANK));
-				break;
-			case 29:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
-						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_4_BANK));
-				break;
-			case 30:
-				gb_tile_moden = (MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-						 ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-						 PIPE_CONFIG(ADDR_SURF_P2) |
-						 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+						 NUM_BANKS(ADDR_SURF_8_BANK) |
 						 BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
 						 BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-						 NUM_BANKS(ADDR_SURF_4_BANK));
+						 MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
 				break;
 			default:
-				continue;
+				gb_tile_moden = 0;
+				break;
 			}
 			adev->gfx.config.tile_mode_array[reg_offset] = gb_tile_moden;
 			WREG32(mmGB_TILE_MODE0 + reg_offset, gb_tile_moden);

Signature · 2 lines

Jean Delvare
SUSE L3 Support

Deucher, Alexander

maintainer Acked-by on v1 1/1

2017-03-02 18:34 UTC #1 lore raw

Quoted 15 lines

-----Original Message-----
From: Jean Delvare [mailto:[email protected]]
Sent: Thursday, March 02, 2017 12:22 PM
To: [email protected]
Cc: Cui, Flora; Zhang, Jerry; Deucher, Alexander
Subject: [PATCH] Revert "drm/amdgpu: update tile table for oland/hainan"
Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan") as it is causing ugly visual artifacts on at least Oland. This is only an optimization so we can live without it.
This fixes kernel bug #194761:
amdgpu driver breaks on Oland (SI)
https://bugzilla.kernel.org/show_bug.cgi?id=194761

Quoted 5 lines

Signed-off-by Jean Delvare <[email protected]>
Fixes f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
Cc Flora Cui <[email protected]>
Cc Junwei Zhang <[email protected]>
Cc Alex Deucher <[email protected]>

Acked-by Alex Deucher <[email protected]>

Quoted 809 lines

---
Note: This is for stable v4.10 branch only. v4.11 and later have a different fix, but it's much larger and more intrusive so not suitable for a stable branch.
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  330 ++++++++++++++----------
----------
 1 file changed, 139 insertions(+), 191 deletions(-)
--- linux-4.10.orig/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 2017-02-19
23:34:00.000000000 +0100
+++ linux-4.10/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c 2017-03-02
18:10:45.786414946 +0100
(quoted diff) +0 -1
@@ -708,290 +708,238 @@ static void gfx_v6_0_tiling_mode_table_i
 		for (reg_offset = 0; reg_offset < num_tile_mode_states;
 reg_offset++) {
 			switch (reg_offset) {
 			case 0:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-
NUM_BANKS(ADDR_SURF_16_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
(quoted diff) +0 -1
 				break;
 			case 1:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-
NUM_BANKS(ADDR_SURF_16_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
(quoted diff) +0 -1
 				break;
 			case 2:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-
NUM_BANKS(ADDR_SURF_16_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
(quoted diff) +0 -1
 				break;
 			case 3:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_128B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_8_BANK) |
-
TILE_SPLIT(split_equal_to_row_size));
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
(quoted diff) +0 -1
 				break;
 			case 4:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2));
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
(quoted diff) +0 -1
 				break;
 			case 5:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+
TILE_SPLIT(split_equal_to_row_size) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_8_BANK));
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
(quoted diff) +0 -1
 				break;
 			case 6:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+
TILE_SPLIT(split_equal_to_row_size) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_8_BANK));
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
(quoted diff) +0 -1
 				break;
 			case 7:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DEPTH_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+
TILE_SPLIT(split_equal_to_row_size) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_4_BANK));
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
(quoted diff) +0 -1
 				break;
 			case 8:
-				gb_tile_moden =
(ARRAY_MODE(ARRAY_LINEAR_ALIGNED));
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_LINEAR_ALIGNED) |
+
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
(quoted diff) +0 -1
 				break;
 			case 9:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | -
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2));
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 10:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | -
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4) |
-
NUM_BANKS(ADDR_SURF_16_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 11:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | -
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-
NUM_BANKS(ADDR_SURF_16_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 12:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) | -
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_DISPLAY_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-
NUM_BANKS(ADDR_SURF_16_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 13:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2));
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_1D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 14:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-
NUM_BANKS(ADDR_SURF_16_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 15:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-
NUM_BANKS(ADDR_SURF_16_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 16:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-
NUM_BANKS(ADDR_SURF_16_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 17:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-
NUM_BANKS(ADDR_SURF_16_BANK) |
-
TILE_SPLIT(split_equal_to_row_size));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -3
-				break;
-			case 18:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_1D_TILED_THICK) |
-
PIPE_CONFIG(ADDR_SURF_P2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -3
-				break;
-			case 19:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_XTHICK) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P4_8x16) |
+
TILE_SPLIT(split_equal_to_row_size) |
NUM_BANKS(ADDR_SURF_16_BANK) |
-
TILE_SPLIT(split_equal_to_row_size));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -3
-				break;
-			case 20:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THICK) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2) |
-
NUM_BANKS(ADDR_SURF_16_BANK) |
-
TILE_SPLIT(split_equal_to_row_size));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 21:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_8_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 22:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_2) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_8_BANK));
+
NUM_BANKS(ADDR_SURF_16_BANK) |
+
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
+
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_4) |
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_4));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 23:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_256B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_8_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 24:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_512B) |
+
NUM_BANKS(ADDR_SURF_16_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_8_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_2));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -1
 				break;
 			case 25:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
(quoted diff) +1 -0
+				gb_tile_moden =
(ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
+
MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
+
PIPE_CONFIG(ADDR_SURF_P8_32x32_8x16) |
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_4_BANK));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -3
-				break;
-			case 26:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_4_BANK));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -3
-				break;
-			case 27:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_4_BANK));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -3
-				break;
-			case 28:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_4_BANK));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -3
-				break;
-			case 29:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_1KB) |
-
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
-
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_2) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_4_BANK));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +0 -3
-				break;
-			case 30:
-				gb_tile_moden =
(MICRO_TILE_MODE(ADDR_SURF_THIN_MICRO_TILING) |
-
ARRAY_MODE(ARRAY_2D_TILED_THIN1) |
-
PIPE_CONFIG(ADDR_SURF_P2) |
-
TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) |
+
NUM_BANKS(ADDR_SURF_8_BANK) |
BANK_WIDTH(ADDR_SURF_BANK_WIDTH_1) |
BANK_HEIGHT(ADDR_SURF_BANK_HEIGHT_1) |
-
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1) |
-
NUM_BANKS(ADDR_SURF_4_BANK));
+
MACRO_TILE_ASPECT(ADDR_SURF_MACRO_ASPECT_1));
drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c +2 -1
 				break;
 			default:
-				continue;
+				gb_tile_moden = 0;
+				break;
 			}
 			adev->gfx.config.tile_mode_array[reg_offset] =
gb_tile_moden;
WREG32(mmGB_TILE_MODE0 + reg_offset,
gb_tile_moden);
--
Jean Delvare
SUSE L3 Support

Greg KH

2017-03-02 20:37 UTC #2 lore raw

In reply to Jean Delvare

Quoted 13 lines · Jean Delvare

Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan") as it is causing ugly visual artifacts on at least Oland. This is only an optimization so we can live without it.
This fixes kernel bug #194761:
amdgpu driver breaks on Oland (SI)
https://bugzilla.kernel.org/show_bug.cgi?id=194761
Signed-off-by Jean Delvare <[email protected]>
Fixes f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
Cc Flora Cui <[email protected]>
Cc Junwei Zhang <[email protected]>
Cc Alex Deucher <[email protected]>

Quoted 7 lines

---
Note: This is for stable v4.10 branch only. v4.11 and later have a different fix, but it's much larger and more intrusive so not suitable for a stable branch.
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  330 ++++++++++++++--------------------
 1 file changed, 139 insertions(+), 191 deletions(-)

More intrusive than this? I'd much rather take what is in 4.11 than have you make a huge change like this if at all possible.

thanks,

greg k-h

Jean Delvare

author

2017-03-03 01:53 UTC #3 lore raw

Hi Greg,

Quoted 19 lines · Greg KH

Quoted 18 lines · Jean Delvare
Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan") as it is causing ugly visual artifacts on at least Oland. This is only an optimization so we can live without it.
This fixes kernel bug #194761:
amdgpu driver breaks on Oland (SI)
https://bugzilla.kernel.org/show_bug.cgi?id=194761
Signed-off-by Jean Delvare <[email protected]>
Fixes f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
Cc Flora Cui <[email protected]>
Cc Junwei Zhang <[email protected]>
Cc Alex Deucher <[email protected]>
---
Note: This is for stable v4.10 branch only. v4.11 and later have a different fix, but it's much larger and more intrusive so not suitable for a stable branch.

Quoted 5 lines

Quoted 2 lines
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  330 ++++++++++++++--------------------
 1 file changed, 139 insertions(+), 191 deletions(-)
More intrusive than this? I'd much rather take what is in 4.11 than have you make a huge change like this if at all possible.

I agree it's not small, but it is just a revert. So it gets you back to 4.9 state, which is known good and well tested.

If you insist on going into the other direction, Flora Cui says we need to backport 7 commits, the combined diffstat of which looks like:

 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  216 +++++++++++++---------------------
 drivers/gpu/drm/amd/amdgpu/si.c       |   90 +++++++++++---
 drivers/gpu/drm/amd/amdgpu/si_enums.h |    4 
 3 files changed, 162 insertions(+), 148 deletions(-)

So barely better IMHO, and I have not tested it, I don't know yet how easy that will be to backport nor if it actually solves the problem.

Personally I'd rather revert one bad commit than backport 7, but I'm not the maintainer of the amdgpu driver and not responsible for the 4.10 stable branch either, so obviously it's not my call.

Thanks,

Signature · 2 lines

Jean Delvare
SUSE L3 Support

Deucher, Alexander

maintainer

2017-03-02 23:02 UTC #4 lore raw

Quoted 49 lines

-----Original Message-----
From: Jean Delvare [mailto:[email protected]]
Sent: Thursday, March 02, 2017 4:05 PM
To: Greg KH
Cc: [email protected]; Cui, Flora; Zhang, Jerry; Deucher, Alexander
Subject: Re: [PATCH] Revert "drm/amdgpu: update tile table for oland/hainan"
Hi Greg,
Quoted 19 lines · Greg KH
Quoted 18 lines · Jean Delvare
Revert commit f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan") as it is causing ugly visual artifacts on at least Oland. This is only an optimization so we can live without it.
This fixes kernel bug #194761:
amdgpu driver breaks on Oland (SI)
https://bugzilla.kernel.org/show_bug.cgi?id=194761
Signed-off-by Jean Delvare <[email protected]>
Fixes f8d9422ef80c ("drm/amdgpu: update tile table for oland/hainan")
Cc Flora Cui <[email protected]>
Cc Junwei Zhang <[email protected]>
Cc Alex Deucher <[email protected]>
---
Note: This is for stable v4.10 branch only. v4.11 and later have a different fix, but it's much larger and more intrusive so not suitable for a stable branch.
Quoted 1 line
Quoted 1 line
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  330 ++++++++++++++------
--------------
Quoted 4 lines
Quoted 1 line
 1 file changed, 139 insertions(+), 191 deletions(-)
More intrusive than this? I'd much rather take what is in 4.11 than have you make a huge change like this if at all possible.
I agree it's not small, but it is just a revert. So it gets you back to 4.9 state, which is known good and well tested.
If you insist on going into the other direction, Flora Cui says we need to backport 7 commits, the combined diffstat of which looks like:
 drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c |  216 +++++++++++++------------
---------
 drivers/gpu/drm/amd/amdgpu/si.c       |   90 +++++++++++---
 drivers/gpu/drm/amd/amdgpu/si_enums.h |    4
 3 files changed, 162 insertions(+), 148 deletions(-)

Quoted 6 lines

So barely better IMHO, and I have not tested it, I don't know yet how easy that will be to backport nor if it actually solves the problem.
Personally I'd rather revert one bad commit than backport 7, but I'm not the maintainer of the amdgpu driver and not responsible for the 4.10 stable branch either, so obviously it's not my call.

SI asic support in amdgpu is experimental. The radeon driver is still the preferred driver for SI asics as it is stable and supports more features. It would be nice to fix up the 4.10 branch for people that want to experiment with SI support in amdgpu, so the revert seems easier in my opinion.

Alex

[email protected]

maintainer Applied

2017-03-12 19:21 UTC #5 lore raw

Patch "Revert "drm/amdgpu: update tile table for oland/hainan"" has been added to the 4.10-stable tree

In reply to Jean Delvare

This is a note to let you know that I've just added the patch titled

Revert "drm/amdgpu: update tile table for oland/hainan"

to the 4.10-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
revert-drm-amdgpu-update-tile-table-for-oland-hainan.patch
and it can be found in the queue-4.10 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From [email protected] Sun Mar 12 19:44:04 2017

From: Jean Delvare <[email protected]>
Date: Thu, 2 Mar 2017 18:21:35 +0100
Subject: Revert "drm/amdgpu: update tile table for oland/hainan"
To: [email protected]
Cc: Flora Cui <[email protected]>, Junwei Zhang <[email protected]>, Alex Deucher <[email protected]>
Message-ID: <20170302182135.3afe11e1@endymion>

From: Jean Delvare <[email protected]>