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crypto: caam - add Queue Interface (QI) support

RFC New Horia Geantă 3 participants 12 messages Mar 3, 2017 – Mar 16, 2017

Subsystems (3)
Crypto API Freescale SoC drivers Freescale CAAM (Cryptographic Acceleration and Assurance Module) driver
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Horia Geantă

author maintainer
#0 lore raw

cover crypto: caam - add Queue Interface (QI) support

The patchset adds support for CAAM Queue Interface (QI), the additional interface (besides job ring) available for submitting jobs to the engine on platforms having DPAA (Datapath Acceleration Architecture).

Patches 1-4 are QMan dependencies.
I would prefer to take them through the crypto tree, but I am open to suggestions.

Patch 5 adds a missing double inclusion guard in desc_constr.h.

Patch 6 adds the caam/qi job submission backend.

Patch 7 adds algorithms (ablkcipher and authenc) that run on top of caam/qi. For now, their priority is set lower than caam/jr.

Thanks,
Horia

Horia Geant? (7):
soc/qman: export volatile dequeue related structs soc/qman: add dedicated channel ID for CAAM soc/qman: export non-programmable FQD fields query soc/qman: add helper functions needed by caam/qi driver
crypto: caam - avoid double inclusion in desc_constr.h
crypto: caam - add Queue Interface (QI) backend support
crypto: caam/qi - add ablkcipher and authenc algorithms

 drivers/crypto/caam/Kconfig             |   20 +-
 drivers/crypto/caam/Makefile            |    5 +
 drivers/crypto/caam/caamalg.c           |    9 +-
 drivers/crypto/caam/caamalg_desc.c      |   77 +-
 drivers/crypto/caam/caamalg_desc.h      |   15 +-
 drivers/crypto/caam/caamalg_qi.c        | 2387 +++++++++++++++++++++++++++++++
 drivers/crypto/caam/ctrl.c              |   58 +-
 drivers/crypto/caam/desc_constr.h       |    5 +
 drivers/crypto/caam/intern.h            |   24 +
 drivers/crypto/caam/qi.c                |  805 +++++++++++
 drivers/crypto/caam/qi.h                |  201 +++
 drivers/crypto/caam/sg_sw_qm.h          |  107 ++
 drivers/soc/fsl/qbman/qman.c            |   20 +-
 drivers/soc/fsl/qbman/qman_ccsr.c       |    6 +-
 drivers/soc/fsl/qbman/qman_priv.h       |   97 --
 drivers/soc/fsl/qbman/qman_test_stash.c |    5 +-
 include/soc/fsl/qman.h                  |  154 ++
 17 files changed, 3839 insertions(+), 156 deletions(-)
 create mode 100644 drivers/crypto/caam/caamalg_qi.c
 create mode 100644 drivers/crypto/caam/qi.c
 create mode 100644 drivers/crypto/caam/qi.h
 create mode 100644 drivers/crypto/caam/sg_sw_qm.h
Signature · 1 line
2.4.4
author maintainer
#1 lore raw

RFC 1/7 soc/qman: export volatile dequeue related structs

Since qman_volatile_dequeue() is already exported, move the related structures into the public header too.

Signed-off-by Horia Geant? <[email protected]>
---
 drivers/soc/fsl/qbman/qman_priv.h | 36 ------------------------------------
 include/soc/fsl/qman.h            | 36 ++++++++++++++++++++++++++++++++++++
 2 files changed, 36 insertions(+), 36 deletions(-)
drivers/soc/fsl/qbman/qman_priv.h +0 -36
index 53685b59718e..64781eff6974 100644
@@ -271,42 +271,6 @@ const struct qm_portal_config *qman_destroy_affine_portal(void);
  */
 int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd);
 
-/*
- * For qman_volatile_dequeue(); Choose one PRECEDENCE. EXACT is optional. Use
- * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use
- * FQID(n) to fill in the frame queue ID.
- */
-#define QM_VDQCR_PRECEDENCE_VDQCR	0x0
-#define QM_VDQCR_PRECEDENCE_SDQCR	0x80000000
-#define QM_VDQCR_EXACT			0x40000000
-#define QM_VDQCR_NUMFRAMES_MASK		0x3f000000
-#define QM_VDQCR_NUMFRAMES_SET(n)	(((n) & 0x3f) << 24)
-#define QM_VDQCR_NUMFRAMES_GET(n)	(((n) >> 24) & 0x3f)
-#define QM_VDQCR_NUMFRAMES_TILLEMPTY	QM_VDQCR_NUMFRAMES_SET(0)
-
-#define QMAN_VOLATILE_FLAG_WAIT	     0x00000001 /* wait if VDQCR is in use */
-#define QMAN_VOLATILE_FLAG_WAIT_INT  0x00000002 /* if wait, interruptible? */
-#define QMAN_VOLATILE_FLAG_FINISH    0x00000004 /* wait till VDQCR completes */
-
-/*
- * qman_volatile_dequeue - Issue a volatile dequeue command
- * @fq: the frame queue object to dequeue from
- * @flags: a bit-mask of QMAN_VOLATILE_FLAG_*** options
- * @vdqcr: bit mask of QM_VDQCR_*** options, as per qm_dqrr_vdqcr_set()
- *
- * Attempts to lock access to the portal's VDQCR volatile dequeue functionality.
- * The function will block and sleep if QMAN_VOLATILE_FLAG_WAIT is specified and
- * the VDQCR is already in use, otherwise returns non-zero for failure. If
- * QMAN_VOLATILE_FLAG_FINISH is specified, the function will only return once
- * the VDQCR command has finished executing (ie. once the callback for the last
- * DQRR entry resulting from the VDQCR command has been called). If not using
- * the FINISH flag, completion can be determined either by detecting the
- * presence of the QM_DQRR_STAT_UNSCHEDULED and QM_DQRR_STAT_DQCR_EXPIRED bits
- * in the "stat" parameter passed to the FQ's dequeue callback, or by waiting
- * for the QMAN_FQ_STATE_VDQCR bit to disappear.
- */
-int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr);
-
 int qman_alloc_fq_table(u32 num_fqids);
 
 /*   QMan s/w corenet portal, low-level i/face	 */
include/soc/fsl/qman.h +36 -0
index 3d4df74a96de..4de1ffcc8982 100644
@@ -791,6 +791,23 @@ struct qman_cgr {
 #define QMAN_INITFQ_FLAG_SCHED	     0x00000001 /* schedule rather than park */
 #define QMAN_INITFQ_FLAG_LOCAL	     0x00000004 /* set dest portal */
 
+/*
+ * For qman_volatile_dequeue(); Choose one PRECEDENCE. EXACT is optional. Use
+ * NUMFRAMES(n) (6-bit) or NUMFRAMES_TILLEMPTY to fill in the frame-count. Use
+ * FQID(n) to fill in the frame queue ID.
+ */
+#define QM_VDQCR_PRECEDENCE_VDQCR	0x0
+#define QM_VDQCR_PRECEDENCE_SDQCR	0x80000000
+#define QM_VDQCR_EXACT			0x40000000
+#define QM_VDQCR_NUMFRAMES_MASK		0x3f000000
+#define QM_VDQCR_NUMFRAMES_SET(n)	(((n) & 0x3f) << 24)
+#define QM_VDQCR_NUMFRAMES_GET(n)	(((n) >> 24) & 0x3f)
+#define QM_VDQCR_NUMFRAMES_TILLEMPTY	QM_VDQCR_NUMFRAMES_SET(0)
+
+#define QMAN_VOLATILE_FLAG_WAIT	     0x00000001 /* wait if VDQCR is in use */
+#define QMAN_VOLATILE_FLAG_WAIT_INT  0x00000002 /* if wait, interruptible? */
+#define QMAN_VOLATILE_FLAG_FINISH    0x00000004 /* wait till VDQCR completes */
+
 	/* Portal Management */
 /**
  * qman_p_irqsource_add - add processing sources to be interrupt-driven

@@ -963,6 +980,25 @@ int qman_retire_fq(struct qman_fq *fq, u32 *flags);
  */
 int qman_oos_fq(struct qman_fq *fq);
 
+/*
+ * qman_volatile_dequeue - Issue a volatile dequeue command
+ * @fq: the frame queue object to dequeue from
+ * @flags: a bit-mask of QMAN_VOLATILE_FLAG_*** options
+ * @vdqcr: bit mask of QM_VDQCR_*** options, as per qm_dqrr_vdqcr_set()
+ *
+ * Attempts to lock access to the portal's VDQCR volatile dequeue functionality.
+ * The function will block and sleep if QMAN_VOLATILE_FLAG_WAIT is specified and
+ * the VDQCR is already in use, otherwise returns non-zero for failure. If
+ * QMAN_VOLATILE_FLAG_FINISH is specified, the function will only return once
+ * the VDQCR command has finished executing (ie. once the callback for the last
+ * DQRR entry resulting from the VDQCR command has been called). If not using
+ * the FINISH flag, completion can be determined either by detecting the
+ * presence of the QM_DQRR_STAT_UNSCHEDULED and QM_DQRR_STAT_DQCR_EXPIRED bits
+ * in the "stat" parameter passed to the FQ's dequeue callback, or by waiting
+ * for the QMAN_FQ_STATE_VDQCR bit to disappear.
+ */
+int qman_volatile_dequeue(struct qman_fq *fq, u32 flags, u32 vdqcr);
+
 /**
  * qman_enqueue - Enqueue a frame to a frame queue
  * @fq: the frame queue object to enqueue to
Signature · 1 line
2.4.4
author maintainer
#2 lore raw

RFC 2/7 soc/qman: add dedicated channel ID for CAAM

In reply to Horia Geantă

Add and export the ID of the channel serviced by the CAAM (Cryptographic Acceleration and Assurance Module) DCP.

Signed-off-by Horia Geant? <[email protected]>
---
 drivers/soc/fsl/qbman/qman_ccsr.c | 6 +++++-
 include/soc/fsl/qman.h            | 3 +++
 2 files changed, 8 insertions(+), 1 deletion(-)
drivers/soc/fsl/qbman/qman_ccsr.c +5 -1
index f4e6e70de259..90bc40c48675 100644
@@ -34,6 +34,8 @@ u16 qman_ip_rev;
 EXPORT_SYMBOL(qman_ip_rev);
 u16 qm_channel_pool1 = QMAN_CHANNEL_POOL1;
 EXPORT_SYMBOL(qm_channel_pool1);
+u16 qm_channel_caam = QMAN_CHANNEL_CAAM;
+EXPORT_SYMBOL(qm_channel_caam);
 
 /* Register offsets */
 #define REG_QCSP_LIO_CFG(n)	(0x0000 + ((n) * 0x10))

@@ -720,8 +722,10 @@ static int fsl_qman_probe(struct platform_device *pdev)
 		return -ENODEV;
 	}
 
-	if ((qman_ip_rev & 0xff00) >= QMAN_REV30)
+	if ((qman_ip_rev & 0xff00) >= QMAN_REV30) {
 		qm_channel_pool1 = QMAN_CHANNEL_POOL1_REV3;
+		qm_channel_caam = QMAN_CHANNEL_CAAM_REV3;
+	}
 
 	ret = zero_priv_mem(dev, node, fqd_a, fqd_sz);
 	WARN_ON(ret);
include/soc/fsl/qman.h +3 -0
index 4de1ffcc8982..10b549783ec5 100644
@@ -36,8 +36,11 @@
 /* Hardware constants */
 #define QM_CHANNEL_SWPORTAL0 0
 #define QMAN_CHANNEL_POOL1 0x21
+#define QMAN_CHANNEL_CAAM 0x80
 #define QMAN_CHANNEL_POOL1_REV3 0x401
+#define QMAN_CHANNEL_CAAM_REV3 0x840
 extern u16 qm_channel_pool1;
+extern u16 qm_channel_caam;
 
 /* Portal processing (interrupt) sources */
 #define QM_PIRQ_CSCI	0x00100000	/* Congestion State Change */
Signature · 1 line
2.4.4
author maintainer
#3 lore raw

RFC 3/7 soc/qman: export non-programmable FQD fields query

In reply to Horia Geantă

Export qman_query_fq_np() function and related structures. This will be needed in the caam/qi driver, where "queue empty" condition will be decided based on the frm_cnt.

Signed-off-by Horia Geant? <[email protected]>
---
 drivers/soc/fsl/qbman/qman.c      |  4 +--
 drivers/soc/fsl/qbman/qman_priv.h | 61 -----------------------------------
 include/soc/fsl/qman.h            | 68 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 70 insertions(+), 63 deletions(-)
drivers/soc/fsl/qbman/qman.c +2 -2
index 6f509f68085e..3d891db57ee6 100644
@@ -2019,8 +2019,7 @@ int qman_query_fq(struct qman_fq *fq, struct qm_fqd *fqd)
 	return ret;
 }
 
-static int qman_query_fq_np(struct qman_fq *fq,
-			    struct qm_mcr_queryfq_np *np)
+int qman_query_fq_np(struct qman_fq *fq, struct qm_mcr_queryfq_np *np)
 {
 	union qm_mc_command *mcc;
 	union qm_mc_result *mcr;

@@ -2046,6 +2045,7 @@ static int qman_query_fq_np(struct qman_fq *fq,
 	put_affine_portal();
 	return ret;
 }
+EXPORT_SYMBOL(qman_query_fq_np);
 
 static int qman_query_cgr(struct qman_cgr *cgr,
 			  struct qm_mcr_querycgr *cgrd)
drivers/soc/fsl/qbman/qman_priv.h +0 -61

67 lines not on this page · raw message

include/soc/fsl/qman.h +68 -0

80 lines not on this page · raw message

Signature · 1 line
2.4.4
author maintainer
#4 lore raw

RFC 4/7 soc/qman: add helper functions needed by caam/qi driver

In reply to Horia Geantă

Add helper functions, macros, #defines for accessing / enabling qman functionality from caam/qi driver, such that this driver is not aware of the need for data conversion to big endian. qman is updated to use these helpers internally.

Signed-off-by Horia Geant? <[email protected]>
---
 drivers/soc/fsl/qbman/qman.c            | 16 +++++------
 drivers/soc/fsl/qbman/qman_test_stash.c |  5 ++--
 include/soc/fsl/qman.h                  | 47 +++++++++++++++++++++++++++++++++
 3 files changed, 56 insertions(+), 12 deletions(-)
drivers/soc/fsl/qbman/qman.c +7 -9
index 3d891db57ee6..7668ff53cd90 100644
@@ -1764,16 +1764,15 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
 	if (fq_isclear(fq, QMAN_FQ_FLAG_TO_DCPORTAL)) {
 		dma_addr_t phys_fq;
 
-		mcc->initfq.we_mask |= cpu_to_be16(QM_INITFQ_WE_CONTEXTB);
-		mcc->initfq.fqd.context_b = cpu_to_be32(fq_to_tag(fq));
+		qm_initfq_setbits(&mcc->initfq, QM_INITFQ_WE_CONTEXTB);
+		qm_fqd_set_contextb(&mcc->initfq.fqd, fq_to_tag(fq));
 		/*
 		 *  and the physical address - NB, if the user wasn't trying to
 		 * set CONTEXTA, clear the stashing settings.
 		 */
 		if (!(be16_to_cpu(mcc->initfq.we_mask) &
 				  QM_INITFQ_WE_CONTEXTA)) {
-			mcc->initfq.we_mask |=
-				cpu_to_be16(QM_INITFQ_WE_CONTEXTA);
+			qm_initfq_setbits(&mcc->initfq, QM_INITFQ_WE_CONTEXTA);
 			memset(&mcc->initfq.fqd.context_a, 0,
 				sizeof(mcc->initfq.fqd.context_a));
 		} else {

@@ -1795,8 +1794,7 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
 
 		if (!(be16_to_cpu(mcc->initfq.we_mask) &
 				  QM_INITFQ_WE_DESTWQ)) {
-			mcc->initfq.we_mask |=
-				cpu_to_be16(QM_INITFQ_WE_DESTWQ);
+			qm_initfq_setbits(&mcc->initfq, QM_INITFQ_WE_DESTWQ);
 			wq = 4;
 		}
 		qm_fqd_set_destwq(&mcc->initfq.fqd, p->config->channel, wq);

@@ -1816,7 +1814,7 @@ int qman_init_fq(struct qman_fq *fq, u32 flags, struct qm_mcc_initfq *opts)
 	}
 	if (opts) {
 		if (be16_to_cpu(opts->we_mask) & QM_INITFQ_WE_FQCTRL) {
-			if (be16_to_cpu(opts->fqd.fq_ctrl) & QM_FQCTRL_CGE)
+			if (qm_fqd_isset_fqctrl(&opts->fqd, QM_FQCTRL_CGE))
 				fq_set(fq, QMAN_FQ_STATE_CGR_EN);
 			else
 				fq_clear(fq, QMAN_FQ_STATE_CGR_EN);

@@ -2321,7 +2319,7 @@ int qman_create_cgr(struct qman_cgr *cgr, u32 flags,
 
 		qm_cgr_cscn_targ_set(&local_opts.cgr, PORTAL_IDX(p),
 				     be32_to_cpu(cgr_state.cgr.cscn_targ));
-		local_opts.we_mask |= cpu_to_be16(QM_CGR_WE_CSCN_TARG);
+		qm_initcgr_setbits(&local_opts, QM_CGR_WE_CSCN_TARG);
 
 		/* send init if flags indicate so */
 		if (flags & QMAN_CGR_FLAG_USE_INIT)

@@ -2840,7 +2838,7 @@ static int cgr_cleanup(u32 cgrid)
 			err = qman_query_fq(&fq, &fqd);
 			if (WARN_ON(err))
 				return err;
-			if (be16_to_cpu(fqd.fq_ctrl) & QM_FQCTRL_CGE &&
+			if (qm_fqd_isset_fqctrl(&fqd, QM_FQCTRL_CGE) &&
 			    fqd.cgid == cgrid) {
 				pr_err("CRGID 0x%x is being used by FQID 0x%x, CGR will be leaked\n",
 				       cgrid, fq.fqid);
drivers/soc/fsl/qbman/qman_test_stash.c +2 -3
index e87b65403b67..d2bf453092d7 100644
@@ -406,9 +406,8 @@ static int init_handler(void *h)
 		goto failed;
 	}
 	memset(&opts, 0, sizeof(opts));
-	opts.we_mask = cpu_to_be16(QM_INITFQ_WE_FQCTRL |
-				   QM_INITFQ_WE_CONTEXTA);
-	opts.fqd.fq_ctrl = cpu_to_be16(QM_FQCTRL_CTXASTASHING);
+	qm_initfq_setbits(&opts, QM_INITFQ_WE_FQCTRL | QM_INITFQ_WE_CONTEXTA);
+	qm_fqd_set_fqctrl(&opts.fqd, QM_FQCTRL_CTXASTASHING);
 	qm_fqd_set_stashing(&opts.fqd, 0, STASH_DATA_CL, STASH_CTX_CL);
 	err = qman_init_fq(&handler->rx, QMAN_INITFQ_FLAG_SCHED |
 			   QMAN_INITFQ_FLAG_LOCAL, &opts);
include/soc/fsl/qman.h +47 -0

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Signature · 1 line
2.4.4
#5 lore raw

RFC 4/7 soc/qman: add helper functions needed by caam/qi driver

Quoted 3 lines · Horia Geant?

Add helper functions, macros, #defines for accessing / enabling qman functionality from caam/qi driver, such that this driver is not aware of the need for data conversion to big endian.

Why? ?I complained about that (probably internally) when this driver was originally submitted.

Having a bunch of accessors in a header file that just do an assignment with an endian conversion just obfuscates things. ?The driver still needs to know that the conversion needs to happen, or else it wouldn't know that the fields can't be accessed directly... and it gets particularly ridiculous when a single field has a growing pile of accessors depending on exactly what flags you want to set (e.g. qm_sg_entry_set_*). ?Just open-code it unless an accessor is justified by the call sites getting unwieldy or numerous.

It looks like GCC 6 has added an attribute (scalar_storage_order) that could be used on structs to avoid having to manually swap such things. ?I look forward to the day when GCC 6 is old enough for the kernel to depend on this.

-Scott

author maintainer
#6 lore raw

RFC 5/7 crypto: caam - avoid double inclusion in desc_constr.h

In reply to Horia Geantă
Signed-off-by Horia Geant? <[email protected]>
---
 drivers/crypto/caam/desc_constr.h | 5 +++++
 1 file changed, 5 insertions(+)
drivers/crypto/caam/desc_constr.h +5 -0
index b9c8d98ef826..d8e83ca104e0 100644
@@ -4,6 +4,9 @@
  * Copyright 2008-2012 Freescale Semiconductor, Inc.
  */
 
+#ifndef DESC_CONSTR_H
+#define DESC_CONSTR_H
+
 #include "desc.h"
 #include "regs.h"
 

@@ -491,3 +494,5 @@ static inline int desc_inline_query(unsigned int sd_base_len,
 
 	return (rem_bytes >= 0) ? 0 : -1;
 }
+
+#endif /* DESC_CONSTR_H */
Signature · 1 line
2.4.4
author maintainer
#7 lore raw

RFC 6/7 crypto: caam - add Queue Interface (QI) backend support

In reply to Horia Geantă

CAAM engine supports two interfaces for crypto job submission:
-job ring interface - already existing caam/jr driver -Queue Interface (QI) - caam/qi driver added in current patch

QI is present in CAAM engines found on DPAA platforms.
QI gets its I/O (frame descriptors) from QMan (Queue Manager) queues.

This patch adds a platform device for accessing CAAM's queue interface. The requests are submitted to CAAM using one frame queue per cryptographic context. Each crypto context has one shared descriptor. This shared descriptor is attached to frame queue associated with corresponding driver context using context_a.

The driver hides the mechanics of FQ creation, initialisation from its applications. Each cryptographic context needs to be associated with driver context which houses the FQ to be used to transport the job to CAAM. The driver provides API for:
(a) Context creation
(b) Job submission
(c) Context deletion
(d) Congestion indication - whether path to/from CAAM is congested

The driver supports affining its context to a particular CPU. This means that any responses from CAAM for the context in question would arrive at the given CPU. This helps in implementing one CPU per packet round trip in IPsec application.

The driver processes CAAM responses under NAPI contexts. NAPI contexts are instantiated only on cores with affined portals since only cores having their own portal can receive responses from DQRR.

The responses from CAAM for all cryptographic contexts ride on a fixed set of FQs. We use one response FQ per portal owning core. The response FQ is configured in each core's and thus portal's dedicated channel. This gives the flexibility to direct CAAM's responses for a crypto context on a given core.

Signed-off-by Vakul Garg <[email protected]>
Signed-off-by Alex Porosanu <[email protected]>
Signed-off-by Horia Geant? <[email protected]>
---
 drivers/crypto/caam/Makefile |   4 +
 drivers/crypto/caam/ctrl.c   |  58 ++--
 drivers/crypto/caam/intern.h |  24 ++
 drivers/crypto/caam/qi.c     | 805 +++++++++++++++++++++++++++++++++++++++++++
 drivers/crypto/caam/qi.h     | 201 +++++++++++
 5 files changed, 1064 insertions(+), 28 deletions(-)
 create mode 100644 drivers/crypto/caam/qi.c
 create mode 100644 drivers/crypto/caam/qi.h
drivers/crypto/caam/Makefile +4 -0
index 6554742f357e..2e60e45c2bf1 100644
@@ -16,3 +16,7 @@ obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_PKC_API) += caam_pkc.o
 caam-objs := ctrl.o
 caam_jr-objs := jr.o key_gen.o error.o
 caam_pkc-y := caampkc.o pkc_desc.o
+ifneq ($(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI),)
+	ccflags-y += -DCONFIG_CAAM_QI
+	caam-objs += qi.o
+endif
drivers/crypto/caam/ctrl.c +30 -28

100 lines not on this page · raw message

drivers/crypto/caam/intern.h +24 -0
index e2bcacc1a921..c334df638ff6 100644
@@ -67,6 +67,9 @@ struct caam_drv_private {
 
 	struct device *dev;
 	struct platform_device **jrpdev; /* Alloc'ed array per sub-device */
+#ifdef CONFIG_CAAM_QI
+	struct device *qidev;
+#endif
 	struct platform_device *pdev;
 
 	/* Physical-presence section */

@@ -110,9 +113,30 @@ struct caam_drv_private {
 
 	struct debugfs_blob_wrapper ctl_kek_wrap, ctl_tkek_wrap, ctl_tdsk_wrap;
 	struct dentry *ctl_kek, *ctl_tkek, *ctl_tdsk;
+#ifdef CONFIG_CAAM_QI
+	struct dentry *qi_congested;
+#endif
 #endif
 };
 
 void caam_jr_algapi_init(struct device *dev);
 void caam_jr_algapi_remove(struct device *dev);
+
+#ifdef CONFIG_DEBUG_FS
+static int caam_debugfs_u64_get(void *data, u64 *val)
+{
+	*val = caam64_to_cpu(*(u64 *)data);
+	return 0;
+}
+
+static int caam_debugfs_u32_get(void *data, u64 *val)
+{
+	*val = caam32_to_cpu(*(u32 *)data);
+	return 0;
+}
+
+DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u32_ro, caam_debugfs_u32_get, NULL, "%llu\n");
+DEFINE_SIMPLE_ATTRIBUTE(caam_fops_u64_ro, caam_debugfs_u64_get, NULL, "%llu\n");
+#endif
+
 #endif /* INTERN_H */
drivers/crypto/caam/qi.c new file +805 -0

805 lines not on this page · raw message

drivers/crypto/caam/qi.h new file +201 -0

201 lines not on this page · raw message

Signature · 1 line
2.4.4
author maintainer
#8 lore raw

RFC 7/7 crypto: caam/qi - add ablkcipher and authenc algorithms

In reply to Horia Geantă

Add support to submit ablkcipher and authenc algorithms via the QI backend:
-ablkcipher:
cbc({aes,des,des3_ede})
ctr(aes), rfc3686(ctr(aes))
xts(aes)
-authenc:
authenc(hmac(md5),cbc({aes,des,des3_ede})) authenc(hmac(sha*),cbc({aes,des,des3_ede}))

caam/qi being a new driver, let's wait some time to settle down without interfering with existing caam/jr driver.
Accordingly, for now all caam/qi algorithms (caamalg_qi module) are marked to be of lower priority than caam/jr ones (caamalg module).

Signed-off-by Vakul Garg <[email protected]>
Signed-off-by Alex Porosanu <[email protected]>
Signed-off-by Horia Geant? <[email protected]>
---
 drivers/crypto/caam/Kconfig        |   20 +-
 drivers/crypto/caam/Makefile       |    1 +
 drivers/crypto/caam/caamalg.c      |    9 +-
 drivers/crypto/caam/caamalg_desc.c |   77 +-
 drivers/crypto/caam/caamalg_desc.h |   15 +-
 drivers/crypto/caam/caamalg_qi.c   | 2387 ++++++++++++++++++++++++++++++++++++
 drivers/crypto/caam/sg_sw_qm.h     |  107 ++
 7 files changed, 2600 insertions(+), 16 deletions(-)
 create mode 100644 drivers/crypto/caam/caamalg_qi.c
 create mode 100644 drivers/crypto/caam/sg_sw_qm.h
drivers/crypto/caam/Kconfig +19 -1
index bc0d3569f8d9..e36aeacd7635 100644
@@ -87,6 +87,23 @@ config CRYPTO_DEV_FSL_CAAM_CRYPTO_API
 	  To compile this as a module, choose M here: the module
 	  will be called caamalg.
 
+config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI
+	tristate "Queue Interface as Crypto API backend"
+	depends on CRYPTO_DEV_FSL_CAAM_JR && FSL_DPAA && NET
+	default y
+	select CRYPTO_AUTHENC
+	select CRYPTO_BLKCIPHER
+	help
+	  Selecting this will use CAAM Queue Interface (QI) for sending
+	  & receiving crypto jobs to/from CAAM. This gives better performance
+	  than job ring interface when the number of cores are more than the
+	  number of job rings assigned to the kernel. The number of portals
+	  assigned to the kernel should also be more than the number of
+	  job rings.
+
+	  To compile this as a module, choose M here: the module
+	  will be called caamalg_qi.
+
 config CRYPTO_DEV_FSL_CAAM_AHASH_API
 	tristate "Register hash algorithm implementations with Crypto API"
 	depends on CRYPTO_DEV_FSL_CAAM_JR

@@ -136,4 +153,5 @@ config CRYPTO_DEV_FSL_CAAM_DEBUG
 	  information in the CAAM driver.
 
 config CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC
-	def_tristate CRYPTO_DEV_FSL_CAAM_CRYPTO_API
+	def_tristate (CRYPTO_DEV_FSL_CAAM_CRYPTO_API || \
+		      CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI)
drivers/crypto/caam/Makefile +1 -0
index 2e60e45c2bf1..9e2e98856b9b 100644
@@ -8,6 +8,7 @@ endif
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM) += caam.o
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_JR) += caam_jr.o
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API) += caamalg.o
+obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_QI) += caamalg_qi.o
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_CRYPTO_API_DESC) += caamalg_desc.o
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_AHASH_API) += caamhash.o
 obj-$(CONFIG_CRYPTO_DEV_FSL_CAAM_RNG_API) += caamrng.o
drivers/crypto/caam/caamalg.c +5 -4
index 9bc80eb06934..398807d1b77e 100644
@@ -266,8 +266,9 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
 
 	/* aead_encrypt shared descriptor */
 	desc = ctx->sh_desc_enc;
-	cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ctx->authsize,
-			       is_rfc3686, nonce, ctx1_iv_off);
+	cnstr_shdsc_aead_encap(desc, &ctx->cdata, &ctx->adata, ivsize,
+			       ctx->authsize, is_rfc3686, nonce, ctx1_iv_off,
+			       false);
 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
 				   desc_bytes(desc), DMA_TO_DEVICE);
 

@@ -299,7 +300,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
 	desc = ctx->sh_desc_dec;
 	cnstr_shdsc_aead_decap(desc, &ctx->cdata, &ctx->adata, ivsize,
 			       ctx->authsize, alg->caam.geniv, is_rfc3686,
-			       nonce, ctx1_iv_off);
+			       nonce, ctx1_iv_off, false);
 	dma_sync_single_for_device(jrdev, ctx->sh_desc_dec_dma,
 				   desc_bytes(desc), DMA_TO_DEVICE);
 

@@ -333,7 +334,7 @@ static int aead_set_sh_desc(struct crypto_aead *aead)
 	desc = ctx->sh_desc_enc;
 	cnstr_shdsc_aead_givencap(desc, &ctx->cdata, &ctx->adata, ivsize,
 				  ctx->authsize, is_rfc3686, nonce,
-				  ctx1_iv_off);
+				  ctx1_iv_off, false);
 	dma_sync_single_for_device(jrdev, ctx->sh_desc_enc_dma,
 				   desc_bytes(desc), DMA_TO_DEVICE);
drivers/crypto/caam/caamalg_desc.c +71 -6

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drivers/crypto/caam/caamalg_desc.h +10 -5
index 95551737333a..8731e4a7ff05 100644
@@ -12,6 +12,9 @@
 #define DESC_AEAD_ENC_LEN		(DESC_AEAD_BASE + 11 * CAAM_CMD_SZ)
 #define DESC_AEAD_DEC_LEN		(DESC_AEAD_BASE + 15 * CAAM_CMD_SZ)
 #define DESC_AEAD_GIVENC_LEN		(DESC_AEAD_ENC_LEN + 7 * CAAM_CMD_SZ)
+#define DESC_QI_AEAD_ENC_LEN		(DESC_AEAD_ENC_LEN + 3 * CAAM_CMD_SZ)
+#define DESC_QI_AEAD_DEC_LEN		(DESC_AEAD_DEC_LEN + 3 * CAAM_CMD_SZ)
+#define DESC_QI_AEAD_GIVENC_LEN		(DESC_AEAD_GIVENC_LEN + 3 * CAAM_CMD_SZ)
 
 /* Note: Nonce is counted in cdata.keylen */
 #define DESC_AEAD_CTR_RFC3686_LEN	(4 * CAAM_CMD_SZ)

@@ -45,20 +48,22 @@ void cnstr_shdsc_aead_null_decap(u32 * const desc, struct alginfo *adata,
 				 unsigned int icvsize);
 
 void cnstr_shdsc_aead_encap(u32 * const desc, struct alginfo *cdata,
-			    struct alginfo *adata, unsigned int icvsize,
-			    const bool is_rfc3686, u32 *nonce,
-			    const u32 ctx1_iv_off);
+			    struct alginfo *adata, unsigned int ivsize,
+			    unsigned int icvsize, const bool is_rfc3686,
+			    u32 *nonce, const u32 ctx1_iv_off,
+			    const bool is_qi);
 
 void cnstr_shdsc_aead_decap(u32 * const desc, struct alginfo *cdata,
 			    struct alginfo *adata, unsigned int ivsize,
 			    unsigned int icvsize, const bool geniv,
 			    const bool is_rfc3686, u32 *nonce,
-			    const u32 ctx1_iv_off);
+			    const u32 ctx1_iv_off, const bool is_qi);
 
 void cnstr_shdsc_aead_givencap(u32 * const desc, struct alginfo *cdata,
 			       struct alginfo *adata, unsigned int ivsize,
 			       unsigned int icvsize, const bool is_rfc3686,
-			       u32 *nonce, const u32 ctx1_iv_off);
+			       u32 *nonce, const u32 ctx1_iv_off,
+			       const bool is_qi);
 
 void cnstr_shdsc_gcm_encap(u32 * const desc, struct alginfo *cdata,
 			   unsigned int icvsize);
drivers/crypto/caam/caamalg_qi.c new file +2387 -0

2,387 lines not on this page · raw message

drivers/crypto/caam/sg_sw_qm.h new file +107 -0

107 lines not on this page · raw message

Signature · 1 line
2.4.4
maintainer
#9 lore raw

cover crypto: caam - add Queue Interface (QI) support

In reply to Horia Geantă
Quoted 8 lines · Horia Geant?

The patchset adds support for CAAM Queue Interface (QI), the additional interface (besides job ring) available for submitting jobs to the engine on platforms having DPAA (Datapath Acceleration Architecture).

Patches 1-4 are QMan dependencies.
I would prefer to take them through the crypto tree, but I am open to suggestions.

Quoted 6 lines

Patch 5 adds a missing double inclusion guard in desc_constr.h.

Patch 6 adds the caam/qi job submission backend.

Patch 7 adds algorithms (ablkcipher and authenc) that run on top of caam/qi. For now, their priority is set lower than caam/jr.

I'm fine with the crypto bits.

Cheers,

Signature · 3 lines
Email: Herbert Xu <[email protected]>
Home Page: http://gondor.apana.org.au/~herbert/
PGP Key: http://gondor.apana.org.au/~herbert/pubkey.txt
author maintainer
#10 lore raw

cover crypto: caam - add Queue Interface (QI) support

Quoted 9 lines · Herbert Xu
Quoted 8 lines · Horia Geant?

The patchset adds support for CAAM Queue Interface (QI), the additional interface (besides job ring) available for submitting jobs to the engine on platforms having DPAA (Datapath Acceleration Architecture).

Patches 1-4 are QMan dependencies.
I would prefer to take them through the crypto tree, but I am open to suggestions.

Quoted 9 lines
Quoted 6 lines

Patch 5 adds a missing double inclusion guard in desc_constr.h.

Patch 6 adds the caam/qi job submission backend.

Patch 7 adds algorithms (ablkcipher and authenc) that run on top of caam/qi. For now, their priority is set lower than caam/jr.

I'm fine with the crypto bits.

Herbert,

Thanks for the review.
Should I submit formally, i.e. without the [RFC] prefix?

Scott, Roy,

Do you have any comments wrt. soc/qman patches or with them going through the crypto tree?

Thanks,
Horia

#11 lore raw

cover crypto: caam - add Queue Interface (QI) support

Quoted 22 lines · Horia Geant?
Quoted 11 lines · Herbert Xu
Quoted 9 lines · Horia Geant?

The patchset adds support for CAAM Queue Interface (QI), the additional interface (besides job ring) available for submitting jobs to the engine on platforms having DPAA (Datapath Acceleration Architecture).

Patches 1-4 are QMan dependencies.
I would prefer to take them through the crypto tree, but I am open to suggestions.

Quoted 8 lines
Quoted 6 lines

Patch 5 adds a missing double inclusion guard in desc_constr.h.

Patch 6 adds the caam/qi job submission backend.

Patch 7 adds algorithms (ablkcipher and authenc) that run on top of caam/qi. For now, their priority is set lower than caam/jr.

I'm fine with the crypto bits.

Herbert,

Quoted 7 lines

Thanks for the review.
Should I submit formally, i.e. without the [RFC] prefix?

Scott, Roy,

Do you have any comments wrt. soc/qman patches or with them going through the crypto tree?

Going through the crypto tree is fine.

-Scott