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measure SMI cost

PATCH Superseded [email protected] 6 participants 19 messages Mar 23, 2017 – Apr 1, 2017

Subsystems (2)
x86 perf events

v1 of 7 Superseded Latest is v7 →

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#0 lore raw

cover measure SMI cost

From: Kan Liang <[email protected]>

Currently, there is no way to measure the time cost in System management mode (SMM) by perf.

Intel perfmon supports FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. Once it sets, the PMU core counters will freeze on SMI handler. But it will not have an effect on free running counters. E.g. APERF counter.
The cost of SMI can be measured by (aperf - cycles).

A new sysfs entry /sys/device/cpu/freeze_on_smi is introduced to set FREEZE_WHILE_SMM bit in IA32_DEBUGCTL.

A new --smi-cost mode in perf stat is implemented to measure the SMI cost by calculating cycles and aperf results. In practice, the percentages of SMI cycles should be more useful than absolute value. So the output will be the percentage of SMI cycles and SMI#.

Here is an example output.

Performance counter stats for 'sudo echo ':

SMI cycles% SMI#

    0.1%              1

       0.010858678 seconds time elapsed

Kan Liang (3):
perf/x86: add sysfs entry to freeze counter on SMI tools lib api fs: Add sysfs__write_int function perf stat: Add support to measure SMI cost

 arch/x86/events/core.c                 | 10 +++++++
 arch/x86/events/intel/core.c           | 48 ++++++++++++++++++++++++++++++++++
 arch/x86/events/perf_event.h           |  3 +++
 arch/x86/include/asm/msr-index.h       |  1 +
 tools/lib/api/fs/fs.c                  | 29 ++++++++++++++++++++
 tools/lib/api/fs/fs.h                  |  4 +++
 tools/perf/Documentation/perf-stat.txt |  9 +++++++
 tools/perf/builtin-stat.c              | 48 ++++++++++++++++++++++++++++++++++
 tools/perf/util/stat-shadow.c          | 33 +++++++++++++++++++++++
 tools/perf/util/stat.c                 |  2 ++
 tools/perf/util/stat.h                 |  2 ++
 11 files changed, 189 insertions(+)
Signature · 1 line
2.7.4
author
#1 lore raw

PATCH 1/3 perf/x86: add sysfs entry to freeze counter on SMI

From: Kan Liang <[email protected]>

When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance counters will be effected. There is no way to do per-counter freeze on smi. So it should not use the per-event interface (e.g. ioctl or event attribute) to set FREEZE_WHILE_SMM bit.

Adds sysfs entry /sys/device/cpu/freeze_on_smi to set FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages while in SMM.
Value has to be 0 or 1. It will be applied to all possible cpus.

Signed-off-by Kan Liang <[email protected]>
---
 arch/x86/events/core.c           | 10 +++++++++
 arch/x86/events/intel/core.c     | 48 ++++++++++++++++++++++++++++++++++++++++
 arch/x86/events/perf_event.h     |  3 +++
 arch/x86/include/asm/msr-index.h |  1 +
 4 files changed, 62 insertions(+)
arch/x86/events/core.c +10 -0
index 349d4d1..c16fb50 100644
@@ -1750,6 +1750,8 @@ ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event)
 	return ret;
 }
 
+static struct attribute_group x86_pmu_attr_group;
+
 static int __init init_hw_perf_events(void)
 {
 	struct x86_pmu_quirk *quirk;

@@ -1813,6 +1815,14 @@ static int __init init_hw_perf_events(void)
 			x86_pmu_events_group.attrs = tmp;
 	}
 
+	if (x86_pmu.attrs) {
+		struct attribute **tmp;
+
+		tmp = merge_attr(x86_pmu_attr_group.attrs, x86_pmu.attrs);
+		if (!WARN_ON(!tmp))
+			x86_pmu_attr_group.attrs = tmp;
+	}
+
 	pr_info("... version:                %d\n",     x86_pmu.version);
 	pr_info("... bit width:              %d\n",     x86_pmu.cntval_bits);
 	pr_info("... generic registers:      %d\n",     x86_pmu.num_counters);
arch/x86/events/intel/core.c +48 -0

60 lines not on this page · raw message

arch/x86/events/perf_event.h +3 -0
index bcbb1d2..110cb9b0 100644
@@ -561,6 +561,9 @@ struct x86_pmu {
 	ssize_t		(*events_sysfs_show)(char *page, u64 config);
 	struct attribute **cpu_events;
 
+	int		attr_freeze_on_smi;
+	struct attribute **attrs;
+
 	/*
 	 * CPU Hotplug hooks
 	 */
arch/x86/include/asm/msr-index.h +1 -0
index d8b5f8a..26c861f 100644
@@ -134,6 +134,7 @@
 #define DEBUGCTLMSR_BTS_OFF_OS		(1UL <<  9)
 #define DEBUGCTLMSR_BTS_OFF_USR		(1UL << 10)
 #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI	(1UL << 11)
+#define DEBUGCTLMSR_FREEZE_WHILE_SMM	(1UL << 14)
 
 #define MSR_PEBS_FRONTEND		0x000003f7
Signature · 1 line
2.7.4
maintainer
#2 lore raw

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

Quoted 11 lines · On Thu, Mar 23, 2017 at 11:25:49AM -0700, [email protected] wrote:

From: Kan Liang <[email protected]>

When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance counters will be effected. There is no way to do per-counter freeze on smi. So it should not use the per-event interface (e.g. ioctl or event attribute) to set FREEZE_WHILE_SMM bit.

Adds sysfs entry /sys/device/cpu/freeze_on_smi to set FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages while in SMM.
Value has to be 0 or 1. It will be applied to all possible cpus.

So is there ever a good reason to not set this?

author
#3 lore raw

RE: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

Quoted 9 lines · On Thu, Mar 23, 2017 at 11:25:49AM -0700, [email protected] wrote:
Quoted 3 lines

From: Kan Liang <[email protected]>

When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all

performance

Quoted 4 lines

counters will be effected. There is no way to do per-counter freeze on smi. So it should not use the per-event interface (e.g. ioctl or event attribute) to set FREEZE_WHILE_SMM bit.

Quoted 7 lines
Quoted 1 line

Adds sysfs entry /sys/device/cpu/freeze_on_smi to set

FREEZE_WHILE_SMM

Quoted 3 lines

bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages while in SMM.
Value has to be 0 or 1. It will be applied to all possible cpus.

So is there ever a good reason to not set this?

For me, I don't see any drawbacks to set it unconditionally. But I'm not sure if there is someone else who may want the counter running in SMI.

If there is no objection, I will set the FREEZE_WHILE_SMM bit unconditionally in next version.

Thanks,
Kan

#4 lore raw

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

In reply to Peter Zijlstra
Quoted 8 lines · Peter Zijlstra
Quoted 7 lines · On Thu, Mar 23, 2017 at 11:25:49AM -0700, [email protected] wrote:

From: Kan Liang <[email protected]>

When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance counters will be effected. There is no way to do per-counter freeze on smi. So it should not use the per-event interface (e.g. ioctl or event attribute) to set FREEZE_WHILE_SMM bit.

Quoted 6 lines
Quoted 4 lines

Adds sysfs entry /sys/device/cpu/freeze_on_smi to set FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages while in SMM.
Value has to be 0 or 1. It will be applied to all possible cpus.

So is there ever a good reason to not set this?

That means SMIs become invisible to most performance counters.

I don't think that's a good default. If the SMI takes 1% of my cycles I want to see it.

The masking trick is mainly useful when doing --smi-cost

-Andi

maintainer
#5 lore raw

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

Quoted 14 lines · Andi Kleen
Quoted 13 lines · Peter Zijlstra
Quoted 11 lines · On Thu, Mar 23, 2017 at 11:25:49AM -0700, [email protected] wrote:

From: Kan Liang <[email protected]>

When setting FREEZE_WHILE_SMM bit in IA32_DEBUGCTL, all performance counters will be effected. There is no way to do per-counter freeze on smi. So it should not use the per-event interface (e.g. ioctl or event attribute) to set FREEZE_WHILE_SMM bit.

Adds sysfs entry /sys/device/cpu/freeze_on_smi to set FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. When set, freezes perfmon and trace messages while in SMM.
Value has to be 0 or 1. It will be applied to all possible cpus.

Quoted 8 lines
Quoted 1 line

So is there ever a good reason to not set this?

That means SMIs become invisible to most performance counters.

I don't think that's a good default. If the SMI takes 1% of my cycles I want to see it.

The masking trick is mainly useful when doing --smi-cost

Changelog should spell this out though. It adds a knob, so it should say why it needs be a knob.

maintainer
#6 lore raw

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

In reply to [email protected]

arch/x86/events/intel/core.c static struct attribute *hsw_events_attrs[] = { · line 3630

Quoted 7 lines · On Thu, Mar 23, 2017 at 11:25:49AM -0700, [email protected] wrote:
arch/x86/events/intel/core.c +7 -0
+	for_each_possible_cpu(cpu) {
+		rdmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, &debugctlmsr);
+		if (val)
+			wrmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, debugctlmsr | DEBUGCTLMSR_FREEZE_WHILE_SMM);
+		else
+			wrmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, debugctlmsr & ~DEBUGCTLMSR_FREEZE_WHILE_SMM);
+	}

No; that's just disgusting. Also {rd,wr}msr_on_cpu() should die, exactly because people end up writing crap like this.

#7 lore raw

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

Quoted 11 lines · Peter Zijlstra

arch/x86/events/intel/core.c static struct attribute *hsw_events_attrs[] = { · line 3630

Quoted 7 lines · On Thu, Mar 23, 2017 at 11:25:49AM -0700, [email protected] wrote:
arch/x86/events/intel/core.c +7 -0
+	for_each_possible_cpu(cpu) {
+		rdmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, &debugctlmsr);
+		if (val)
+			wrmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, debugctlmsr | DEBUGCTLMSR_FREEZE_WHILE_SMM);
+		else
+			wrmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR, debugctlmsr & ~DEBUGCTLMSR_FREEZE_WHILE_SMM);
+	}

No; that's just disgusting. Also {rd,wr}msr_on_cpu() should die, exactly because people end up writing crap like this.

Aside of that this is completely broken against other users of DEBUGCTLMSR because it's not atomic vs. the other modifications.

Thanks,

tglx

author
#8 lore raw

RE: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

Quoted 13 lines · Peter Zijlstra
Quoted 3 lines · On Thu, Mar 23, 2017 at 11:25:49AM -0700, [email protected] wrote:

Review

Quoted 2 lines
(quoted diff) +2 -0
+	for_each_possible_cpu(cpu) {
+		rdmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR,

&debugctlmsr);

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+		if (val)
+			wrmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR,

debugctlmsr | DEBUGCTLMSR_FREEZE_WHILE_SMM);

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+		else
+			wrmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR,

debugctlmsr & ~DEBUGCTLMSR_FREEZE_WHILE_SMM);

Quoted 8 lines
Quoted 4 lines

Review

Quoted 1 line
(quoted diff) +1 -0
+	}

No; that's just disgusting. Also {rd,wr}msr_on_cpu() should die, exactly because people end up writing crap like this.

Aside of that this is completely broken against other users of DEBUGCTLMSR because it's not atomic vs. the other modifications.

OK. I will change it.
I guess I need a way/function which can atomically rd,wr msr on all cpus. Are there existing alternative ways/functions to do that?

Thanks,
Kan

maintainer
#9 lore raw

Re: [PATCH 1/3] perf/x86: add sysfs entry to freeze counter on SMI

Quoted 18 lines · Kan
Quoted 18 lines · Peter Zijlstra
Quoted 3 lines · On Thu, Mar 23, 2017 at 11:25:49AM -0700, [email protected] wrote:

Review

Quoted 2 lines
(quoted diff) +2 -0
+	for_each_possible_cpu(cpu) {
+		rdmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR,

&debugctlmsr);

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+		if (val)
+			wrmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR,

debugctlmsr | DEBUGCTLMSR_FREEZE_WHILE_SMM);

Quoted 2 lines

Review

Quoted 2 lines
(quoted diff) +2 -0
+		else
+			wrmsrl_on_cpu(cpu, MSR_IA32_DEBUGCTLMSR,

debugctlmsr & ~DEBUGCTLMSR_FREEZE_WHILE_SMM);

Quoted 4 lines

Review

Quoted 1 line
(quoted diff) +1 -0
+	}

No; that's just disgusting. Also {rd,wr}msr_on_cpu() should die, exactly because people end up writing crap like this.

Quoted 7 lines
Quoted 3 lines

Aside of that this is completely broken against other users of DEBUGCTLMSR because it's not atomic vs. the other modifications.

OK. I will change it.
I guess I need a way/function which can atomically rd,wr msr on all cpus. Are there existing alternative ways/functions to do that?

No; also don't forget hotplug.

author
#10 lore raw

PATCH 2/3 tools lib api fs: Add sysfs__write_int function

In reply to [email protected]

From: Kan Liang <[email protected]>

Adding sysfs__write_int function to ease up writing int to sysfs. New interface is:

  int sysfs__write_int(const char *entry, int value);

Also, introducing filename__write_int which is useful for new helpers to write sysctl values.

Signed-off-by Kan Liang <[email protected]>
---
 tools/lib/api/fs/fs.c | 29 +++++++++++++++++++++++++++++
 tools/lib/api/fs/fs.h |  4 ++++
 2 files changed, 33 insertions(+)
tools/lib/api/fs/fs.c +29 -0
index 809c772..de4f74e 100644
@@ -387,6 +387,22 @@ int filename__read_str(const char *filename, char **buf, size_t *sizep)
 	return err;
 }
 
+int filename__write_int(const char *filename, int value)
+{
+	int fd = open(filename, O_WRONLY), err = -1;
+	char buf[64];
+
+	if (fd < 0)
+		return err;
+
+	sprintf(buf, "%d", value);
+	if (write(fd, buf, sizeof(buf)) == sizeof(buf))
+		err = 0;
+
+	close(fd);
+	return err;
+}
+
 int procfs__read_str(const char *entry, char **buf, size_t *sizep)
 {
 	char path[PATH_MAX];

@@ -480,3 +496,16 @@ int sysctl__read_int(const char *sysctl, int *value)
 
 	return filename__read_int(path, value);
 }
+
+int sysfs__write_int(const char *entry, int value)
+{
+	char path[PATH_MAX];
+	const char *sysfs = sysfs__mountpoint();
+
+	if (!sysfs)
+		return -1;
+
+	snprintf(path, sizeof(path), "%s/%s", sysfs, entry);
+
+	return filename__write_int(path, value);
+}
tools/lib/api/fs/fs.h +4 -0
index 956c211..4560534 100644
@@ -31,6 +31,8 @@ int filename__read_int(const char *filename, int *value);
 int filename__read_ull(const char *filename, unsigned long long *value);
 int filename__read_str(const char *filename, char **buf, size_t *sizep);
 
+int filename__write_int(const char *filename, int value);
+
 int procfs__read_str(const char *entry, char **buf, size_t *sizep);
 
 int sysctl__read_int(const char *sysctl, int *value);

@@ -38,4 +40,6 @@ int sysfs__read_int(const char *entry, int *value);
 int sysfs__read_ull(const char *entry, unsigned long long *value);
 int sysfs__read_str(const char *entry, char **buf, size_t *sizep);
 int sysfs__read_bool(const char *entry, bool *value);
+
+int sysfs__write_int(const char *entry, int value);
 #endif /* __API_FS__ */
Signature · 1 line
2.7.4
#11 lore raw

RE: [PATCH 2/3] tools lib api fs: Add sysfs__write_int function

Quoted 7 lines

-----Original Message-----
From: [email protected] [mailto:linux-kernel- [email protected]] On Behalf Of [email protected]
Sent: Thursday, March 23, 2017 1:26 PM
Subject: [PATCH 2/3] tools lib api fs: Add sysfs__write_int function

...

Quoted 1 line
tools/lib/api/fs/fs.c +0 -0

...

tools/lib/api/fs/fs.c int sysctl__read_int(const char *sysctl, int *value) · line 510

Quoted 12 lines
tools/lib/api/fs/fs.c +12 -0
+
+int sysfs__write_int(const char *entry, int value)
+{
+	char path[PATH_MAX];
+	const char *sysfs = sysfs__mountpoint();
+
+	if (!sysfs)
+		return -1;
+
+	snprintf(path, sizeof(path), "%s/%s", sysfs, entry);
+
+	return filename__write_int(path, value);

In the unlikely event of an overflow, it would be safer to confirm that the string fit into the path array (by using scnprintf()?) before trying to open that path.

author
#12 lore raw

PATCH 3/3 perf stat: Add support to measure SMI cost

In reply to [email protected]

From: Kan Liang <[email protected]>

Implementing a new --smi-cost mode in perf stat to measure SMI cost. During the measurement, the /sys/device/cpu/freeze_on_smi will be set. The measurement can be done with one counter and two free running MSR counters (IA32_APERF and SMI_COUNT).

The formula to caculate SMI cost is as below. The percentages of SMI cycles = (aperf - cycles) / aperf

metric_only will be set by default unless the user explicitly disable it.

Here is an example output.

Performance counter stats for 'sudo echo ':

SMI cycles% SMI#

    0.1%              1

       0.010858678 seconds time elapsed
Signed-off-by Kan Liang <[email protected]>
---
 tools/perf/Documentation/perf-stat.txt |  9 +++++++
 tools/perf/builtin-stat.c              | 48 ++++++++++++++++++++++++++++++++++
 tools/perf/util/stat-shadow.c          | 33 +++++++++++++++++++++++
 tools/perf/util/stat.c                 |  2 ++
 tools/perf/util/stat.h                 |  2 ++
 5 files changed, 94 insertions(+)
tools/perf/Documentation/perf-stat.txt +9 -0
index 9785481..d8df8e9 100644
@@ -236,6 +236,15 @@ To interpret the results it is usually needed to know on which
 CPUs the workload runs on. If needed the CPUs can be forced using
 taskset.
 
+--smi-cost::
+Measure SMI cost if support and SMI is detected
+
+During the measurement, the /sys/device/cpu/freeze_on_smi will be
+set to freeze cycles counter on SMI. The aperf event will not be
+effected by freeze_on_smi.
+
+The percentages of SMI cycles = (aperf - cycles) / aperf
+
 EXAMPLES
 --------
tools/perf/builtin-stat.c +48 -0

84 lines not on this page · raw message

tools/perf/util/stat-shadow.c +33 -0
index 8a2bbd2..dda7877 100644
@@ -41,6 +41,8 @@ static struct stats runtime_topdown_slots_issued[NUM_CTX][MAX_NR_CPUS];
 static struct stats runtime_topdown_slots_retired[NUM_CTX][MAX_NR_CPUS];
 static struct stats runtime_topdown_fetch_bubbles[NUM_CTX][MAX_NR_CPUS];
 static struct stats runtime_topdown_recovery_bubbles[NUM_CTX][MAX_NR_CPUS];
+static struct stats runtime_smi_num_stats[NUM_CTX][MAX_NR_CPUS];
+static struct stats runtime_aperf_stats[NUM_CTX][MAX_NR_CPUS];
 static bool have_frontend_stalled;
 
 struct stats walltime_nsecs_stats;

@@ -92,6 +94,9 @@ void perf_stat__reset_shadow_stats(void)
 	memset(runtime_topdown_slots_issued, 0, sizeof(runtime_topdown_slots_issued));
 	memset(runtime_topdown_fetch_bubbles, 0, sizeof(runtime_topdown_fetch_bubbles));
 	memset(runtime_topdown_recovery_bubbles, 0, sizeof(runtime_topdown_recovery_bubbles));
+
+	memset(runtime_smi_num_stats, 0, sizeof(runtime_smi_num_stats));
+	memset(runtime_aperf_stats, 0, sizeof(runtime_aperf_stats));
 }
 
 /*

@@ -143,6 +148,10 @@ void perf_stat__update_shadow_stats(struct perf_evsel *counter, u64 *count,
 		update_stats(&runtime_dtlb_cache_stats[ctx][cpu], count[0]);
 	else if (perf_evsel__match(counter, HW_CACHE, HW_CACHE_ITLB))
 		update_stats(&runtime_itlb_cache_stats[ctx][cpu], count[0]);
+	else if (perf_stat_evsel__is(counter, SMI_NUM))
+		update_stats(&runtime_smi_num_stats[ctx][cpu], count[0]);
+	else if (perf_stat_evsel__is(counter, APERF))
+		update_stats(&runtime_aperf_stats[ctx][cpu], count[0]);
 }
 
 /* used for get_ratio_color() */

@@ -423,6 +432,25 @@ static double td_be_bound(int ctx, int cpu)
 	return sanitize_val(1.0 - sum);
 }
 
+static void print_smi_cost(int cpu, struct perf_evsel *evsel,
+			   struct perf_stat_output_ctx *out)
+{
+	double smi_num, aperf, cycles, cost = 0.0;
+	int ctx = evsel_context(evsel);
+	const char *color = NULL;
+
+	smi_num = avg_stats(&runtime_smi_num_stats[ctx][cpu]);
+	aperf = avg_stats(&runtime_aperf_stats[ctx][cpu]);
+	cycles = avg_stats(&runtime_cycles_stats[ctx][cpu]);
+
+	cost = (aperf - cycles) / aperf * 100.00;
+
+	if (cost > 10)
+		color = PERF_COLOR_RED;
+	out->print_metric(out->ctx, color, "%8.1f%%", "SMI cycles%", cost);
+	out->print_metric(out->ctx, NULL, "%4.0f", "SMI#", smi_num);
+}
+
 void perf_stat__print_shadow_stats(struct perf_evsel *evsel,
 				   double avg, int cpu,
 				   struct perf_stat_output_ctx *out)

@@ -628,6 +656,11 @@ void perf_stat__print_shadow_stats(struct perf_evsel *evsel,
 		}
 		snprintf(unit_buf, sizeof(unit_buf), "%c/sec", unit);
 		print_metric(ctxp, NULL, "%8.3f", unit_buf, ratio);
+	} else if (perf_stat_evsel__is(evsel, SMI_NUM)) {
+		if (avg_stats(&runtime_smi_num_stats[ctx][cpu]))
+			print_smi_cost(cpu, evsel, out);
+		else
+			print_metric(ctxp, NULL, NULL, " no SMI detected", 0);
 	} else {
 		print_metric(ctxp, NULL, NULL, NULL, 0);
 	}
tools/perf/util/stat.c +2 -0
index 0d51334..8ae3160f 100644
@@ -84,6 +84,8 @@ static const char *id_str[PERF_STAT_EVSEL_ID__MAX] = {
 	ID(TOPDOWN_SLOTS_RETIRED, topdown-slots-retired),
 	ID(TOPDOWN_FETCH_BUBBLES, topdown-fetch-bubbles),
 	ID(TOPDOWN_RECOVERY_BUBBLES, topdown-recovery-bubbles),
+	ID(SMI_NUM, msr/smi/),
+	ID(APERF, msr/aperf/),
 };
 #undef ID
tools/perf/util/stat.h +2 -0
index c29bb94..c3be07d 100644
@@ -22,6 +22,8 @@ enum perf_stat_evsel_id {
 	PERF_STAT_EVSEL_ID__TOPDOWN_SLOTS_RETIRED,
 	PERF_STAT_EVSEL_ID__TOPDOWN_FETCH_BUBBLES,
 	PERF_STAT_EVSEL_ID__TOPDOWN_RECOVERY_BUBBLES,
+	PERF_STAT_EVSEL_ID__SMI_NUM,
+	PERF_STAT_EVSEL_ID__APERF,
 	PERF_STAT_EVSEL_ID__MAX,
 };
Signature · 1 line
2.7.4
#13 lore raw
In reply to [email protected]
Quoted 10 lines · On Thu, 23 Mar 2017, [email protected] wrote:

From: Kan Liang <[email protected]>

Currently, there is no way to measure the time cost in System management mode (SMM) by perf.

Intel perfmon supports FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. Once it sets, the PMU core counters will freeze on SMI handler. But it will not have an effect on free running counters. E.g. APERF counter.
The cost of SMI can be measured by (aperf - cycles).

Quoted 6 lines

A new sysfs entry /sys/device/cpu/freeze_on_smi is introduced to set FREEZE_WHILE_SMM bit in IA32_DEBUGCTL.

A new --smi-cost mode in perf stat is implemented to measure the SMI cost by calculating cycles and aperf results. In practice, the percentages of SMI cycles should be more useful than absolute value.

That's only true for performance oriented analysis, but for analyzing the root cause of latencies the actual cycles are definitely interesting.

Thanks,

tglx

#14 lore raw
Quoted 6 lines
Quoted 3 lines

A new --smi-cost mode in perf stat is implemented to measure the SMI cost by calculating cycles and aperf results. In practice, the percentages of SMI cycles should be more useful than absolute value.

That's only true for performance oriented analysis, but for analyzing the root cause of latencies the actual cycles are definitely interesting.

perf stat also prints the absolute cycles of course (unless you do --metric-only)

It cannot print individual cycles (per SMI occurrence), the only way to do that would be to poll constantly.

-Andi

#15 lore raw
Quoted 8 lines · Andi Kleen
Quoted 6 lines
Quoted 3 lines

A new --smi-cost mode in perf stat is implemented to measure the SMI cost by calculating cycles and aperf results. In practice, the percentages of SMI cycles should be more useful than absolute value.

That's only true for performance oriented analysis, but for analyzing the root cause of latencies the actual cycles are definitely interesting.

perf stat also prints the absolute cycles of course (unless you do --metric-only)

So much for the theory. From the patch:

+ if (!force_metric_only)
+ metric_only = true;

Quoted 2 lines

It cannot print individual cycles (per SMI occurrence), the only way to do that would be to poll constantly.

I'm well aware of that.

Thanks,

tglx

author
#16 lore raw
Quoted 17 lines
Quoted 9 lines
Quoted 9 lines
Quoted 6 lines

A new --smi-cost mode in perf stat is implemented to measure the SMI cost by calculating cycles and aperf results. In practice, the percentages of SMI cycles should be more useful than absolute value.

That's only true for performance oriented analysis, but for analyzing the root cause of latencies the actual cycles are definitely

interesting.

Quoted 3 lines

perf stat also prints the absolute cycles of course (unless you do --metric-only)

So much for the theory. From the patch:

Review

Quoted 2 lines
(quoted diff) +2 -0
+                       if (!force_metric_only)
+                               metric_only = true;

The metric_only will be set by default in the patch. If user wants to get the actual cycles, they can apply --no-metric-only.

Do you want me to make it clear in the changelog? Or you just don't like that "metric_only=true" is set by default?

Thanks,
Kan

#17 lore raw
In reply to [email protected]
Quoted 10 lines · On Thu, Mar 23, 2017 at 11:25 AM, <[email protected]> wrote:

From: Kan Liang <[email protected]>

Currently, there is no way to measure the time cost in System management mode (SMM) by perf.

Intel perfmon supports FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. Once it sets, the PMU core counters will freeze on SMI handler. But it will not have an effect on free running counters. E.g. APERF counter.
The cost of SMI can be measured by (aperf - cycles).

Quoted 8 lines

A new sysfs entry /sys/device/cpu/freeze_on_smi is introduced to set FREEZE_WHILE_SMM bit in IA32_DEBUGCTL.

A new --smi-cost mode in perf stat is implemented to measure the SMI cost by calculating cycles and aperf results. In practice, the percentages of SMI cycles should be more useful than absolute value. So the output will be the percentage of SMI cycles and SMI#.

You are talking about the percentage of what cycles? Wallclock, unhalted_ref_cycles, unhalted_core_cycles? I

Quoted 31 lines

Here is an example output.

Performance counter stats for 'sudo echo ':

SMI cycles% SMI#

    0.1%              1

       0.010858678 seconds time elapsed

Kan Liang (3):
perf/x86: add sysfs entry to freeze counter on SMI tools lib api fs: Add sysfs__write_int function perf stat: Add support to measure SMI cost

 arch/x86/events/core.c                 | 10 +++++++
 arch/x86/events/intel/core.c           | 48 ++++++++++++++++++++++++++++++++++
 arch/x86/events/perf_event.h           |  3 +++
 arch/x86/include/asm/msr-index.h       |  1 +
 tools/lib/api/fs/fs.c                  | 29 ++++++++++++++++++++
 tools/lib/api/fs/fs.h                  |  4 +++
 tools/perf/Documentation/perf-stat.txt |  9 +++++++
 tools/perf/builtin-stat.c              | 48 ++++++++++++++++++++++++++++++++++
 tools/perf/util/stat-shadow.c          | 33 +++++++++++++++++++++++
 tools/perf/util/stat.c                 |  2 ++
 tools/perf/util/stat.h                 |  2 ++
 11 files changed, 189 insertions(+)

--
2.7.4

author
#18 lore raw
Quoted 17 lines · On Thu, Mar 23, 2017 at 11:25 AM, <[email protected]> wrote:
Quoted 6 lines

From: Kan Liang <[email protected]>

Currently, there is no way to measure the time cost in System management mode (SMM) by perf.

Intel perfmon supports FREEZE_WHILE_SMM bit in IA32_DEBUGCTL. Once

it

Quoted 7 lines

sets, the PMU core counters will freeze on SMI handler. But it will not have an effect on free running counters. E.g. APERF counter. The cost of SMI can be measured by (aperf - cycles).

A new sysfs entry /sys/device/cpu/freeze_on_smi is introduced to set FREEZE_WHILE_SMM bit in IA32_DEBUGCTL.

Quoted 7 lines
Quoted 5 lines

A new --smi-cost mode in perf stat is implemented to measure the SMI cost by calculating cycles and aperf results. In practice, the percentages of SMI cycles should be more useful than absolute value. So the output will be the percentage of SMI cycles and SMI#.

You are talking about the percentage of what cycles? Wallclock, unhalted_ref_cycles, unhalted_core_cycles?

Unhalted core cycles.

Thanks,
Kan