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serial: Add serial driver for Intel MID

PATCH Superseded Andy Shevchenko 5 participants 7 messages Feb 28, 2017 – Apr 10, 2017

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Andy Shevchenko

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#0 lore raw

PATCH v3 1/1 serial: Add serial driver for Intel MID

Add a specific serial driver for Intel MID platforms.

It has special fractional divider which can be programmed via UART_PS, UART_MUL, and UART_DIV registers.

The UART clock is calculated as

UART clock = XTAL * UART_MUL / UART_DIV

The baudrate is calculated as

baud rate = UART clock / UART_PS / DLAB

Initialize fractional divider correctly for Intel Edison platform.

For backward compatibility we have to set initial DLAB value to 16 and speed to 115200 baud, where initial frequency is 29491200Hz, and XTAL frequency is 38.4MHz.

Signed-off-by Andy Shevchenko <[email protected]>
---
 drivers/serial/Kconfig            |  9 +++++
 drivers/serial/Makefile           |  1 +
 drivers/serial/serial_intel_mid.c | 69 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 79 insertions(+)
 create mode 100644 drivers/serial/serial_intel_mid.c
drivers/serial/Kconfig +9 -0
index b11f3ff89e..99dcdeb00d 100644
@@ -347,6 +347,15 @@ config SYS_NS16550
 	  be used. It can be a constant or a function to get clock, eg,
 	  get_serial_clock().
 
+config INTEL_MID_SERIAL
+	bool "Intel MID platform UART support"
+	depends on DM_SERIAL && OF_CONTROL
+	depends on INTEL_MID
+	select SYS_NS16550
+	help
+	  Select this to enable a UART for Intel MID platforms.
+	  This uses the ns16550 driver as a library.
+
 config ROCKCHIP_SERIAL
 	bool "Rockchip on-chip UART support"
 	depends on DM_SERIAL && SPL_OF_PLATDATA
drivers/serial/Makefile +1 -0
index 8430668bf9..abd9dea4dc 100644
@@ -28,6 +28,7 @@ obj-$(CONFIG_S5P) += serial_s5p.o
 obj-$(CONFIG_MXC_UART) += serial_mxc.o
 obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
 obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
+obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
 endif
drivers/serial/serial_intel_mid.c new file +69 -0

69 lines not on this page · raw message

Signature · 1 line
2.11.0
#1 lore raw

PATCH v3 1/1 serial: Add serial driver for Intel MID

Quoted 19 lines · Andy Shevchenko

Add a specific serial driver for Intel MID platforms.

It has special fractional divider which can be programmed via UART_PS, UART_MUL, and UART_DIV registers.

The UART clock is calculated as

UART clock = XTAL * UART_MUL / UART_DIV

The baudrate is calculated as

baud rate = UART clock / UART_PS / DLAB

Initialize fractional divider correctly for Intel Edison platform.

For backward compatibility we have to set initial DLAB value to 16 and speed to 115200 baud, where initial frequency is 29491200Hz, and XTAL frequency is 38.4MHz.

Quoted 7 lines
Signed-off-by Andy Shevchenko <[email protected]>
---
 drivers/serial/Kconfig            |  9 +++++
 drivers/serial/Makefile           |  1 +
 drivers/serial/serial_intel_mid.c | 69 +++++++++++++++++++++++++++++++++++++++
 3 files changed, 79 insertions(+)
 create mode 100644 drivers/serial/serial_intel_mid.c
Reviewed-by Simon Glass <[email protected]>
#2 lore raw

PATCH v3 1/1 serial: Add serial driver for Intel MID

In reply to Andy Shevchenko

Hi Andy,

Quoted 124 lines · Andy Shevchenko

Add a specific serial driver for Intel MID platforms.

It has special fractional divider which can be programmed via UART_PS, UART_MUL, and UART_DIV registers.

The UART clock is calculated as

UART clock = XTAL * UART_MUL / UART_DIV

The baudrate is calculated as

baud rate = UART clock / UART_PS / DLAB

Initialize fractional divider correctly for Intel Edison platform.

For backward compatibility we have to set initial DLAB value to 16 and speed to 115200 baud, where initial frequency is 29491200Hz, and XTAL frequency is 38.4MHz.

Signed-off-by Andy Shevchenko <[email protected]>
---
  drivers/serial/Kconfig            |  9 +++++
  drivers/serial/Makefile           |  1 +
  drivers/serial/serial_intel_mid.c | 69 +++++++++++++++++++++++++++++++++++++++
  3 files changed, 79 insertions(+)

create mode 100644 drivers/serial/serial_intel_mid.c

drivers/serial/Kconfig +9 -0
index b11f3ff89e..99dcdeb00d 100644
@@ -347,6 +347,15 @@ config SYS_NS16550
  	  be used. It can be a constant or a function to get clock, eg,
  	  get_serial_clock().
 
+config INTEL_MID_SERIAL
+	bool "Intel MID platform UART support"
+	depends on DM_SERIAL && OF_CONTROL
+	depends on INTEL_MID
+	select SYS_NS16550
+	help
+	  Select this to enable a UART for Intel MID platforms.
+	  This uses the ns16550 driver as a library.
+
  config ROCKCHIP_SERIAL
  	bool "Rockchip on-chip UART support"
  	depends on DM_SERIAL && SPL_OF_PLATDATA
drivers/serial/Makefile +1 -0
index 8430668bf9..abd9dea4dc 100644
@@ -28,6 +28,7 @@ obj-$(CONFIG_S5P) += serial_s5p.o
  obj-$(CONFIG_MXC_UART) += serial_mxc.o
  obj-$(CONFIG_PXA_SERIAL) += serial_pxa.o
  obj-$(CONFIG_MESON_SERIAL) += serial_meson.o
+obj-$(CONFIG_INTEL_MID_SERIAL) += serial_intel_mid.o
  ifdef CONFIG_SPL_BUILD
  obj-$(CONFIG_ROCKCHIP_SERIAL) += serial_rockchip.o
  endif
drivers/serial/serial_intel_mid.c new file +59 -0
new file mode 100644
index 0000000000..777c09d6d2
@@ -0,0 +1,69 @@
+/*
+ * Copyright (c) 2017 Intel Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <ns16550.h>
+#include <serial.h>
+
+/*
+ * The UART clock is calculated as
+ *
+ *	UART clock = XTAL * UART_MUL / UART_DIV
+ *
+ * The baudrate is calculated as
+ *
+ *	baud rate = UART clock / UART_PS / DLAB
+ */
+#define UART_PS		0x30
+#define UART_MUL	0x34
+#define UART_DIV	0x38
+
+static void mid_writel(struct ns16550_platdata *plat, int offset, int value)
+{
+	unsigned char *addr;
+
+	offset *= 1 << plat->reg_shift;
+	addr = (unsigned char *)plat->base + offset;
+
+	writel(value, addr + plat->reg_offset);
+}
+
+static int mid_serial_probe(struct udevice *dev)
+{
+	struct ns16550_platdata *plat = dev_get_platdata(dev);
+
+	/*
+	 * Initialize fractional divider correctly for Intel Edison
+	 * platform.
+	 *
+	 * For backward compatibility we have to set initial DLAB value
+	 * to 16 and speed to 115200 baud, where initial frequency is
+	 * 29491200Hz, and XTAL frequency is 38.4MHz.
+	 */
+	mid_writel(plat, UART_MUL, 96);
+	mid_writel(plat, UART_DIV, 125);
+	mid_writel(plat, UART_PS, 16);
+
+	return ns16550_serial_probe(dev);
+}
+
+static const struct udevice_id mid_serial_ids[] = {
+	{ .compatible = "intel,mid-uart" },
+	{}
+};
+
+U_BOOT_DRIVER(serial_intel_mid) = {

drivers/serial/serial_intel_mid.c line 69

Quoted 10 lines
drivers/serial/serial_intel_mid.c new file +10 -0
+	.name	= "serial_intel_mid",
+	.id	= UCLASS_SERIAL,
+	.of_match = mid_serial_ids,
+	.ofdata_to_platdata = ns16550_serial_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct ns16550_platdata),
+	.priv_auto_alloc_size = sizeof(struct NS16550),
+	.probe	= mid_serial_probe,
+	.ops	= &ns16550_serial_ops,
+	.flags	= DM_FLAG_PRE_RELOC,
+};
Reviewed-by Kever Yang <[email protected]>

Thanks,
- Kever

#3 lore raw

PATCH v3 1/1 serial: Add serial driver for Intel MID

Quoted 15 lines · Kever Yang
Quoted 14 lines · Andy Shevchenko

Add a specific serial driver for Intel MID platforms.

It has special fractional divider which can be programmed via UART_PS, UART_MUL, and UART_DIV registers.

The UART clock is calculated as

UART clock = XTAL * UART_MUL / UART_DIV

The baudrate is calculated as

baud rate = UART clock / UART_PS / DLAB

Quoted 7 lines
Quoted 5 lines

Initialize fractional divider correctly for Intel Edison platform.

For backward compatibility we have to set initial DLAB value to 16 and speed to 115200 baud, where initial frequency is 29491200Hz, and XTAL frequency is 38.4MHz.

Reviewed-by Kever Yang <[email protected]>

Thanks!

Tom et all, is it forgotten?

Signature · 2 lines
With Best Regards,
Andy Shevchenko
author
#4 lore raw

PATCH v3 1/1 serial: Add serial driver for Intel MID

Quoted 24 lines · Andy Shevchenko

On Fri, Mar 3, 2017 at 12:31 PM, Kever Yang <[email protected]

Quoted 23 lines

wrote:

Quoted 21 lines · Andy Shevchenko

Add a specific serial driver for Intel MID platforms.

It has special fractional divider which can be programmed via UART_PS,
UART_MUL, and UART_DIV registers.

The UART clock is calculated as

        UART clock = XTAL * UART_MUL / UART_DIV

The baudrate is calculated as

        baud rate = UART clock / UART_PS / DLAB

Initialize fractional divider correctly for Intel Edison platform.

For backward compatibility we have to set initial DLAB value to 16 and speed to 115200 baud, where initial frequency is 29491200Hz, and
XTAL frequency is 38.4MHz.

Quoted 5 lines
Quoted 1 line
Reviewed-by Kever Yang <[email protected]>

Thanks!

Tom et all, is it forgotten?

Any update on this? Should I do something about?

Signature · 2 lines
Andy Shevchenko <[email protected]>
Intel Finland Oy
#5 lore raw

PATCH v3 1/1 serial: Add serial driver for Intel MID

+Bin

Hi,

Quoted 25 lines · Andy Shevchenko
Quoted 24 lines · Andy Shevchenko

On Fri, Mar 3, 2017 at 12:31 PM, Kever Yang <[email protected]

Quoted 23 lines

wrote:

Quoted 21 lines · Andy Shevchenko

Add a specific serial driver for Intel MID platforms.

It has special fractional divider which can be programmed via UART_PS,
UART_MUL, and UART_DIV registers.

The UART clock is calculated as

UART clock = XTAL * UART_MUL / UART_DIV

The baudrate is calculated as

baud rate = UART clock / UART_PS / DLAB

Initialize fractional divider correctly for Intel Edison platform.

For backward compatibility we have to set initial DLAB value to 16 and speed to 115200 baud, where initial frequency is 29491200Hz, and
XTAL frequency is 38.4MHz.

Quoted 7 lines
Quoted 5 lines
Quoted 1 line
Reviewed-by Kever Yang <[email protected]>

Thanks!

Tom et all, is it forgotten?

Any update on this? Should I do something about?

Probably Bin can apply it - it's a good idea to cc him on x86 stuff. If not let me know and I can pull it in via DM.

Regards,
Simon

#6 lore raw

PATCH v3 1/1 serial: Add serial driver for Intel MID

Quoted 33 lines · Simon Glass

+Bin

Hi,

Quoted 27 lines · Andy Shevchenko
Quoted 26 lines · Andy Shevchenko

On Fri, Mar 3, 2017 at 12:31 PM, Kever Yang <[email protected]

Quoted 24 lines

wrote:

Quoted 13 lines · Andy Shevchenko

Add a specific serial driver for Intel MID platforms.

It has special fractional divider which can be programmed via UART_PS,
UART_MUL, and UART_DIV registers.

The UART clock is calculated as

UART clock = XTAL * UART_MUL / UART_DIV

The baudrate is calculated as

Quoted 8 lines

baud rate = UART clock / UART_PS / DLAB

Initialize fractional divider correctly for Intel Edison platform.

For backward compatibility we have to set initial DLAB value to 16 and speed to 115200 baud, where initial frequency is 29491200Hz, and
XTAL frequency is 38.4MHz.

Reviewed-by Kever Yang <[email protected]>
Quoted 9 lines
Quoted 5 lines
Quoted 3 lines

Thanks!

Tom et all, is it forgotten?

Any update on this? Should I do something about?

Probably Bin can apply it - it's a good idea to cc him on x86 stuff. If not let me know and I can pull it in via DM.

applied to u-boot-x86, thanks!