arcv2: Make sure busy bit is set properly on SLC flushing

As reported in STAR 9001165532 if data cache gets disabled right before L2 cache invalidation we may read wrong value of L2 cache "busy" bit. So we won't wait before L2 cache gets properly flushed and so some data might not reach DDR at all thus we'll use older values from DDR next time they are accessed.

For now we use a work-around with one extra read from SLC's control register which guarantees next read will return real value of "busy" bit.

Signed-off-by Alexey Brodkin <abrodkin at synopsys.com>

---
 arch/arc/mm/cache.c | 3 +++
 1 file changed, 3 insertions(+)

arch/arc/mm/cache.c +3 -0

index d408fa21a07c..899f1d6b3560 100644
@@ -633,6 +633,9 @@ noinline static void slc_entire_op(const int op)
 
 	write_aux_reg(ARC_REG_SLC_INVALIDATE, 1);
 
+	/* Make sure "busy" bit reports correct stataus, see STAR 9001165532 */
+	read_aux_reg(r);
+
 	/* Important to wait for flush to complete */
 	while (read_aux_reg(r) & SLC_CTRL_BUSY);
 }

Quoted 7 lines · Alexey Brodkin

As reported in STAR 9001165532 if data cache gets disabled right before L2 cache invalidation we may read wrong value of L2 cache "busy" bit. So we won't wait before L2 cache gets properly flushed and so some data might not reach DDR at all thus we'll use older values from DDR next time they are accessed.

Quoted 5 lines

For now we use a work-around with one extra read from SLC's control register which guarantees next read will return real value of "busy" bit.

Signed-off-by Alexey Brodkin <abrodkin at synopsys.com>

Thx Alexey - pushed to for-curr !