Add Intel Arria 10 SoC support

Add SPL support for Arria 10.

Signed-off-by Tien Fong Chee <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/spl.c | 72 +++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach-socfpga/spl.c +18 -3

index 0064fc8..f4a3cdd 100644
@@ -19,23 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
 	const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
-	switch (bsel & 0x7) {
+	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
 	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
 		return BOOT_DEVICE_RAM;
 	case 0x2:	/* NAND Flash (1.8V) */

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
 	writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
 #endif
 	unsigned long sdram_size;
 	unsigned long reg;
+	int ret;
 
 	/*
 	 * First C code to run. Clear fake OCRAM ECC first as SBE

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
 	/* Put everything into reset but L4WD0. */
 	socfpga_per_reset_all();
 	/* Put FPGA bridges into reset too. */
-	socfpga_bridges_reset(1);
+	ret = socfpga_bridges_reset(1);
+	if (ret) {
+		printf("socfpga_bridges_reset() failed: %d\n", ret);
+		hang();
+	}
 
 	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
 	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

Quoted 78 lines · Ley Foon Tan

Add SPL support for Arria 10.

Signed-off-by Tien Fong Chee <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/spl.c | 72 +++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach-socfpga/spl.c +18 -3

index 0064fc8..f4a3cdd 100644
@@ -19,23 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
 	(struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
 	(struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
 	(struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
 	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
 	const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
-	switch (bsel & 0x7) {
+	switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
 	case 0x1:	/* FPGA (HPS2FPGA Bridge) */
 		return BOOT_DEVICE_RAM;
 	case 0x2:	/* NAND Flash (1.8V) */

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
 	writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
 #endif
 	unsigned long sdram_size;
 	unsigned long reg;
+	int ret;
 
 	/*
 	 * First C code to run. Clear fake OCRAM ECC first as SBE

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
 	/* Put everything into reset but L4WD0. */
 	socfpga_per_reset_all();
 	/* Put FPGA bridges into reset too. */
-	socfpga_bridges_reset(1);
+	ret = socfpga_bridges_reset(1);
+	if (ret) {
+		printf("socfpga_bridges_reset() failed: %d\n", ret);
+		hang();
+	}
 
 	socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
 	socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 169

Quoted 7 lines

arch/arm/mach-socfpga/spl.c +4 -1

 	/* De-assert reset for peripherals and bridges based on handoff */
 	reset_deassert_peripherals_handoff();
-	socfpga_bridges_reset(0);
+	ret = socfpga_bridges_reset(0);
+	if (ret) {
+		printf("socfpga_bridges_reset() failed: %d\n", ret);
+		hang();

If you keep this patch the way it is, this will cause the Atlas board to hang here.

CC Dalon Westergreen

Quoted 81 lines · Dinh Nguyen

Quoted 78 lines · Ley Foon Tan

Add SPL support for Arria 10.

Signed-off-by Tien Fong Chee <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---
 arch/arm/mach-socfpga/spl.c | 72 +++++++++++++++++++++++++++++++++++++++++----
 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach-socfpga/spl.c +18 -3

index 0064fc8..f4a3cdd 100644
@@ -19,23 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
     (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;
     case 0x2:       /* NAND Flash (1.8V) */

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
     writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
 #endif
     unsigned long sdram_size;
     unsigned long reg;
+    int ret;
 
     /*
      * First C code to run. Clear fake OCRAM ECC first as SBE

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
     /* Put everything into reset but L4WD0. */
     socfpga_per_reset_all();
     /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret);
+            hang();
+    }
 
     socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 

Quoted 11 lines

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 169

Quoted 7 lines

arch/arm/mach-socfpga/spl.c +4 -1

     /* De-assert reset for peripherals and bridges based on handoff */
     reset_deassert_peripherals_handoff();
-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret);
+            hang();

If you keep this patch the way it is, this will cause the Atlas board to hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is failing, because is_fpgamgr_initdone_high() is returning 0.

Dinh
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
https://lists.denx.de/listinfo/u-boot

Really including Dalon

Quoted 13 lines · Dinh Nguyen

CC Dalon Westergreen

Quoted 9 lines · Dinh Nguyen

Quoted 6 lines · Ley Foon Tan

Add SPL support for Arria 10.

Quoted 2 lines

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Signed-off-by Tien Fong Chee <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---

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 arch/arm/mach-socfpga/spl.c | 72

Quoted 84 lines

Quoted 83 lines

Quoted 71 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach-socfpga/spl.c +7 -0

index 0064fc8..f4a3cdd 100644
@@ -19,23 +19,32 @@
  #include <asm/arch/sdram.h>
  #include <asm/arch/scu.h>
  #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
  DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

 static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;

arch/arm/mach-socfpga/spl.c +3 -1

-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =

     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);

-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;
     case 0x2:       /* NAND Flash (1.8V) */

arch/arm/mach-socfpga/spl.c +7 -1

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
  }
  #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  static void socfpga_nic301_slave_ns(void)
  {
      writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
  #endif
      unsigned long sdram_size;
      unsigned long reg;
+    int ret;
 
      /*
       * First C code to run. Clear fake OCRAM ECC first as SBE

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
      /* Put everything into reset but L4WD0. */
      socfpga_per_reset_all();
      /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret);
+            hang();
+    }
 
      socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
      socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 169

Quoted 8 lines

arch/arm/mach-socfpga/spl.c +4 -1

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 
      /* De-assert reset for peripherals and bridges based on handoff */
      reset_deassert_peripherals_handoff();
-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret);
+            hang();

If you keep this patch the way it is, this will cause the Atlas board to hang here.

Quoted 7 lines

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is failing, because is_fpgamgr_initdone_high() is returning 0.

Dinh

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_______________________________________________

Quoted 27 lines · Dinh Nguyen

Really including Dalon

Quoted 24 lines · Dinh Nguyen

CC Dalon Westergreen

Quoted 19 lines · Dinh Nguyen

Quoted 15 lines · Ley Foon Tan

Add SPL support for Arria 10.

Quoted 6 lines

Quoted 6 lines

Quoted 6 lines

Quoted 6 lines

Signed-off-by Tien Fong Chee <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---

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 arch/arm/mach-socfpga/spl.c | 72

+++++++++++++++++++++++++++++++++++++++++----

Quoted 95 lines

Quoted 95 lines

Quoted 76 lines

Quoted 76 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach-socfpga/spl.c +7 -0

index 0064fc8..f4a3cdd 100644
@@ -19,23 +19,32 @@
  #include <asm/arch/sdram.h>
  #include <asm/arch/scu.h>
  #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
  DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

 static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;

arch/arm/mach-socfpga/spl.c +3 -1

-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =

     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);

-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;
     case 0x2:       /* NAND Flash (1.8V) */

arch/arm/mach-socfpga/spl.c +7 -1

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
  }
  #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  static void socfpga_nic301_slave_ns(void)
  {
      writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
  #endif
      unsigned long sdram_size;
      unsigned long reg;
+    int ret;
 
      /*
       * First C code to run. Clear fake OCRAM ECC first as SBE

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
      /* Put everything into reset but L4WD0. */
      socfpga_per_reset_all();
      /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret);
+            hang();
+    }
 
      socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
      socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 

Quoted 12 lines

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 169

Quoted 8 lines

arch/arm/mach-socfpga/spl.c +4 -1

      /* De-assert reset for peripherals and bridges based on handoff
 */
      reset_deassert_peripherals_handoff();
-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret);
+            hang();

If you keep this patch the way it is, this will cause the Atlas board to hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is failing, because is_fpgamgr_initdone_high() is returning 0.

Quoted 1 line

Quoted 1 line

Dinh

i saw it the first go round.  i will test this out this afternoon.

--dalon

Quoted 11 lines

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_______________________________________________

U-Boot mailing list
U-Boot at lists.denx.de
https://lists.denx.de/listinfo/u-boot

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
https://lists.denx.de/listinfo/u-boot
_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
https://lists.denx.de/listinfo/u-boot

Quoted 124 lines · Dalon Westergreen

Quoted 27 lines · Dinh Nguyen

Really including Dalon

Quoted 24 lines · Dinh Nguyen

CC Dalon Westergreen

Quoted 19 lines · Dinh Nguyen

Quoted 15 lines · Ley Foon Tan

Add SPL support for Arria 10.

Quoted 6 lines

Quoted 6 lines

Quoted 6 lines

Quoted 6 lines

Signed-off-by Tien Fong Chee <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---

Quoted 5 lines

Quoted 5 lines

Quoted 5 lines

Quoted 5 lines

 arch/arm/mach-socfpga/spl.c | 72

+++++++++++++++++++++++++++++++++++++++++----

Quoted 95 lines

Quoted 95 lines

Quoted 76 lines

Quoted 76 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach-socfpga/spl.c +18 -3

index 0064fc8..f4a3cdd 100644
@@ -19,23 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
     (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;
     case 0x2:       /* NAND Flash (1.8V) */

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
     writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
 #endif
     unsigned long sdram_size;
     unsigned long reg;
+    int ret;
 
     /*
      * First C code to run. Clear fake OCRAM ECC first as SBE

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
     /* Put everything into reset but L4WD0. */
     socfpga_per_reset_all();
     /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret);
+            hang();
+    }
 
     socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 

Quoted 12 lines

arch/arm/mach-socfpga/spl.c void board_init_f(ulong dummy) · line 169

Quoted 8 lines

arch/arm/mach-socfpga/spl.c +4 -1

     /* De-assert reset for peripherals and bridges based on handoff
 */
     reset_deassert_peripherals_handoff();
-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret);
+            hang();

If you keep this patch the way it is, this will cause the Atlas board to hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is failing, because is_fpgamgr_initdone_high() is returning 0.

Quoted 5 lines

Quoted 1 line

Quoted 1 line

Dinh

i saw it the first go round. i will test this out this afternoon.

--dalon

i see the exact same thing. for the c5/a5 devices there is no reason for init done to be high since fpga configuration isnt required to boot.

Quoted 149 lines · Dalon Westergreen

Quoted 147 lines · Dalon Westergreen

Quoted 40 lines · Dinh Nguyen

Really including Dalon

Quoted 36 lines

On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <[email protected]> wrote:
CC: Dalon Westergreen

Quoted 29 lines · Dinh Nguyen

Quoted 24 lines · Ley Foon Tan

Add SPL support for Arria 10.

Quoted 10 lines

Quoted 10 lines

Quoted 10 lines

Quoted 10 lines

Signed-off-by Tien Fong Chee <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---

Quoted 9 lines

Quoted 9 lines

Quoted 9 lines

Quoted 9 lines

 arch/arm/mach-socfpga/spl.c | 72

+++++++++++++++++++++++++++++++++++++++++----

Quoted 103 lines

Quoted 103 lines

Quoted 81 lines

Quoted 81 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index 0064fc8..f4a3cdd 100644

arch/arm/mach-socfpga/spl.c +7 -0

@@ -19,23 +19,32 @@
  #include <asm/arch/sdram.h>
  #include <asm/arch/scu.h>
  #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
  DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

 static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;

arch/arm/mach-socfpga/spl.c +3 -1

-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =

     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);

-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;
     case 0x2:       /* NAND Flash (1.8V) */

arch/arm/mach-socfpga/spl.c +7 -1

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
  }
  #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  static void socfpga_nic301_slave_ns(void)
  {
      writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
  #endif
      unsigned long sdram_size;
      unsigned long reg;
+    int ret;
 
      /*
       * First C code to run. Clear fake OCRAM ECC first as SBE

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
      /* Put everything into reset but L4WD0. */
      socfpga_per_reset_all();
      /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret);
+            hang();
+    }
 
      socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
      socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 

Quoted 14 lines

Quoted 9 lines

arch/arm/mach-socfpga/spl.c +0 -0

      /* De-assert reset for peripherals and bridges based on

handoff
*/
     reset_deassert_peripherals_handoff();
-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret); +            hang();

If you keep this patch the way it is, this will cause the Atlas board to
hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is failing, because is_fpgamgr_initdone_high() is returning 0.

Dinh

Quoted 7 lines

Quoted 3 lines

i saw it the first go round.  i will test this out this afternoon.

--dalon

i see the exact same thing.  for the c5/a5 devices there is no reason for init
done to be high since fpga configuration isnt required to boot.

Okay, good! It doesn't happen on the C5 devkit though.

Ley Foon, did you test this on the Arria5?

Dinh

Quoted 184 lines · Dinh Nguyen

Quoted 169 lines · Dalon Westergreen

Quoted 166 lines · Dalon Westergreen

Quoted 52 lines · Dinh Nguyen

Really including Dalon

Quoted 47 lines

On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <[email protected]> wrote:
CC: Dalon Westergreen

Quoted 39 lines · Dinh Nguyen

Quoted 33 lines · Ley Foon Tan

Add SPL support for Arria 10.

Quoted 12 lines

Quoted 12 lines

Quoted 12 lines

Quoted 12 lines

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

Signed-off-by Tien Fong Chee <[email protected]>

Signed-off-by Ley Foon Tan <[email protected]>

---

Quoted 13 lines

Quoted 13 lines

Quoted 13 lines

Quoted 13 lines

 arch/arm/mach-socfpga/spl.c | 72

+++++++++++++++++++++++++++++++++++++++++----

Quoted 109 lines

Quoted 109 lines

Quoted 86 lines

Quoted 86 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index 0064fc8..f4a3cdd 100644

arch/arm/mach-socfpga/spl.c +7 -0

@@ -19,23 +19,32 @@
  #include <asm/arch/sdram.h>
  #include <asm/arch/scu.h>
  #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
  DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

 static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;

arch/arm/mach-socfpga/spl.c +3 -1

-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =

     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;

 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);

-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;
     case 0x2:       /* NAND Flash (1.8V) */

arch/arm/mach-socfpga/spl.c +7 -1

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
  }
  #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  static void socfpga_nic301_slave_ns(void)
  {
      writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
  #endif
      unsigned long sdram_size;
      unsigned long reg;
+    int ret;
 
      /*
       * First C code to run. Clear fake OCRAM ECC first as SBE

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
      /* Put everything into reset but L4WD0. */
      socfpga_per_reset_all();
      /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n",
 ret);
+            hang();
+    }
 
      socfpga_per_reset(SOCFPGA_RESET(SDR), 0);

     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

arch/arm/mach-socfpga/spl.c +0 -0

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 

Quoted 15 lines

Quoted 10 lines

arch/arm/mach-socfpga/spl.c +0 -0

      /* De-assert reset for peripherals and bridges based on

handoff
*/
     reset_deassert_peripherals_handoff();
-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n", ret);
+            hang();

If you keep this patch the way it is, this will cause the Atlas board to
hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is failing, because is_fpgamgr_initdone_high() is returning 0.

Dinh

Quoted 7 lines

Quoted 3 lines

i saw it the first go round.  i will test this out this afternoon.

--dalon

i see the exact same thing.  for the c5/a5 devices there is no reason for init
done to be high since fpga configuration isnt required to boot.

Okay, good! It doesn't happen on the C5 devkit though.

Ley Foon, did you test this on the Arria5?

Quoted 1 line

Dinh

Odd, init done should not be high without the FPGA configured.  i will try it on
the c5 board as well to try and figure out why init done is high.

--dalon

_______________________________________________
U-Boot mailing list
U-Boot at lists.denx.de
https://lists.denx.de/listinfo/u-boot

Quoted 191 lines · Dalon Westergreen

Quoted 180 lines · Dinh Nguyen

Quoted 169 lines · Dalon Westergreen

Quoted 166 lines · Dalon Westergreen

Quoted 52 lines · Dinh Nguyen

Really including Dalon

Quoted 47 lines

On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <[email protected]> wrote:
CC: Dalon Westergreen

Quoted 39 lines · Dinh Nguyen

Quoted 33 lines · Ley Foon Tan

Add SPL support for Arria 10.

Quoted 12 lines

Quoted 12 lines

Quoted 12 lines

Quoted 12 lines

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>

---

Quoted 13 lines

Quoted 13 lines

Quoted 13 lines

Quoted 13 lines

arch/arm/mach-socfpga/spl.c | 72

+++++++++++++++++++++++++++++++++++++++++----

Quoted 109 lines

Quoted 109 lines

Quoted 86 lines

Quoted 86 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index 0064fc8..f4a3cdd 100644

arch/arm/mach-socfpga/spl.c +18 -3

@@ -19,23 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
     (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;
     case 0x2:       /* NAND Flash (1.8V) */

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
     writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
 #endif
     unsigned long sdram_size;
     unsigned long reg;
+    int ret;
 
     /*
      * First C code to run. Clear fake OCRAM ECC first as SBE

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
     /* Put everything into reset but L4WD0. */
     socfpga_per_reset_all();
     /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n",
 ret);
+            hang();
+    }
 
     socfpga_per_reset(SOCFPGA_RESET(SDR), 0);

     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

arch/arm/mach-socfpga/spl.c +0 -0

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 

Quoted 15 lines

Quoted 10 lines

arch/arm/mach-socfpga/spl.c +0 -0

     /* De-assert reset for peripherals and bridges based on

handoff
*/

     reset_deassert_peripherals_handoff();

arch/arm/mach-socfpga/spl.c +3 -1

-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n",

ret);
+ hang();

If you keep this patch the way it is, this will cause the Atlas board to
hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is failing, because is_fpgamgr_initdone_high() is returning 0.

Dinh

Quoted 7 lines

Quoted 3 lines

i saw it the first go round. i will test this out this afternoon.

--dalon

i see the exact same thing. for the c5/a5 devices there is no reason for init
done to be high since fpga configuration isnt required to boot.

Quoted 5 lines

Okay, good! It doesn't happen on the C5 devkit though.

Ley Foon, did you test this on the Arria5?

Dinh

Odd, init done should not be high without the FPGA configured. i will try it on
the c5 board as well to try and figure out why init done is high.

Quoted 1 line

--dalon

I ran this on the c5 socdk and noticed the same behavior as Dinh, then realized the board was setup to configure the fpga independently of the processor. When i change the MSELs on the board to ensure the FPGA is unconfigured the code fails in the same location where init done is not high. It is definitely an expected use case in c5/a5 that uboot can run without the fpga configured at all.

Quoted 192 lines · Dalon Westergreen

Quoted 191 lines · Dalon Westergreen

Quoted 180 lines · Dinh Nguyen

Quoted 169 lines · Dalon Westergreen

Quoted 166 lines · Dalon Westergreen

Quoted 52 lines · Dinh Nguyen

Really including Dalon

Quoted 47 lines

On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <[email protected]> wrote:
CC: Dalon Westergreen

Quoted 39 lines · Dinh Nguyen

Quoted 33 lines · Ley Foon Tan

Add SPL support for Arria 10.

Quoted 12 lines

Quoted 12 lines

Quoted 12 lines

Quoted 2 lines

Quoted 2 lines

Quoted 2 lines

Signed-off-by: Tien Fong Chee <[email protected]>
Signed-off-by: Ley Foon Tan <[email protected]>

---

Quoted 13 lines

Quoted 13 lines

Quoted 13 lines

arch/arm/mach-socfpga/spl.c | 72

+++++++++++++++++++++++++++++++++++++++++----

Quoted 109 lines

Quoted 109 lines

Quoted 86 lines

Quoted 86 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index 0064fc8..f4a3cdd 100644

arch/arm/mach-socfpga/spl.c +18 -3

@@ -19,23 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
     (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
     (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;
     case 0x2:       /* NAND Flash (1.8V) */

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
     writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
 #endif
     unsigned long sdram_size;
     unsigned long reg;
+    int ret;
 
     /*
      * First C code to run. Clear fake OCRAM ECC first as SBE

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
     /* Put everything into reset but L4WD0. */
     socfpga_per_reset_all();
     /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n",
 ret);
+            hang();
+    }
 
     socfpga_per_reset(SOCFPGA_RESET(SDR), 0);

     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

arch/arm/mach-socfpga/spl.c +0 -0

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 

Quoted 15 lines

Quoted 10 lines

arch/arm/mach-socfpga/spl.c +0 -0

     /* De-assert reset for peripherals and bridges based on

handoff
*/

     reset_deassert_peripherals_handoff();

arch/arm/mach-socfpga/spl.c +3 -1

-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed: %d\n",

ret);
+ hang();

If you keep this patch the way it is, this will cause the Atlas board to
hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is failing, because is_fpgamgr_initdone_high() is returning 0.

Dinh

Quoted 7 lines

Quoted 3 lines

i saw it the first go round. i will test this out this afternoon.

--dalon

i see the exact same thing. for the c5/a5 devices there is no reason for init
done to be high since fpga configuration isnt required to boot.

Quoted 5 lines

Okay, good! It doesn't happen on the C5 devkit though.

Ley Foon, did you test this on the Arria5?

Dinh

Odd, init done should not be high without the FPGA configured. i will try it on
the c5 board as well to try and figure out why init done is high.

Quoted 8 lines

Quoted 1 line

--dalon

I ran this on the c5 socdk and noticed the same behavior as Dinh, then realized the board was setup to configure the fpga independently of the processor. When i change the MSELs on the board to ensure the FPGA is unconfigured the code fails in the same location where init done is not high. It is definitely an expected use case in c5/a5 that uboot can run without the fpga configured at all.

My proposal is revert back to its original code, revert socfpga_bridges_reset() return type to void and don't check error from fpgamgr_test_fpga_ready(). So, we can support Gen5 boot without program FPGA.

Quoted 242 lines · Ley Foon Tan

Quoted 239 lines · Dalon Westergreen

Quoted 217 lines · Dalon Westergreen

Quoted 215 lines · Dinh Nguyen

Quoted 198 lines · Dalon Westergreen

Quoted 194 lines · Dalon Westergreen

Quoted 4 lines · Dinh Nguyen

Quoted 63 lines

Really including Dalon

Quoted 61 lines

On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dinguyen@kernel. org>
wrote:
CC: Dalon Westergreen

Quoted 51 lines · Dinh Nguyen

Quoted 44 lines · Ley Foon Tan

Add SPL support for Arria 10.

Quoted 16 lines

Quoted 16 lines

Quoted 4 lines

Quoted 4 lines

Signed-off-by: Tien Fong Chee <tien.fong.chee@inte
l.com>
Signed-off-by: Ley Foon Tan <[email protected]
m>

---

Quoted 17 lines

Quoted 17 lines

 arch/arm/mach-socfpga/spl.c | 72

+++++++++++++++++++++++++++++++++++++++++----

Quoted 121 lines

Quoted 121 lines

Quoted 102 lines

Quoted 102 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index 0064fc8..f4a3cdd 100644

arch/arm/mach-socfpga/spl.c +7 -0

@@ -19,23 +19,32 @@
  #include <asm/arch/sdram.h>
  #include <asm/arch/scu.h>
  #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
  DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)

 static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; static struct scu_registers *scu_regs = (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS; static struct nic301_registers *nic301_regs = (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;

arch/arm/mach-socfpga/spl.c +3 -1

-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =

     (struct socfpga_system_manager
*)SOCFPGA_SYSMGR_ADDRESS;

 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);

-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;
     case 0x2:       /* NAND Flash (1.8V) */

arch/arm/mach-socfpga/spl.c +2 -0

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
  }
  #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
  static void socfpga_nic301_slave_ns(void)
  {
      writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
  #endif
      unsigned long sdram_size;
      unsigned long reg;
+    int ret;
 
      /*
       * First C code to run. Clear fake OCRAM ECC first as

SBE

arch/arm/mach-socfpga/spl.c +5 -1

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
      /* Put everything into reset but L4WD0. */
      socfpga_per_reset_all();
      /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed:
 %d\n",
 ret);
+            hang();
+    }
 

     socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

arch/arm/mach-socfpga/spl.c +0 -0

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 
      /* De-assert reset for peripherals and bridges based

on
handoff
*/
     reset_deassert_peripherals_handoff();
-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed:

Quoted 9 lines

Quoted 3 lines

%d\n",
ret);
+            hang();

If you keep this patch the way it is, this will cause the Atlas
board to
hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to
socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is
failing, because is_fpgamgr_initdone_high() is returning 0.

Dinh

Quoted 8 lines

Quoted 3 lines

i saw it the first go round.  i will test this out this afternoon.

--dalon

i see the exact same thing.  for the c5/a5 devices there is no reason for
init
done to be high since fpga configuration isnt required to boot.

Okay, good! It doesn't happen on the C5 devkit though.

Ley Foon, did you test this on the Arria5?

Quoted 8 lines

Quoted 1 line

Dinh

Odd, init done should not be high without the FPGA configured.  i will try it
on
the c5 board as well to try and figure out why init done is high.

--dalon

I ran this on the c5 socdk and noticed the same behavior as Dinh, then realized
the board was setup to configure the fpga independently of the processor.  When
i change the MSELs on the board to ensure the FPGA is unconfigured the code
fails in the same location where init done is not high.  It is definitely an
expected use case in c5/a5 that uboot can run without the fpga configured at
all.

Quoted 4 lines

My proposal is revert back to its original code, revert socfpga_bridges_reset() return type to void and don't check error from fpgamgr_test_fpga_ready(). So, we can support Gen5 boot without program FPGA.

Isn't the difference between CV/AV and A10 such that the former can boot without programmed FPGA while the later can NOT boot without programmed FPGA ? So this code is A10 specific ?

Quoted 248 lines · Marek Vasut

Quoted 246 lines · Ley Foon Tan

Quoted 228 lines · Dalon Westergreen

Quoted 217 lines · Dalon Westergreen

Quoted 215 lines · Dinh Nguyen

Quoted 198 lines · Dalon Westergreen

Quoted 194 lines · Dalon Westergreen

Quoted 4 lines · Dinh Nguyen

Quoted 63 lines

Really including Dalon

Quoted 61 lines

On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dinguyen@kernel. org>
wrote:
CC: Dalon Westergreen

Quoted 51 lines · Dinh Nguyen

Quoted 44 lines · Ley Foon Tan

Add SPL support for Arria 10.

Quoted 20 lines

Signed-off-by: Tien Fong Chee <tien.fong.chee@inte
l.com>
Signed-off-by: Ley Foon Tan <[email protected]
m>

---

Quoted 17 lines

arch/arm/mach-socfpga/spl.c | 72

+++++++++++++++++++++++++++++++++++++++++----

Quoted 121 lines

Quoted 121 lines

Quoted 102 lines

Quoted 102 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index 0064fc8..f4a3cdd 100644

arch/arm/mach-socfpga/spl.c +11 -2

@@ -19,23 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
     (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
     (struct socfpga_system_manager
 *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;

     case 0x2:       /* NAND Flash (1.8V) */

arch/arm/mach-socfpga/spl.c +2 -0

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
     writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
 #endif
     unsigned long sdram_size;
     unsigned long reg;
+    int ret;
 
     /*
      * First C code to run. Clear fake OCRAM ECC first as

SBE

arch/arm/mach-socfpga/spl.c +5 -1

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
     /* Put everything into reset but L4WD0. */
     socfpga_per_reset_all();
     /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed:
 %d\n",
 ret);
+            hang();
+    }
 

     socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

arch/arm/mach-socfpga/spl.c +0 -0

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 
     /* De-assert reset for peripherals and bridges based

on
handoff
*/

     reset_deassert_peripherals_handoff();

arch/arm/mach-socfpga/spl.c +3 -1

-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed:

Quoted 9 lines

Quoted 3 lines

%d\n",
ret);
+ hang();

If you keep this patch the way it is, this will cause the Atlas
board to
hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to
socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is
failing, because is_fpgamgr_initdone_high() is returning 0.

Dinh

Quoted 8 lines

Quoted 3 lines

i saw it the first go round. i will test this out this afternoon.

--dalon

i see the exact same thing. for the c5/a5 devices there is no reason for
init
done to be high since fpga configuration isnt required to boot.

Okay, good! It doesn't happen on the C5 devkit though.

Ley Foon, did you test this on the Arria5?

Quoted 8 lines

Quoted 1 line

Dinh

Odd, init done should not be high without the FPGA configured. i will try it
on
the c5 board as well to try and figure out why init done is high.

--dalon

Quoted 11 lines

I ran this on the c5 socdk and noticed the same behavior as Dinh, then realized
the board was setup to configure the fpga independently of the processor. When
i change the MSELs on the board to ensure the FPGA is unconfigured the code
fails in the same location where init done is not high. It is definitely an
expected use case in c5/a5 that uboot can run without the fpga configured at
all.

My proposal is revert back to its original code, revert socfpga_bridges_reset() return type to void and don't check error from fpgamgr_test_fpga_ready(). So, we can support Gen5 boot without program FPGA.

Quoted 3 lines

Isn't the difference between CV/AV and A10 such that the former can boot without programmed FPGA while the later can NOT boot without programmed FPGA ? So this code is A10 specific ?

Yes, at a minimum in A10 the IO ring needs to be configured prior to boot.

Since these functions (socfpga_bridges_reset) are different for c5/a5 and a10,
i would suggest changing the code to enable the bridges IF the fpga is configured. perhaps just:

...

        } else {                                                                
                writel(0, &sysmgr_regs->iswgrp_handoff[0]);                     
                writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);                
                                                                                
                /* Check signal from FPGA. */                                   
                if (!fpgamgr_test_fpga_ready()) {                               
                       /* brdmodrst */                                          
      			writel(0, &reset_manager_base->brg_mod_reset);             
                }                                                               

...

I think this actually mirrors the behavior of the 2013.01.01 fork where if the fpga is configured, spl enables the bridges.

--dalon

Quoted 289 lines · Dalon Westergreen

Quoted 287 lines · Marek Vasut

Quoted 284 lines · Ley Foon Tan

Quoted 263 lines · Dalon Westergreen

Quoted 252 lines · Dalon Westergreen

Quoted 243 lines · Dinh Nguyen

Quoted 231 lines · Dalon Westergreen

Quoted 226 lines · Dalon Westergreen

Quoted 5 lines · Dinh Nguyen

Quoted 77 lines

Really including Dalon

Quoted 75 lines

On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dinguyen@ker nel.
org>
wrote:
CC: Dalon Westergreen

Quoted 63 lines · Dinh Nguyen

Quoted 55 lines · Ley Foon Tan

Add SPL support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@
inte
l.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@inte
l.co
m>
---

 arch/arm/mach-socfpga/spl.c | 72

+++++++++++++++++++++++++++++++++++++++++----

Quoted 133 lines

Quoted 133 lines

Quoted 113 lines

Quoted 113 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

diff --git a/arch/arm/mach-socfpga/spl.c
b/arch/arm/mach-
socfpga/spl.c
index 0064fc8..f4a3cdd 100644
--- a/arch/arm/mach-socfpga/spl.c
+++ b/arch/arm/mach-socfpga/spl.c
@@ -19,23 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif

 DECLARE_GLOBAL_DATA_PTR;

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
     (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
     (struct nic301_registers
*)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager
*sysmgr_regs =
     (struct socfpga_system_manager
*)SOCFPGA_SYSMGR_ADDRESS;

 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);

-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;
     case 0x2:       /* NAND Flash (1.8V) */
@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32
boot_device)
 }
 #endif

+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
     writel(0x1, &nic301_regs->lwhps2fpgaregs);
@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
 #endif
     unsigned long sdram_size;
     unsigned long reg;
+    int ret;

     /*
      * First C code to run. Clear fake OCRAM ECC
first as
SBE
@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
     /* Put everything into reset but L4WD0. */
     socfpga_per_reset_all();
     /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed:
%d\n",
ret);
+            hang();
+    }

     socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)

     /* De-assert reset for peripherals and bridges
based
on
handoff
*/
     reset_deassert_peripherals_handoff();
-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed:
%d\n",

Quoted 9 lines

Quoted 2 lines

ret);
+            hang();

If you keep this patch the way it is, this will cause the
Atlas
board to
hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the
call to
socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is
failing, because is_fpgamgr_initdone_high() is returning 0.

Quoted 1 line

Quoted 1 line

Dinh

i saw it the first go round.  i will test this out this afternoon.

Quoted 6 lines

Quoted 1 line

--dalon

i see the exact same thing.  for the c5/a5 devices there is no reason for
init
done to be high since fpga configuration isnt required to boot.

Quoted 5 lines

Okay, good! It doesn't happen on the C5 devkit though.

Ley Foon, did you test this on the Arria5?

Dinh

Quoted 7 lines

Odd, init done should not be high without the FPGA configured.  i will
try it
on
the c5 board as well to try and figure out why init done is high.

--dalon

Quoted 13 lines

I ran this on the c5 socdk and noticed the same behavior as Dinh, then realized
the board was setup to configure the fpga independently of the processor.  When
i change the MSELs on the board to ensure the FPGA is unconfigured the code
fails in the same location where init done is not high.  It is definitely
an
expected use case in c5/a5 that uboot can run without the fpga configured
at
all.

My proposal is revert back to its original code, revert socfpga_bridges_reset() return type to void and don't check error from fpgamgr_test_fpga_ready(). So, we can support Gen5 boot without program FPGA.

Quoted 5 lines

Quoted 3 lines

Isn't the difference between CV/AV and A10 such that the former can boot without programmed FPGA while the later can NOT boot without programmed FPGA ? So this code is A10 specific ?

Yes, at a minimum in A10 the IO ring needs to be configured prior to boot.

We do the IOCSR configuration on C5/A5 too, so what's the difference ?

Quoted 5 lines

 Since these functions (socfpga_bridges_reset) are different for c5/a5 and a10,
i would suggest changing the code to enable the bridges IF the fpga is configured.  perhaps just:

If it works ... fine.

Quoted 24 lines

...
        } else
{
                writel(0, &sysmgr_regs-

Quoted 1 line

iswgrp_handoff[0]);

                writel(l3mask, &sysmgr_regs-

Quoted 1 line

iswgrp_handoff[1]);

                /* Check signal from FPGA.
*/
                if (!fpgamgr_test_fpga_ready()) {
                       /* brdmodrst
*/
       writel(0, &reset_manager_base-

Quoted 1 line

brg_mod_reset);

                }



...

Quoted 3 lines

I think this actually mirrors the behavior of the 2013.01.01 fork where if the
fpga is configured, spl enables the bridges.

Super :)

Quoted 3 lines

--dalon

Quoted 9 lines

Quoted 9 lines

Quoted 8 lines

Quoted 4 lines

My proposal is revert back to its original code, revert socfpga_bridges_reset() return type to void and don't check error from fpgamgr_test_fpga_ready(). So, we can support Gen5 boot without program FPGA.

Isn't the difference between CV/AV and A10 such that the former can boot without programmed FPGA while the later can NOT boot without programmed FPGA ? So this code is A10 specific ?

Quoted 4 lines

Quoted 1 line

Yes, at a minimum in A10 the IO ring needs to be configured prior to boot.

We do the IOCSR configuration on C5/A5 too, so what's the difference ?

in c5/a5 the iocsr config is done directly, the iocsr data is compiled into spl, for a10 this is all done by the fpga bitstream, there is no direct iocsr config.

Quoted 43 lines

Quoted 5 lines

Since these functions (socfpga_bridges_reset) are different for c5/a5 and
a10,
i would suggest changing the code to enable the bridges IF the fpga is configured. perhaps just:

If it works ... fine.

Quoted 22 lines

...

        } else
{                                                                
                writel(0, &sysmgr_regs-

Quoted 1 line

iswgrp_handoff[0]);

writel(l3mask, &sysmgr_regs-

Quoted 1 line

iswgrp_handoff[1]);

                /* Check signal from FPGA.
*/                                   
                if (!fpgamgr_test_fpga_ready())
{                               
                       /* brdmodrst

*/
writel(0, &reset_manager_base-

Quoted 1 line

brg_mod_reset);

                }                                                           

Quoted 5 lines

...

I think this actually mirrors the behavior of the 2013.01.01 fork where if the
fpga is configured, spl enables the bridges.

Super :)

Quoted 3 lines

--dalon

Quoted 243 lines · Marek Vasut

Quoted 242 lines · Ley Foon Tan

Quoted 239 lines · Dalon Westergreen

Quoted 217 lines · Dalon Westergreen

Quoted 215 lines · Dinh Nguyen

Quoted 198 lines · Dalon Westergreen

Quoted 194 lines · Dalon Westergreen

Quoted 4 lines · Dinh Nguyen

Quoted 63 lines

Really including Dalon

Quoted 61 lines

On Wed, Apr 19, 2017 at 3:26 PM, Dinh Nguyen <dinguyen@kernel. org>
wrote:
CC: Dalon Westergreen

Quoted 51 lines · Dinh Nguyen

Quoted 44 lines · Ley Foon Tan

Add SPL support for Arria 10.

Quoted 20 lines

Signed-off-by: Tien Fong Chee <tien.fong.chee@inte
l.com>
Signed-off-by: Ley Foon Tan <[email protected]
m>

---

Quoted 17 lines

arch/arm/mach-socfpga/spl.c | 72

+++++++++++++++++++++++++++++++++++++++++----

Quoted 121 lines

Quoted 121 lines

Quoted 102 lines

Quoted 102 lines

 1 file changed, 67 insertions(+), 5 deletions(-)

arch/arm/mach- renamed from arch/arm/mach-socfpga/spl.c +0 -0

socfpga/spl.c
index 0064fc8..f4a3cdd 100644

arch/arm/mach-socfpga/spl.c +11 -2

@@ -19,23 +19,32 @@
 #include <asm/arch/sdram.h>
 #include <asm/arch/scu.h>
 #include <asm/arch/nic301.h>
+#include <asm/sections.h>
+#include <fdtdec.h>
+#include <watchdog.h>
+#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/pinmux.h>
+#endif
 
 DECLARE_GLOBAL_DATA_PTR;
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static struct pl310_regs *const pl310 =
     (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
 static struct scu_registers *scu_regs =
     (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
 static struct nic301_registers *nic301_regs =
     (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
+#endif
+
+static const struct socfpga_system_manager *sysmgr_regs =
     (struct socfpga_system_manager
 *)SOCFPGA_SYSMGR_ADDRESS;
 
 u32 spl_boot_device(void)
 {
     const u32 bsel = readl(&sysmgr_regs->bootinfo);
 
-    switch (bsel & 0x7) {
+    switch (SYSMGR_GET_BOOTINFO_BSEL(bsel)) {
     case 0x1:       /* FPGA (HPS2FPGA Bridge) */
             return BOOT_DEVICE_RAM;

     case 0x2:       /* NAND Flash (1.8V) */

arch/arm/mach-socfpga/spl.c +2 -0

@@ -68,6 +77,7 @@ u32 spl_boot_mode(const u32 boot_device)
 }
 #endif
 
+#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 static void socfpga_nic301_slave_ns(void)
 {
     writel(0x1, &nic301_regs->lwhps2fpgaregs);

@@ -85,6 +95,7 @@ void board_init_f(ulong dummy)
 #endif
     unsigned long sdram_size;
     unsigned long reg;
+    int ret;
 
     /*
      * First C code to run. Clear fake OCRAM ECC first as

SBE

arch/arm/mach-socfpga/spl.c +5 -1

@@ -117,7 +128,11 @@ void board_init_f(ulong dummy)
     /* Put everything into reset but L4WD0. */
     socfpga_per_reset_all();
     /* Put FPGA bridges into reset too. */
-    socfpga_bridges_reset(1);
+    ret = socfpga_bridges_reset(1);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed:
 %d\n",
 ret);
+            hang();
+    }
 

     socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
     socfpga_per_reset(SOCFPGA_RESET(UART0), 0);

arch/arm/mach-socfpga/spl.c +0 -0

@@ -148,7 +163,11 @@ void board_init_f(ulong dummy)
 
     /* De-assert reset for peripherals and bridges based

on
handoff
*/

     reset_deassert_peripherals_handoff();

arch/arm/mach-socfpga/spl.c +3 -1

-    socfpga_bridges_reset(0);
+    ret = socfpga_bridges_reset(0);
+    if (ret) {
+            printf("socfpga_bridges_reset() failed:

Quoted 9 lines

Quoted 3 lines

%d\n",
ret);
+ hang();

If you keep this patch the way it is, this will cause the Atlas
board to
hang here.

Hi Dalon,

Can you check this patch? On the Atlas board, I'm seeing the call to
socfpga_bridges_reset(0) fail because fpgamgr_test_fpga_ready() is
failing, because is_fpgamgr_initdone_high() is returning 0.

Dinh

Quoted 8 lines

Quoted 3 lines

i saw it the first go round. i will test this out this afternoon.

--dalon

i see the exact same thing. for the c5/a5 devices there is no reason for
init
done to be high since fpga configuration isnt required to boot.

Okay, good! It doesn't happen on the C5 devkit though.

Ley Foon, did you test this on the Arria5?

Quoted 8 lines

Quoted 1 line

Dinh

Odd, init done should not be high without the FPGA configured. i will try it
on
the c5 board as well to try and figure out why init done is high.

--dalon

I ran this on the c5 socdk and noticed the same behavior as Dinh, then realized
the board was setup to configure the fpga independently of the processor. When
i change the MSELs on the board to ensure the FPGA is unconfigured the code
fails in the same location where init done is not high. It is definitely an
expected use case in c5/a5 that uboot can run without the fpga configured at
all.

Quoted 8 lines

Quoted 4 lines

My proposal is revert back to its original code, revert socfpga_bridges_reset() return type to void and don't check error from fpgamgr_test_fpga_ready(). So, we can support Gen5 boot without program FPGA.

Isn't the difference between CV/AV and A10 such that the former can boot without programmed FPGA while the later can NOT boot without programmed FPGA ? So this code is A10 specific ?

Yes, at a minimum in A10 the IO ring needs to be configured prior to boot.
Since these functions (socfpga_bridges_reset) are different for c5/a5 and a10,
i would suggest changing the code to enable the bridges IF the fpga is configured. perhaps just:

...

        } else {
                writel(0, &sysmgr_regs->iswgrp_handoff[0]);
                writel(l3mask, &sysmgr_regs->iswgrp_handoff[1]);

                /* Check signal from FPGA. */
                if (!fpgamgr_test_fpga_ready()) {
                       /* brdmodrst */
                        writel(0, &reset_manager_base->brg_mod_reset);
                }

...

I think this actually mirrors the behavior of the 2013.01.01 fork where if the fpga is configured, spl enables the bridges.

This is the 6th version of patchset to adds support for Intel Arria 10 SoC. This is initial patchset enables the basic support for Arria 10 and other features will come after this.

There is only one minor change in patch #5.

This series is rebased on top of http://git.denx.de/?p=u-boot/u-boot-socfpga.git.

v5 -> v6 changes:
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- macros sorted by address