Add support for Broadcom MIPS SoCs

Add a new sysreset driver based on linux/drivers/power/reset/syscon-reboot.c, which provides a generic driver for platforms that only require writing a mask to a regmap offset.

Signed-off-by Álvaro Fernández Rojas <[email protected]>

Reviewed-by Simon Glass <[email protected]>

---
v5: No chnages.
v4: Rebased.
v3: Introduce changes suggested by Simon Glass:
- Add missing driver description.
- Alphabetically order includes.
- Add priv struct to store regmap during probe.
- Cosmetic fixes.
v2: No changes.

 drivers/sysreset/Kconfig           |  8 ++++
 drivers/sysreset/Makefile          |  1 +
 drivers/sysreset/sysreset_syscon.c | 76 ++++++++++++++++++++++++++++++++++++++
 3 files changed, 85 insertions(+)
 create mode 100644 drivers/sysreset/sysreset_syscon.c

drivers/sysreset/Kconfig +8 -0

index 9664630..b2f7464 100644
@@ -23,4 +23,12 @@ config SYSRESET_PSCI
 	  must be running on your system.
 
 endif
+
+config SYSRESET_SYSCON
+	bool "Enable support for mfd syscon reboot driver"
+	select REGMAP
+	select SYSCON
+	help
+	  Reboot support for generic SYSCON mapped register reset.
+
 endmenu

drivers/sysreset/Makefile +1 -0

index 7bb8406..bd352e7 100644
@@ -6,6 +6,7 @@
 
 obj-$(CONFIG_SYSRESET) += sysreset-uclass.o
 obj-$(CONFIG_SYSRESET_PSCI) += sysreset_psci.o
+obj-$(CONFIG_SYSRESET_SYSCON) += sysreset_syscon.o
 
 ifndef CONFIG_SPL_BUILD
 obj-$(CONFIG_ROCKCHIP_RK3036) += sysreset_rk3036.o

drivers/sysreset/sysreset_syscon.c new file +49 -0

new file mode 100644
index 0000000..adfddb4
@@ -0,0 +1,76 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * Derived from linux/drivers/power/reset/syscon-reboot.c:
+ *	Copyright (C) 2013, Applied Micro Circuits Corporation
+ *	Author: Feng Kan <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <regmap.h>
+#include <sysreset.h>
+#include <syscon.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct syscon_reboot_priv {
+	struct regmap *regmap;
+	unsigned int offset;
+	unsigned int mask;
+};
+
+static int syscon_reboot_request(struct udevice *dev, enum sysreset_t type)
+{
+	struct syscon_reboot_priv *priv = dev_get_priv(dev);
+
+	regmap_write(priv->regmap, priv->offset, priv->mask);
+
+	return -EINPROGRESS;
+}
+
+static struct sysreset_ops syscon_reboot_ops = {
+	.request = syscon_reboot_request,
+};
+
+int syscon_reboot_probe(struct udevice *dev)
+{
+	struct udevice *syscon;
+	struct syscon_reboot_priv *priv = dev_get_priv(dev);
+	int err;
+
+	err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev,
+					   "regmap", &syscon);
+	if (err) {
+		error("unable to find syscon device\n");
+		return err;

drivers/sysreset/sysreset_syscon.c new file +17 -0

+
+	return 0;
+}
+
+static const struct udevice_id syscon_reboot_ids[] = {
+	{ .compatible = "syscon-reboot" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(syscon_reboot) = {
+	.name = "syscon_reboot",
+	.id = UCLASS_SYSRESET,
+	.of_match = syscon_reboot_ids,
+	.probe = syscon_reboot_probe,
+	.priv_auto_alloc_size = sizeof(struct syscon_reboot_priv),
+	.ops = &syscon_reboot_ops,
+};

It is based on linux/drivers/tty/serial/bcm63xx_uart.c

Signed-off-by Álvaro Fernández Rojas <[email protected]>

---
v5: No changes.
v4: Add more missing register configurations based on CFE.
v3: Several improvements:
- Add missing register configurations based on CFE.
- Replace tabs with whitespaces.
- Cosmetic fixes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Remove unneeded defines.
- Fix incorrect multi-line comment.

 drivers/serial/Kconfig          |  14 ++
 drivers/serial/Makefile         |   1 +
 drivers/serial/serial_bcm6345.c | 311 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 326 insertions(+)
 create mode 100644 drivers/serial/serial_bcm6345.c

drivers/serial/Kconfig +8 -0

index c0ec2ec..ca776d8 100644
@@ -134,6 +134,14 @@ config DEBUG_UART_ATMEL
 	  will need to provide parameters to make this work. The driver will
 	  be available until the real driver-model serial is running.
 
+config DEBUG_UART_BCM6345
+	bool "BCM6345 UART"
+	depends on BCM6345_SERIAL
+	help
+	  Select this to enable a debug UART on BCM6345 SoCs. You
+	  will need to provide parameters to make this work. The driver will
+	  be available until the real driver model serial is running.
+
 config DEBUG_UART_NS16550
 	bool "ns16550"
 	help

drivers/serial/Kconfig +3 -0

+	help
+	  Select this to enable UART on BCM6345 SoCs.
+
 config FSL_LPUART
 	bool "Freescale LPUART support"
 	help

drivers/serial/Makefile +1 -0

index 4382cf9..dca31b2 100644
@@ -20,6 +20,7 @@ obj-$(CONFIG_ALTERA_JTAG_UART) += altera_jtag_uart.o
 obj-$(CONFIG_AR933X_UART) += serial_ar933x.o
 obj-$(CONFIG_ARM_DCC) += arm_dcc.o
 obj-$(CONFIG_ATMEL_USART) += atmel_usart.o
+obj-$(CONFIG_BCM6345_SERIAL) += serial_bcm6345.o
 obj-$(CONFIG_EFI_APP) += serial_efi.o
 obj-$(CONFIG_LPC32XX_HSUART) += lpc32xx_hsuart.o
 obj-$(CONFIG_MCFUART) += mcfuart.o

drivers/serial/serial_bcm6345.c new file +85 -0

new file mode 100644
index 0000000..e4d3497
@@ -0,0 +1,311 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * Derived from linux/drivers/tty/serial/bcm63xx_uart.c:
+ *	Copyright (C) 2008 Maxime Bizon <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <clk.h>
+#include <debug_uart.h>
+#include <errno.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/types.h>
+#include <dm/device.h>
+
+/* UART Control register */
+#define UART_CTL_REG			0x0
+#define UART_CTL_RXTIMEOUT_MASK		0x1f
+#define UART_CTL_RSTRXFIFO_SHIFT	6
+#define UART_CTL_RSTRXFIFO_MASK		(1 << UART_CTL_RSTRXFIFO_SHIFT)
+#define UART_CTL_RSTTXFIFO_SHIFT	7
+#define UART_CTL_RSTTXFIFO_MASK		(1 << UART_CTL_RSTTXFIFO_SHIFT)
+#define UART_CTL_STOPBITS_SHIFT		8
+#define UART_CTL_STOPBITS_MASK		(0xf << UART_CTL_STOPBITS_SHIFT)
+#define UART_CTL_STOPBITS_1		(0x7 << UART_CTL_STOPBITS_SHIFT)
+#define UART_CTL_BITSPERSYM_SHIFT	12
+#define UART_CTL_BITSPERSYM_MASK	(0x3 << UART_CTL_BITSPERSYM_SHIFT)
+#define UART_CTL_XMITBRK_SHIFT		14
+#define UART_CTL_XMITBRK_MASK		(1 << UART_CTL_XMITBRK_SHIFT)
+#define UART_CTL_RSVD_SHIFT		15
+#define UART_CTL_RSVD_MASK		(1 << UART_CTL_RSVD_SHIFT)
+#define UART_CTL_RXPAREVEN_SHIFT	16
+#define UART_CTL_RXPAREVEN_MASK		(1 << UART_CTL_RXPAREVEN_SHIFT)
+#define UART_CTL_RXPAREN_SHIFT		17
+#define UART_CTL_RXPAREN_MASK		(1 << UART_CTL_RXPAREN_SHIFT)
+#define UART_CTL_TXPAREVEN_SHIFT	18
+#define UART_CTL_TXPAREVEN_MASK		(1 << UART_CTL_TXPAREVEN_SHIFT)
+#define UART_CTL_TXPAREN_SHIFT		19
+#define UART_CTL_TXPAREN_MASK		(1 << UART_CTL_TXPAREN_SHIFT)
+#define UART_CTL_LOOPBACK_SHIFT		20
+#define UART_CTL_LOOPBACK_MASK		(1 << UART_CTL_LOOPBACK_SHIFT)
+#define UART_CTL_RXEN_SHIFT		21
+#define UART_CTL_RXEN_MASK		(1 << UART_CTL_RXEN_SHIFT)
+#define UART_CTL_TXEN_SHIFT		22
+#define UART_CTL_TXEN_MASK		(1 << UART_CTL_TXEN_SHIFT)
+#define UART_CTL_BRGEN_SHIFT		23
+#define UART_CTL_BRGEN_MASK		(1 << UART_CTL_BRGEN_SHIFT)
+
+/* UART Baudword register */
+#define UART_BAUD_REG			0x4
+
+/* UART FIFO Config register */
+#define UART_FIFO_CFG_REG		0x8
+#define UART_FIFO_CFG_RX_SHIFT		8
+#define UART_FIFO_CFG_RX_MASK		(0xf << UART_FIFO_CFG_RX_SHIFT)
+#define UART_FIFO_CFG_TX_SHIFT		12
+#define UART_FIFO_CFG_TX_MASK		(0xf << UART_FIFO_CFG_TX_SHIFT)
+
+/* UART Interrupt register */
+#define UART_IR_REG			0x10
+#define UART_IR_STAT(x)			(1 << (x))
+#define UART_IR_TXEMPTY			5
+#define UART_IR_RXOVER			7
+#define UART_IR_RXNOTEMPTY		11
+
+/* UART FIFO register */
+#define UART_FIFO_REG			0x14
+#define UART_FIFO_VALID_MASK		0xff
+#define UART_FIFO_FRAMEERR_SHIFT	8
+#define UART_FIFO_FRAMEERR_MASK		(1 << UART_FIFO_FRAMEERR_SHIFT)
+#define UART_FIFO_PARERR_SHIFT		9
+#define UART_FIFO_PARERR_MASK		(1 << UART_FIFO_PARERR_SHIFT)
+#define UART_FIFO_BRKDET_SHIFT		10
+#define UART_FIFO_BRKDET_MASK		(1 << UART_FIFO_BRKDET_SHIFT)
+#define UART_FIFO_ANYERR_MASK		(UART_FIFO_FRAMEERR_MASK |	\
+					UART_FIFO_PARERR_MASK |		\
+					UART_FIFO_BRKDET_MASK)
+
+struct bcm6345_serial_priv {
+	void __iomem *base;
+	ulong uartclk;
+};
+

drivers/serial/serial_bcm6345.c new file +128 -0

+}
+
+/*
+ * disable rx & tx operation on uart
+ */
+static void bcm6345_serial_disable(void __iomem *base)
+{
+	u32 val;
+
+	val = __raw_readl(base + UART_CTL_REG);
+	val &= ~(UART_CTL_BRGEN_MASK | UART_CTL_TXEN_MASK |
+		 UART_CTL_RXEN_MASK);
+	__raw_writel(val, base + UART_CTL_REG);
+}
+
+/*
+ * clear all unread data in rx fifo and unsent data in tx fifo
+ */
+static void bcm6345_serial_flush(void __iomem *base)
+{
+	u32 val;
+
+	/* empty rx and tx fifo */
+	val = __raw_readl(base + UART_CTL_REG);
+	val |= UART_CTL_RSTRXFIFO_MASK | UART_CTL_RSTTXFIFO_MASK;
+	__raw_writel(val, base + UART_CTL_REG);
+
+	/* read any pending char to make sure all irq status are cleared */
+	__raw_readl(base + UART_FIFO_REG);
+}
+
+static int bcm6345_serial_init(void __iomem *base, ulong clk, u32 baudrate)
+{
+	u32 val;
+
+	/* mask all irq and flush port */
+	bcm6345_serial_disable(base);
+	bcm6345_serial_flush(base);
+
+	val = __raw_readl(base + UART_CTL_REG);
+	/* set rx timeout */
+	val &= ~UART_CTL_RXTIMEOUT_MASK;
+	val |= 0x5;
+	/* set stop bits */
+	val &= ~UART_CTL_STOPBITS_MASK;
+	val |= UART_CTL_STOPBITS_1;
+	/* set bits per symbol */
+	val &= ~UART_CTL_BITSPERSYM_MASK;
+	val |= (3 << UART_CTL_BITSPERSYM_SHIFT);
+	/* clear xmit break */
+	val &= ~UART_CTL_XMITBRK_MASK;
+	/* clear reserved bit */
+	val &= ~UART_CTL_RSVD_MASK;
+	/* disable parity */
+	val |= UART_CTL_RXPAREVEN_MASK | UART_CTL_TXPAREVEN_MASK;
+	val &= ~(UART_CTL_RXPAREN_MASK | UART_CTL_TXPAREN_MASK);
+	/* disable loopback */
+	val &= ~UART_CTL_LOOPBACK_MASK;
+	__raw_writel(val, base + UART_CTL_REG);
+
+	val = __raw_readl(base + UART_FIFO_CFG_REG);
+	/* set rx fifo config */
+	val &= ~UART_FIFO_CFG_RX_MASK;
+	val |= (4 << UART_FIFO_CFG_RX_SHIFT);
+	/* set tx fifo config */
+	val &= ~UART_FIFO_CFG_TX_MASK;
+	val |= (4 << UART_FIFO_CFG_TX_SHIFT);
+	__raw_writel(val, base + UART_FIFO_CFG_REG);
+
+	/* set baud rate */
+	val = (clk / baudrate) / 16;
+	if (val & 0x1)
+		val = val;
+	else
+		val = val / 2 - 1;
+	__raw_writel(val, base + UART_BAUD_REG);
+
+	/* clear interrupts */
+	__raw_writel(0, base + UART_IR_REG);
+
+	/* enable uart */
+	bcm6345_serial_enable(base);
+
+	return 0;
+}
+
+static int bcm6345_serial_pending(struct udevice *dev, bool input)
+{
+	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
+	u32 val = __raw_readl(priv->base + UART_IR_REG);
+
+	if (input)
+		return (val & UART_IR_STAT(UART_IR_RXNOTEMPTY)) ? 1 : 0;
+	else
+		return (val & UART_IR_STAT(UART_IR_TXEMPTY)) ? 0 : 1;
+}
+
+static int bcm6345_serial_setbrg(struct udevice *dev, int baudrate)
+{
+	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
+
+	return bcm6345_serial_init(priv->base, priv->uartclk, baudrate);
+}
+
+static int bcm6345_serial_putc(struct udevice *dev, const char ch)
+{
+	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
+	u32 val;
+
+	val = __raw_readl(priv->base + UART_IR_REG);
+	if (!(val & UART_IR_STAT(UART_IR_TXEMPTY)))
+		return -EAGAIN;
+
+	__raw_writel(ch, priv->base + UART_FIFO_REG);
+
+	return 0;
+}
+
+static int bcm6345_serial_getc(struct udevice *dev)
+{
+	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
+	u32 val;
+
+	val = __raw_readl(priv->base + UART_IR_REG);
+	if (val & UART_IR_STAT(UART_IR_RXOVER)) {
+		/* fifo reset is required to clear interrupt */
+		val = __raw_readl(priv->base + UART_CTL_REG);
+		val |= UART_CTL_RSTRXFIFO_MASK;

drivers/serial/serial_bcm6345.c new file +78 -0

+}
+
+static int bcm6345_serial_probe(struct udevice *dev)
+{
+	struct bcm6345_serial_priv *priv = dev_get_priv(dev);
+	struct clk clk;
+	fdt_addr_t addr;
+	fdt_size_t size;
+	int ret;
+
+	/* get address */
+	addr = dev_get_addr_size_index(dev, 0, &size);
+	if (addr == FDT_ADDR_T_NONE)
+		return -EINVAL;
+
+	priv->base = ioremap(addr, size);
+
+	/* get clock rate */
+	ret = clk_get_by_index(dev, 0, &clk);
+	if (ret < 0)
+		return ret;
+	priv->uartclk = clk_get_rate(&clk) / 2;
+	clk_free(&clk);
+
+	/* initialize serial */
+	return bcm6345_serial_init(priv->base, priv->uartclk, CONFIG_BAUDRATE);
+}
+
+static const struct dm_serial_ops bcm6345_serial_ops = {
+	.putc = bcm6345_serial_putc,
+	.pending = bcm6345_serial_pending,
+	.getc = bcm6345_serial_getc,
+	.setbrg = bcm6345_serial_setbrg,
+};
+
+static const struct udevice_id bcm6345_serial_ids[] = {
+	{ .compatible = "brcm,bcm6345-uart" },
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(bcm6345_serial) = {
+	.name = "bcm6345-uart",
+	.id = UCLASS_SERIAL,
+	.of_match = bcm6345_serial_ids,
+	.probe = bcm6345_serial_probe,
+	.priv_auto_alloc_size = sizeof(struct bcm6345_serial_priv),
+	.ops = &bcm6345_serial_ops,
+	.flags = DM_FLAG_PRE_RELOC,
+};
+
+#ifdef CONFIG_DEBUG_UART_BCM6345
+static inline void _debug_uart_init(void)
+{
+	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+
+	bcm6345_serial_init(base, CONFIG_DEBUG_UART_CLOCK, CONFIG_BAUDRATE);
+}
+
+static inline void wait_xfered(void __iomem *base)
+{
+	do {
+		u32 val = __raw_readl(base + UART_IR_REG);
+		if (val & UART_IR_STAT(UART_IR_TXEMPTY))
+			break;
+	} while (1);
+}
+
+static inline void _debug_uart_putc(int ch)
+{
+	void __iomem *base = (void __iomem *)CONFIG_DEBUG_UART_BASE;
+
+	wait_xfered(base);
+	__raw_writel(ch, base + UART_FIFO_REG);
+	wait_xfered(base);
+}
+
+DEBUG_UART_FUNCS
+#endif

Use uclass_first_device and uclass_next_device in order to avoid exceptions for drivers that aren't probed when cpu ops are requested. Improve code style and fix indentations.
Fix incorrect line break when cpu info is not available.
Remove unneeded brackets.

Signed-off-by Álvaro Fernández Rojas <[email protected]>

---
v5: No changes.
v4: Refactor code to use uclass_first_device and uclass_next_device as
requested by Simon Glass.
v3: add new patch to ensure that device is probed.

 cmd/cpu.c | 30 +++++++++++++-----------------
 1 file changed, 13 insertions(+), 17 deletions(-)

Signed-off-by Álvaro Fernández Rojas <[email protected]>

---
v5: Add specific desc functions.
v4: No changes.
v3: Several improvements:
- Probe driver correctly.
- Allocate size for priv struct.
- Cosmetic fixes.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Get register base from DT.

 drivers/cpu/Makefile    |   2 +
 drivers/cpu/bmips_cpu.c | 310 ++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 312 insertions(+)
 create mode 100644 drivers/cpu/bmips_cpu.c

CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop

Signed-off-by Álvaro Fernández Rojas <[email protected]>

---
v4: No changes.
v5: No changes.
v3: Select CONFIG_REMAKE_ELF.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Replace initdram with dram_init.
- Merge with "fix first CPU check" patch.

 arch/mips/Kconfig              | 10 ++++++++++
 arch/mips/Makefile             |  1 +
 arch/mips/cpu/start.S          |  5 +++++
 arch/mips/mach-bmips/Kconfig   | 22 ++++++++++++++++++++++
 arch/mips/mach-bmips/Makefile  |  5 +++++
 arch/mips/mach-bmips/dram.c    | 37 +++++++++++++++++++++++++++++++++++++
 include/configs/bmips_common.h | 27 +++++++++++++++++++++++++++
 7 files changed, 107 insertions(+)
 create mode 100644 arch/mips/mach-bmips/Kconfig
 create mode 100644 arch/mips/mach-bmips/Makefile
 create mode 100644 arch/mips/mach-bmips/dram.c
 create mode 100644 include/configs/bmips_common.h

arch/mips/Kconfig +10 -0

index d97930e..c97ea41 100644
@@ -75,6 +75,15 @@ config ARCH_ATH79
 	select OF_CONTROL
 	select DM
 
+config ARCH_BMIPS
+	bool "Support BMIPS SoCs"
+	select OF_CONTROL
+	select DM
+	select CLK
+	select CPU
+	select RAM
+	select SYSRESET
+
 config MACH_PIC32
 	bool "Support Microchip PIC32"
 	select OF_CONTROL

@@ -123,6 +132,7 @@ source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-bmips/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS

arch/mips/Makefile +1 -0

index efe7e44..c30d4ef 100644
@@ -15,6 +15,7 @@ libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
 machine-$(CONFIG_ARCH_ATH79) += ath79
+machine-$(CONFIG_ARCH_BMIPS) += bmips
 machine-$(CONFIG_MACH_PIC32) += pic32
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))

arch/mips/cpu/start.S +5 -0

index f7dee81..5c1ad00 100644
@@ -151,8 +151,13 @@ reset:
 	 mfc0	t0, CP0_GLOBALNUMBER
 #endif
 
+#ifdef CONFIG_ARCH_BMIPS
+1:	mfc0	t0, CP0_DIAGNOSTIC, 3
+	and	t0, t0, (1 << 31)
+#else
 1:	mfc0	t0, CP0_EBASE
 	and	t0, t0, EBASE_CPUNUM
+#endif
 
 	/* Hang if this isn't the first CPU in the system */
 2:	beqz	t0, 4f

arch/mips/mach-bmips/Kconfig new file +5 -0

new file mode 100644
index 0000000..42a7e41
@@ -0,0 +1,22 @@
+menu "Broadcom MIPS platforms"
+	depends on ARCH_BMIPS
+
+config SYS_SOC
+	default "none"

arch/mips/mach-bmips/Kconfig new file +7 -0

+
+endchoice
+
+config BMIPS_SUPPORTS_BOOT_RAM
+	bool
+
+endmenu

arch/mips/mach-bmips/Makefile new file +5 -0

new file mode 100644
index 0000000..f432acc
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += dram.o

arch/mips/mach-bmips/dram.c new file +37 -0

new file mode 100644
index 0000000..b19b28a
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2016 Daniel Schwierzeck <[email protected]>
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
+#include <ram.h>
+#include <dm.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	struct ram_info ram;
+	struct udevice *dev;
+	int err;
+
+	err = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (err) {
+		debug("DRAM init failed: %d\n", err);
+		return 0;
+	}
+
+	err = ram_get_info(dev, &ram);
+	if (err) {
+		debug("Cannot get DRAM size: %d\n", err);
+		return 0;
+	}
+
+	debug("SDRAM base=%zx, size=%x\n", ram.base, ram.size);
+
+	gd->ram_size = ram.size;
+
+	return 0;
+}

include/configs/bmips_common.h new file +27 -0

new file mode 100644
index 0000000..3d67729
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_COMMON_H
+#define __CONFIG_BMIPS_COMMON_H
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START	0xa0000000
+#define CONFIG_SYS_MEMTEST_END		0xa2000000
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+#define CONFIG_SYS_CBSIZE		512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_REMAKE_ELF
+
+#endif /* __CONFIG_BMIPS_COMMON_H */

CFE checks CPU Thread in a different way (using register $22):
mfc0 t1, C0_BCM_CONFIG, 3 # $22
li t2, CP0_CMT_TPID # (1 << 31)
and t1, t2
bnez t1, 2f # if we are running on thread 1, skip init
nop

Signed-off-by Álvaro Fernández Rojas

---
v4: No changes.
v5: No changes.
v3: Select CONFIG_REMAKE_ELF.
v2: Introduce changes suggested by Daniel Schwierzeck:
- Split BMIPS support patches.
- Replace initdram with dram_init.
- Merge with "fix first CPU check" patch.

 arch/mips/Kconfig              | 10 ++++++++++
 arch/mips/Makefile             |  1 +
 arch/mips/cpu/start.S          |  5 +++++
 arch/mips/mach-bmips/Kconfig   | 22 ++++++++++++++++++++++
 arch/mips/mach-bmips/Makefile  |  5 +++++
 arch/mips/mach-bmips/dram.c    | 37 +++++++++++++++++++++++++++++++++++++
 include/configs/bmips_common.h | 27 +++++++++++++++++++++++++++
 7 files changed, 107 insertions(+)
 create mode 100644 arch/mips/mach-bmips/Kconfig
 create mode 100644 arch/mips/mach-bmips/Makefile
 create mode 100644 arch/mips/mach-bmips/dram.c
 create mode 100644 include/configs/bmips_common.h

arch/mips/Kconfig +10 -0

index d97930e..c97ea41 100644
@@ -75,6 +75,15 @@ config ARCH_ATH79
 	select OF_CONTROL
 	select DM
 
+config ARCH_BMIPS
+	bool "Support BMIPS SoCs"
+	select OF_CONTROL
+	select DM
+	select CLK
+	select CPU
+	select RAM
+	select SYSRESET
+
 config MACH_PIC32
 	bool "Support Microchip PIC32"
 	select OF_CONTROL

@@ -123,6 +132,7 @@ source "board/micronas/vct/Kconfig"
 source "board/pb1x00/Kconfig"
 source "board/qemu-mips/Kconfig"
 source "arch/mips/mach-ath79/Kconfig"
+source "arch/mips/mach-bmips/Kconfig"
 source "arch/mips/mach-pic32/Kconfig"
 
 if MIPS

arch/mips/Makefile +1 -0

index efe7e44..c30d4ef 100644
@@ -15,6 +15,7 @@ libs-y += arch/mips/lib/
 
 machine-$(CONFIG_SOC_AU1X00) += au1x00
 machine-$(CONFIG_ARCH_ATH79) += ath79
+machine-$(CONFIG_ARCH_BMIPS) += bmips
 machine-$(CONFIG_MACH_PIC32) += pic32
 
 machdirs := $(patsubst %,arch/mips/mach-%/,$(machine-y))

arch/mips/cpu/start.S +5 -0

index f7dee81..5c1ad00 100644
@@ -151,8 +151,13 @@ reset:
 	 mfc0	t0, CP0_GLOBALNUMBER
 #endif
 
+#ifdef CONFIG_ARCH_BMIPS
+1:	mfc0	t0, CP0_DIAGNOSTIC, 3
+	and	t0, t0, (1 << 31)
+#else
 1:	mfc0	t0, CP0_EBASE
 	and	t0, t0, EBASE_CPUNUM
+#endif
 
 	/* Hang if this isn't the first CPU in the system */
 2:	beqz	t0, 4f

arch/mips/mach-bmips/Kconfig new file +5 -0

new file mode 100644
index 0000000..42a7e41
@@ -0,0 +1,22 @@
+menu "Broadcom MIPS platforms"
+	depends on ARCH_BMIPS
+
+config SYS_SOC
+	default "none"

arch/mips/mach-bmips/Kconfig new file +7 -0

+
+endchoice
+
+config BMIPS_SUPPORTS_BOOT_RAM
+	bool
+
+endmenu

arch/mips/mach-bmips/Makefile new file +5 -0

new file mode 100644
index 0000000..f432acc
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += dram.o

arch/mips/mach-bmips/dram.c new file +12 -0

new file mode 100644
index 0000000..b19b28a
@@ -0,0 +1,37 @@
+/*
+ * Copyright (C) 2016 Daniel Schwierzeck 
+ * Copyright (C) 2017 Álvaro Fernández Rojas 
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include 
+#include 
+#include 
+
+DECLARE_GLOBAL_DATA_PTR;

arch/mips/mach-bmips/dram.c new file +5 -0

+
+	gd->ram_size = ram.size;
+
+	return 0;
+}

include/configs/bmips_common.h new file +27 -0

new file mode 100644
index 0000000..3d67729
@@ -0,0 +1,27 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas 
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_COMMON_H
+#define __CONFIG_BMIPS_COMMON_H
+
+/* RAM */
+#define CONFIG_SYS_MEMTEST_START	0xa0000000
+#define CONFIG_SYS_MEMTEST_END		0xa2000000
+
+/* Serial */
+#define CONFIG_BAUDRATE			115200
+
+/* Memory usage */
+#define CONFIG_SYS_MAXARGS		24
+#define CONFIG_SYS_MALLOC_LEN		(1024 * 1024)
+#define CONFIG_SYS_BOOTPARAMS_LEN	(128 * 1024)
+#define CONFIG_SYS_CBSIZE		512
+
+/* U-Boot */
+#define CONFIG_SYS_MONITOR_BASE		CONFIG_SYS_TEXT_BASE
+#define CONFIG_REMAKE_ELF
+
+#endif /* __CONFIG_BMIPS_COMMON_H */