armv8: minor fix to comment for enabling SMPEN bit
PATCH 1/1 armv8: minor fix to comment for enabling SMPEN bit
The SMPEN bit is located in the cpuectlr_el1 register and not the cpuactlr_el1 register. Adjust the comment accordingly and also fix a spelling error.
Signed-off-by Dinh Nguyen <[email protected]>
CC Mingkai Hu <[email protected]>
CC Gong Qianyu <[email protected]>
CC Mateusz Kulikowski <[email protected]>
CC Hou Zhiqiang <[email protected]>
CC York Sun <[email protected]>
CC Albert Aribaud <[email protected]>
CC Masahiro Yamada <[email protected]>
--- arch/arm/cpu/armv8/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
arch/arm/cpu/armv8/start.S +2 -2
@@ -86,12 +86,12 @@ save_boot_params_ret: 0: /* - * Enalbe SMPEN bit for coherency. + * Enable SMPEN bit for coherency. * This register is not architectural but at the moment * this bit should be set for A53/A57/A72. */ #ifdef CONFIG_ARMV8_SET_SMPEN - mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ + mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */ orr x0, x0, #0x40 msr S3_1_c15_c2_1, x0 #endif
Signature · 1 line
2.7.4
PATCH 1/1 armv8: minor fix to comment for enabling SMPEN bit
Quoted 26 lines · Dinh Nguyen
The SMPEN bit is located in the
cpuectlr_el1register and not thecpuactlr_el1register. Adjust the comment accordingly and also fix a spelling error.Signed-off-by Dinh Nguyen <[email protected]>CC Mingkai Hu <[email protected]>CC Gong Qianyu <[email protected]>CC Mateusz Kulikowski <[email protected]>CC Hou Zhiqiang <[email protected]>CC York Sun <[email protected]>CC Albert Aribaud <[email protected]>CC Masahiro Yamada <[email protected]>--- arch/arm/cpu/armv8/start.S | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)arch/arm/cpu/armv8/start.S +0
-1@@ -86,12 +86,12 @@ save_boot_params_ret: 0: /* - * Enalbe SMPEN bit for coherency.
arch/arm/cpu/armv8/start.S save_boot_params_ret: · line 97
Quoted 10 lines
arch/arm/cpu/armv8/start.S +2
-1+ * Enable SMPEN bit for coherency. * This register is not architectural but at the moment * this bit should be set for A53/A57/A72. */ #ifdef CONFIG_ARMV8_SET_SMPEN - mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ + mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */ orr x0, x0, #0x40 msr S3_1_c15_c2_1, x0 #endif
Thanks for fixing this.
Reviewed-by York Sun <[email protected]>
Quoted 4 lines · Dinh Nguyen
The SMPEN bit is located in the
cpuectlr_el1register and not thecpuactlr_el1register. Adjust the comment accordingly and also fix a spelling error.
Quoted 9 lines
Signed-off-by Dinh Nguyen <[email protected]>CC Mingkai Hu <[email protected]>CC Gong Qianyu <[email protected]>CC Mateusz Kulikowski <[email protected]>CC Hou Zhiqiang <[email protected]>CC York Sun <[email protected]>CC Albert Aribaud <[email protected]>CC Masahiro Yamada <[email protected]>Reviewed-by York Sun <[email protected]>
Applied to u-boot/master, thanks!
Signature · 8 lines
Tom -------------- next part -------------- A non-text attachment was scrubbed... Name: signature.asc Type: application/pgp-signature Size: 819 bytes Desc: Digital signature URL: <http://lists.denx.de/pipermail/u-boot/attachments/20170515/3fa13e11/attachment.sig>