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dm: rst: add BCM6345 reset controller support

PATCH Superseded Álvaro Fernández Rojas 3 participants 12 messages May 3, 2017 – May 10, 2017

Subsystems (3)
Device tree bindings MIPS Reset controller framework

v1 of 2 Superseded Latest is v2 →

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Álvaro Fernández Rojas

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#0 lore raw

cover dm: rst: add BCM6345 reset controller support

Broadcom MIPS SoCs have reset controllers which supports asserting and deasserting each peripheral controller.
Checking reset status is not supported, which is why delays are used.

Álvaro Fernández Rojas (5):
dm: reset: add BCM6345 reset driver
mips: bmips: add bcm6345-rst driver support for BCM6358
mips: bmips: add bcm6345-rst driver support for BCM6328
mips: bmips: add bcm6345-rst driver support for BCM63268
mips: bmips: enable bcm6345-reset driver for all BMIPS boards

 arch/mips/dts/brcm,bcm63268.dtsi           |  7 +++
 arch/mips/dts/brcm,bcm6328.dtsi            |  7 +++
 arch/mips/dts/brcm,bcm6358.dtsi            |  7 +++
 configs/comtrend_ar5387un_ram_defconfig    |  3 +
 configs/comtrend_vr3032u_ram_defconfig     |  3 +
 configs/huawei_hg556a_ram_defconfig        |  3 +
 configs/sfr_nb4-ser_ram_defconfig          |  3 +
 drivers/reset/Kconfig                      |  6 ++
 drivers/reset/Makefile                     |  1 +
 drivers/reset/reset-bcm6345.c              | 89 ++++++++++++++++++++++++++++++
 include/dt-bindings/reset/bcm63268-reset.h | 32 +++++++++++
 include/dt-bindings/reset/bcm6328-reset.h  | 24 ++++++++
 include/dt-bindings/reset/bcm6358-reset.h  | 21 +++++++
 13 files changed, 206 insertions(+)
 create mode 100644 drivers/reset/reset-bcm6345.c
 create mode 100644 include/dt-bindings/reset/bcm63268-reset.h
 create mode 100644 include/dt-bindings/reset/bcm6328-reset.h
 create mode 100644 include/dt-bindings/reset/bcm6358-reset.h
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH 1/5 dm: reset: add BCM6345 reset driver

This is a simplified version of linux/arch/mips/bcm63xx/reset.c

Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 drivers/reset/Kconfig         |  6 +++
 drivers/reset/Makefile        |  1 +
 drivers/reset/reset-bcm6345.c | 89 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 96 insertions(+)
 create mode 100644 drivers/reset/reset-bcm6345.c
drivers/reset/Kconfig +6 -0
index fa77ee4..822d7f1 100644
@@ -42,6 +42,12 @@ config TEGRA186_RESET
 	  Enable support for manipulating Tegra's on-SoC reset signals via IPC
 	  requests to the BPMP (Boot and Power Management Processor).
 
+config RESET_BCM6345
+	bool "Reset controller driver for BCM6345"
+	depends on DM_RESET && ARCH_BMIPS
+	help
+	  Support reset controller on BCM6345.
+
 config RESET_UNIPHIER
 	bool "Reset controller driver for UniPhier SoCs"
 	depends on ARCH_UNIPHIER
drivers/reset/Makefile +1 -0
index 2b96396..f29fb20 100644
@@ -8,4 +8,5 @@ obj-$(CONFIG_SANDBOX_MBOX) += sandbox-reset-test.o
 obj-$(CONFIG_STI_RESET) += sti-reset.o
 obj-$(CONFIG_TEGRA_CAR_RESET) += tegra-car-reset.o
 obj-$(CONFIG_TEGRA186_RESET) += tegra186-reset.o
+obj-$(CONFIG_RESET_BCM6345) += reset-bcm6345.o
 obj-$(CONFIG_RESET_UNIPHIER) += reset-uniphier.o
drivers/reset/reset-bcm6345.c new file +89 -0

89 lines not on this page · raw message

Signature · 1 line
2.1.4
#2 lore raw

PATCH 1/5 dm: reset: add BCM6345 reset driver

Quoted 9 lines · Álvaro Fernández Rojas

This is a simplified version of linux/arch/mips/bcm63xx/reset.c

Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 drivers/reset/Kconfig         |  6 +++
 drivers/reset/Makefile        |  1 +
 drivers/reset/reset-bcm6345.c | 89 +++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 96 insertions(+)
 create mode 100644 drivers/reset/reset-bcm6345.c
Reviewed-by Simon Glass <[email protected]>
author
#3 lore raw

PATCH 2/5 mips: bmips: add bcm6345-rst driver support for BCM6358

In reply to Álvaro Fernández Rojas

This driver can control up to 32 resets.

Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 arch/mips/dts/brcm,bcm6358.dtsi           |  7 +++++++
 include/dt-bindings/reset/bcm6358-reset.h | 21 +++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 include/dt-bindings/reset/bcm6358-reset.h
arch/mips/dts/brcm,bcm6358.dtsi +7 -0
index 369c240..df75988 100644
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/bcm6358-clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6358-reset.h>
 #include "skeleton.dtsi"
 
 / {

@@ -80,6 +81,12 @@
 			mask = <0x1>;
 		};
 
+		periph_rst: reset-controller at fffe0034 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0xfffe0034 0x4>;
+			#reset-cells = <1>;
+		};
+
 		gpio1: gpio-controller at fffe0080 {
 			compatible = "brcm,bcm6345-gpio";
 			reg = <0xfffe0080 0x4>, <0xfffe0088 0x4>;
include/dt-bindings/reset/bcm6358-reset.h new file +21 -0
new file mode 100644
index 0000000..4b3cff3
@@ -0,0 +1,21 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6358_H
+#define __DT_BINDINGS_RESET_BCM6358_H
+
+#define BCM6358_RST_SPI		0
+#define BCM6358_RST_ENET	2
+#define BCM6358_RST_MPI		3
+#define BCM6358_RST_EPHY	6
+#define BCM6358_RST_SAR		7
+#define BCM6358_RST_USBH	12
+#define BCM6358_RST_PCM		13
+#define BCM6358_RST_ADSL	14
+
+#endif /* __DT_BINDINGS_RESET_BCM6358_H */
Signature · 1 line
2.1.4
#4 lore raw

PATCH 2/5 mips: bmips: add bcm6345-rst driver support for BCM6358

Quoted 9 lines · Álvaro Fernández Rojas

This driver can control up to 32 resets.

Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 arch/mips/dts/brcm,bcm6358.dtsi           |  7 +++++++
 include/dt-bindings/reset/bcm6358-reset.h | 21 +++++++++++++++++++++
 2 files changed, 28 insertions(+)
 create mode 100644 include/dt-bindings/reset/bcm6358-reset.h
Reviewed-by Simon Glass <[email protected]>
author
#5 lore raw

PATCH 3/5 mips: bmips: add bcm6345-rst driver support for BCM6328

In reply to Álvaro Fernández Rojas

This driver can control up to 32 clocks.

Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 arch/mips/dts/brcm,bcm6328.dtsi           |  7 +++++++
 include/dt-bindings/reset/bcm6328-reset.h | 24 ++++++++++++++++++++++++
 2 files changed, 31 insertions(+)
 create mode 100644 include/dt-bindings/reset/bcm6328-reset.h
arch/mips/dts/brcm,bcm6328.dtsi +7 -0
index 6b5c5dd..9b76a23 100644
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/bcm6328-clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm6328-reset.h>
 #include "skeleton.dtsi"
 
 / {

@@ -58,6 +59,12 @@
 		#size-cells = <1>;
 		u-boot,dm-pre-reloc;
 
+		periph_rst: reset-controller at 10000010 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x10000010 0x4>;
+			#reset-cells = <1>;
+		};
+
 		pll_cntl: syscon at 10000068 {
 			compatible = "syscon";
 			reg = <0x10000068 0x4>;
include/dt-bindings/reset/bcm6328-reset.h new file +24 -0
new file mode 100644
index 0000000..c144ad2
@@ -0,0 +1,24 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM6328_H
+#define __DT_BINDINGS_RESET_BCM6328_H
+
+#define BCM6328_RST_SPI		0
+#define BCM6328_RST_EPHY	1
+#define BCM6328_RST_SAR		2
+#define BCM6328_RST_ENETSW	3
+#define BCM6328_RST_USBS	4
+#define BCM6328_RST_USBH	5
+#define BCM6328_RST_PCM		6
+#define BCM6328_RST_PCIE_CORE	7
+#define BCM6328_RST_PCIE	8
+#define BCM6328_RST_PCIE_EXT	9
+#define BCM6328_RST_PCIE_HARD	10
+
+#endif /* __DT_BINDINGS_RESET_BCM6328_H */
Signature · 1 line
2.1.4
#6 lore raw

PATCH 3/5 mips: bmips: add bcm6345-rst driver support for BCM6328

Quoted 8 lines · Álvaro Fernández Rojas

This driver can control up to 32 clocks.

Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 arch/mips/dts/brcm,bcm6328.dtsi           |  7 +++++++
 include/dt-bindings/reset/bcm6328-reset.h | 24 ++++++++++++++++++++++++
 2 files changed, 31 insertions(+)
 create mode 100644 include/dt-bindings/reset/bcm6328-reset.h
Reviewed-by Simon Glass <[email protected]>
author
#7 lore raw

PATCH 4/5 mips: bmips: add bcm6345-rst driver support for BCM63268

In reply to Álvaro Fernández Rojas

This driver can control up to 32 clocks.

Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 arch/mips/dts/brcm,bcm63268.dtsi           |  7 +++++++
 include/dt-bindings/reset/bcm63268-reset.h | 32 ++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 include/dt-bindings/reset/bcm63268-reset.h
arch/mips/dts/brcm,bcm63268.dtsi +7 -0
index 4d02024..8ff13c1 100644
@@ -6,6 +6,7 @@
 
 #include <dt-bindings/clock/bcm63268-clock.h>
 #include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm63268-reset.h>
 #include "skeleton.dtsi"
 
 / {

@@ -76,6 +77,12 @@
 			mask = <0x1>;
 		};
 
+		periph_rst: reset-controller at 10000010 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x10000010 0x4>;
+			#reset-cells = <1>;
+		};
+
 		gpio1: gpio-controller at 100000c0 {
 			compatible = "brcm,bcm6345-gpio";
 			reg = <0x100000c0 0x4>, <0x100000c8 0x4>;
include/dt-bindings/reset/bcm63268-reset.h new file +32 -0
new file mode 100644
index 0000000..1373884
@@ -0,0 +1,32 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * Derived from linux/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM63268_H
+#define __DT_BINDINGS_RESET_BCM63268_H
+
+#define BCM63268_RST_SPI	0
+#define BCM63268_RST_IPSEC	1
+#define BCM63268_RST_EPHY	2
+#define BCM63268_RST_SAR	3
+#define BCM63268_RST_ENETSW	4
+#define BCM63268_RST_USBS	5
+#define BCM63268_RST_USBH	6
+#define BCM63268_RST_PCM	7
+#define BCM63268_RST_PCIE_CORE	8
+#define BCM63268_RST_PCIE	9
+#define BCM63268_RST_PCIE_EXT	10
+#define BCM63268_RST_WLAN_SHIM	11
+#define BCM63268_RST_DDR_PHY	12
+#define BCM63268_RST_FAP0	13
+#define BCM63268_RST_WLAN_UBUS	14
+#define BCM63268_RST_DECT	15
+#define BCM63268_RST_FAP1	16
+#define BCM63268_RST_PCIE_HARD	17
+#define BCM63268_RST_GPHY	18
+
+#endif /* __DT_BINDINGS_RESET_BCM63268_H */
Signature · 1 line
2.1.4
#8 lore raw

PATCH 4/5 mips: bmips: add bcm6345-rst driver support for BCM63268

Quoted 8 lines · Álvaro Fernández Rojas

This driver can control up to 32 clocks.

Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 arch/mips/dts/brcm,bcm63268.dtsi           |  7 +++++++
 include/dt-bindings/reset/bcm63268-reset.h | 32 ++++++++++++++++++++++++++++++
 2 files changed, 39 insertions(+)
 create mode 100644 include/dt-bindings/reset/bcm63268-reset.h
Reviewed-by Simon Glass <[email protected]>
author
#9 lore raw

PATCH 5/5 mips: bmips: enable bcm6345-reset driver for all BMIPS boards

In reply to Álvaro Fernández Rojas
Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 configs/comtrend_ar5387un_ram_defconfig | 3 +++
 configs/comtrend_vr3032u_ram_defconfig  | 3 +++
 configs/huawei_hg556a_ram_defconfig     | 3 +++
 configs/sfr_nb4-ser_ram_defconfig       | 3 +++
 4 files changed, 12 insertions(+)
configs/comtrend_ar5387un_ram_defconfig +3 -0
index 55cb4bf..d613740 100644
@@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="comtrend,ar-5387un"
 CONFIG_DISPLAY_CPUINFO=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
 CONFIG_DM_SERIAL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_LED=y

@@ -41,6 +42,8 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
 CONFIG_SOC_BMIPS_BCM6328=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
configs/comtrend_vr3032u_ram_defconfig +3 -0
index 7f13d24..fa2b2ae 100644
@@ -31,6 +31,7 @@ CONFIG_DEFAULT_DEVICE_TREE="comtrend,vr-3032u"
 CONFIG_DISPLAY_CPUINFO=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
 CONFIG_DM_SERIAL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_LED=y

@@ -41,6 +42,8 @@ CONFIG_MIPS=y
 # CONFIG_MIPS_BOOT_ENV_LEGACY is not set
 CONFIG_MIPS_BOOT_FDT=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
 CONFIG_SOC_BMIPS_BCM63268=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
configs/huawei_hg556a_ram_defconfig +3 -0
index 71e1163..c2e6472 100644
@@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="huawei,hg556a"
 CONFIG_DISPLAY_CPUINFO=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
 CONFIG_DM_SERIAL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_LED=y

@@ -45,6 +46,8 @@ CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
 CONFIG_SOC_BMIPS_BCM6358=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
configs/sfr_nb4-ser_ram_defconfig +3 -0
index cd6c4a2..d7c8329 100644
@@ -33,6 +33,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sfr,nb4-ser"
 CONFIG_DISPLAY_CPUINFO=y
 # CONFIG_DM_DEVICE_REMOVE is not set
 CONFIG_DM_GPIO=y
+CONFIG_DM_RESET=y
 CONFIG_DM_SERIAL=y
 CONFIG_HUSH_PARSER=y
 CONFIG_LED=y

@@ -46,6 +47,8 @@ CONFIG_MTD=y
 CONFIG_MTD_DEVICE=y
 CONFIG_MTD_NOR_FLASH=y
 CONFIG_OF_STDOUT_VIA_ALIAS=y
+CONFIG_RESET=y
+CONFIG_RESET_BCM6345=y
 CONFIG_SOC_BMIPS_BCM6358=y
 # CONFIG_SPL_SERIAL_PRESENT is not set
 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set
Signature · 1 line
2.1.4
#10 lore raw

PATCH 5/5 mips: bmips: enable bcm6345-reset driver for all BMIPS boards

Quoted 8 lines · Álvaro Fernández Rojas
Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 configs/comtrend_ar5387un_ram_defconfig | 3 +++
 configs/comtrend_vr3032u_ram_defconfig  | 3 +++
 configs/huawei_hg556a_ram_defconfig     | 3 +++
 configs/sfr_nb4-ser_ram_defconfig       | 3 +++
 4 files changed, 12 insertions(+)
Reviewed-by Simon Glass <[email protected]>

Also consider using imply.

#11 lore raw

cover dm: rst: add BCM6345 reset controller support

In reply to Álvaro Fernández Rojas

Am 03.05.2017 um 15:10 schrieb Álvaro Fernández Rojas:

Quoted 21 lines

Broadcom MIPS SoCs have reset controllers which supports asserting and deasserting each peripheral controller.
Checking reset status is not supported, which is why delays are used.

Álvaro Fernández Rojas (5):
dm: reset: add BCM6345 reset driver
mips: bmips: add bcm6345-rst driver support for BCM6358
mips: bmips: add bcm6345-rst driver support for BCM6328
mips: bmips: add bcm6345-rst driver support for BCM63268
mips: bmips: enable bcm6345-reset driver for all BMIPS boards

 arch/mips/dts/brcm,bcm63268.dtsi           |  7 +++
 arch/mips/dts/brcm,bcm6328.dtsi            |  7 +++
 arch/mips/dts/brcm,bcm6358.dtsi            |  7 +++
 configs/comtrend_ar5387un_ram_defconfig    |  3 +
 configs/comtrend_vr3032u_ram_defconfig     |  3 +
 configs/huawei_hg556a_ram_defconfig        |  3 +
 configs/sfr_nb4-ser_ram_defconfig          |  3 +
 drivers/reset/Kconfig                      |  6 ++
 drivers/reset/Makefile                     |  1 +
 drivers/reset/reset-bcm6345.c              | 89 ++++++++++++++++++++++++++++++
Quoted 9 lines
 include/dt-bindings/reset/bcm63268-reset.h | 32 +++++++++++
 include/dt-bindings/reset/bcm6328-reset.h  | 24 ++++++++
 include/dt-bindings/reset/bcm6358-reset.h  | 21 +++++++
 13 files changed, 206 insertions(+)
 create mode 100644 drivers/reset/reset-bcm6345.c
 create mode 100644 include/dt-bindings/reset/bcm63268-reset.h
 create mode 100644 include/dt-bindings/reset/bcm6328-reset.h
 create mode 100644 include/dt-bindings/reset/bcm6358-reset.h

series applied to u-boot-mips/next, thanks

Signature · 9 lines
- Daniel

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