Add minimal boot support for IPQ8074

Add initial pinctrl driver to support pin configuration with pinctrl framework for ipq8074.

Signed-off-by Manoharan Vijaya Raghavan <[email protected]>

Signed-off-by Varadarajan Narayanan <[email protected]>

---
  .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt      |  187 +++
  drivers/pinctrl/qcom/Kconfig                       |   10 +
  drivers/pinctrl/qcom/Makefile                      |    1 +
  drivers/pinctrl/qcom/pinctrl-ipq8074.c             | 1217 ++++++++++++++++++++
  4 files changed, 1415 insertions(+)

create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt new file +187 -0

new file mode 100644
index 0000000..7765bca
@@ -0,0 +1,187 @@
+Qualcomm Technologies, Inc. IPQ8074 TLMM block
+
+This binding describes the Top Level Mode Multiplexer block found in the
+IPQ8074 platform.
+
+- compatible:
+	Usage: required
+	Value type: <string>
+	Definition: must be "qcom,ipq8074-pinctrl"
+
+- reg:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: the base address and size of the TLMM register space.
+
+- interrupts:
+	Usage: required
+	Value type: <prop-encoded-array>
+	Definition: should specify the TLMM summary IRQ.
+
+- interrupt-controller:
+	Usage: required
+	Value type: <none>
+	Definition: identifies this node as an interrupt controller
+
+- #interrupt-cells:
+	Usage: required
+	Value type: <u32>
+	Definition: must be 2. Specifying the pin number and flags, as defined
+		    in <dt-bindings/interrupt-controller/irq.h>
+
+- gpio-controller:
+	Usage: required
+	Value type: <none>
+	Definition: identifies this node as a gpio controller
+
+- #gpio-cells:
+	Usage: required
+	Value type: <u32>
+	Definition: must be 2. Specifying the pin number and flags, as defined
+		    in <dt-bindings/gpio/gpio.h>
+
+Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
+a general description of GPIO and interrupt bindings.
+
+Please refer to pinctrl-bindings.txt in this directory for details of the
+common pinctrl bindings used by client devices, including the meaning of the
+phrase "pin configuration node".
+
+The pin configuration nodes act as a container for an arbitrary number of
+subnodes. Each of these subnodes represents some desired configuration for a
+pin, a group, or a list of pins or groups. This configuration can include the
+mux function to select on those pin(s)/group(s), and various pin configuration
+parameters, such as pull-up, drive strength, etc.
+
+
+PIN CONFIGURATION NODES:
+
+The name of each subnode is not important; all subnodes should be enumerated
+and processed purely based on their content.
+
+Each subnode only affects those parameters that are explicitly listed. In
+other words, a subnode that lists a mux function but no pin configuration
+parameters implies no information about any pin configuration parameters.
+Similarly, a pin subnode that describes a pullup parameter implies no
+information about e.g. the mux function.
+
+
+The following generic properties as defined in pinctrl-bindings.txt are valid
+to specify in a pin configuration subnode:
+
+- pins:
+	Usage: required
+	Value type: <string-array>
+	Definition: List of gpio pins affected by the properties specified in
+		    this subnode.  Valid pins are:
+		    gpio0-gpio121,
+		    sdc1_clk,
+		    sdc1_cmd,
+		    sdc1_data
+		    sdc2_clk,
+		    sdc2_cmd,
+		    sdc2_data,
+		    qdsd_cmd,
+		    qdsd_data0,
+		    qdsd_data1,
+		    qdsd_data2,
+		    qdsd_data3
+
+- function:
+	Usage: required
+	Value type: <string>
+	Definition: Specify the alternative function to be configured for the
+		    specified pins. Functions are only valid for gpio pins.
+		    Valid values are:
+	gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
+	burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
+	qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
+	blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+	qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
+	qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
+	qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
+	qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
+	qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
+	qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
+	pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+	blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
+	audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
+	audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
+	atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
+	pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
+	mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
+	qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
+	blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
+	blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,
+	cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
+	cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
+	pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
+	gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
+	gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
+	tsens_max, mdc, mdio, NA
+
+- bias-disable:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins should be configued as no pull.
+
+- bias-pull-down:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins should be configued as pull down.
+
+- bias-pull-up:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins should be configued as pull up.
+
+- output-high:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins are configured in output mode, driven
+		    high.
+		    Not valid for sdc pins.
+
+- output-low:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins are configured in output mode, driven
+		    low.
+		    Not valid for sdc pins.
+
+- drive-strength:
+	Usage: optional
+	Value type: <u32>
+	Definition: Selects the drive strength for the specified pins, in mA.
+		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+
+Example:
+
+	tlmm: pinctrl at 1000000 {
+		compatible = "qcom,ipq8074-pinctrl";
+		reg = <0x1000000 0x300000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+
+		uart2: uart2-default {
+			mux {
+				pins = "gpio23", "gpio24";
+				function = "blsp4_uart1";
+			};
+
+			rx {
+				pins = "gpio23";
+				drive-strength = <4>;
+				bias-disable;
+			};
+
+			tx {
+				pins = "gpio24";
+				drive-strength = <2>;
+				bias-pull-up;
+			};
+		};
+	};

drivers/pinctrl/qcom/Kconfig +10 -0

index 3ebdc01..9e504db 100644
@@ -39,6 +39,16 @@ config PINCTRL_IPQ8064
  	  This is the pinctrl, pinmux, pinconf and gpiolib driver for the
  	  Qualcomm TLMM block found in the Qualcomm IPQ8064 platform.
 
+config PINCTRL_IPQ8074
+	tristate "Qualcomm Technologies, Inc. IPQ8074 pin controller driver"
+	depends on GPIOLIB && OF
+	select PINCTRL_MSM
+	help
+	  This is the pinctrl, pinmux, pinconf and gpiolib driver for
+	  the Qualcomm Technologies Inc. TLMM block found on the
+	  Qualcomm Technologies Inc. IPQ8074 platform. Select this for
+	  IPQ8074.
+
  config PINCTRL_MSM8660
  	tristate "Qualcomm 8660 pin controller driver"
  	depends on GPIOLIB && OF

drivers/pinctrl/qcom/Makefile +1 -0

index ab47764..06c8b2a 100644
@@ -4,6 +4,7 @@ obj-$(CONFIG_PINCTRL_APQ8064)	+= pinctrl-apq8064.o
  obj-$(CONFIG_PINCTRL_APQ8084)	+= pinctrl-apq8084.o
  obj-$(CONFIG_PINCTRL_IPQ4019)	+= pinctrl-ipq4019.o
  obj-$(CONFIG_PINCTRL_IPQ8064)	+= pinctrl-ipq8064.o
+obj-$(CONFIG_PINCTRL_IPQ8074)	+= pinctrl-ipq8074.o
  obj-$(CONFIG_PINCTRL_MSM8660)	+= pinctrl-msm8660.o
  obj-$(CONFIG_PINCTRL_MSM8960)	+= pinctrl-msm8960.o
  obj-$(CONFIG_PINCTRL_MSM8X74)	+= pinctrl-msm8x74.o

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +1217 -0

new file mode 100644
index 0000000..8bb8071
@@ -0,0 +1,1217 @@
+/*
+ * Copyright (c) 2017, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/pinctrl/pinctrl.h>
+
+#include "pinctrl-msm.h"
+
+#define FUNCTION(fname)			                \
+	[msm_mux_##fname] = {		                \
+		.name = #fname,				\
+		.groups = fname##_groups,               \
+		.ngroups = ARRAY_SIZE(fname##_groups),	\
+	}
+
+#define REG_SIZE 0x1000
+#define PINGROUP(id, f1, f2, f3, f4, f5, f6, f7, f8, f9)	\
+	{					        \
+		.name = "gpio" #id,			\
+		.pins = gpio##id##_pins,		\
+		.npins = (unsigned int)ARRAY_SIZE(gpio##id##_pins),	\
+		.funcs = (int[]){			\
+			msm_mux_gpio, /* gpio mode */	\
+			msm_mux_##f1,			\
+			msm_mux_##f2,			\
+			msm_mux_##f3,			\
+			msm_mux_##f4,			\
+			msm_mux_##f5,			\
+			msm_mux_##f6,			\
+			msm_mux_##f7,			\
+			msm_mux_##f8,			\
+			msm_mux_##f9			\
+		},				        \
+		.nfuncs = 10,				\
+		.ctl_reg = REG_SIZE * id,		\
+		.io_reg = 0x4 + REG_SIZE * id,		\
+		.intr_cfg_reg = 0x8 + REG_SIZE * id,		\
+		.intr_status_reg = 0xc + REG_SIZE * id,	\
+		.intr_target_reg = 0x8 + REG_SIZE * id,	\
+		.mux_bit = 2,			\
+		.pull_bit = 0,			\
+		.drv_bit = 6,			\
+		.oe_bit = 9,			\
+		.in_bit = 0,			\
+		.out_bit = 1,			\
+		.intr_enable_bit = 0,		\
+		.intr_status_bit = 0,		\
+		.intr_target_bit = 5,		\
+		.intr_raw_status_bit = 4,	\
+		.intr_polarity_bit = 1,		\
+		.intr_detection_bit = 2,	\
+		.intr_detection_width = 2,	\
+	}
+
+static const struct pinctrl_pin_desc ipq8074_pins[] = {
+	PINCTRL_PIN(0, "GPIO_0"),
+	PINCTRL_PIN(1, "GPIO_1"),
+	PINCTRL_PIN(2, "GPIO_2"),
+	PINCTRL_PIN(3, "GPIO_3"),
+	PINCTRL_PIN(4, "GPIO_4"),
+	PINCTRL_PIN(5, "GPIO_5"),
+	PINCTRL_PIN(6, "GPIO_6"),
+	PINCTRL_PIN(7, "GPIO_7"),
+	PINCTRL_PIN(8, "GPIO_8"),
+	PINCTRL_PIN(9, "GPIO_9"),
+	PINCTRL_PIN(10, "GPIO_10"),
+	PINCTRL_PIN(11, "GPIO_11"),
+	PINCTRL_PIN(12, "GPIO_12"),
+	PINCTRL_PIN(13, "GPIO_13"),
+	PINCTRL_PIN(14, "GPIO_14"),
+	PINCTRL_PIN(15, "GPIO_15"),
+	PINCTRL_PIN(16, "GPIO_16"),
+	PINCTRL_PIN(17, "GPIO_17"),
+	PINCTRL_PIN(18, "GPIO_18"),
+	PINCTRL_PIN(19, "GPIO_19"),
+	PINCTRL_PIN(20, "GPIO_20"),
+	PINCTRL_PIN(21, "GPIO_21"),
+	PINCTRL_PIN(22, "GPIO_22"),
+	PINCTRL_PIN(23, "GPIO_23"),
+	PINCTRL_PIN(24, "GPIO_24"),
+	PINCTRL_PIN(25, "GPIO_25"),
+	PINCTRL_PIN(26, "GPIO_26"),
+	PINCTRL_PIN(27, "GPIO_27"),
+	PINCTRL_PIN(28, "GPIO_28"),
+	PINCTRL_PIN(29, "GPIO_29"),
+	PINCTRL_PIN(30, "GPIO_30"),
+	PINCTRL_PIN(31, "GPIO_31"),
+	PINCTRL_PIN(32, "GPIO_32"),
+	PINCTRL_PIN(33, "GPIO_33"),
+	PINCTRL_PIN(34, "GPIO_34"),
+	PINCTRL_PIN(35, "GPIO_35"),
+	PINCTRL_PIN(36, "GPIO_36"),
+	PINCTRL_PIN(37, "GPIO_37"),
+	PINCTRL_PIN(38, "GPIO_38"),
+	PINCTRL_PIN(39, "GPIO_39"),
+	PINCTRL_PIN(40, "GPIO_40"),
+	PINCTRL_PIN(41, "GPIO_41"),
+	PINCTRL_PIN(42, "GPIO_42"),
+	PINCTRL_PIN(43, "GPIO_43"),
+	PINCTRL_PIN(44, "GPIO_44"),
+	PINCTRL_PIN(45, "GPIO_45"),
+	PINCTRL_PIN(46, "GPIO_46"),
+	PINCTRL_PIN(47, "GPIO_47"),
+	PINCTRL_PIN(48, "GPIO_48"),
+	PINCTRL_PIN(49, "GPIO_49"),
+	PINCTRL_PIN(50, "GPIO_50"),
+	PINCTRL_PIN(51, "GPIO_51"),
+	PINCTRL_PIN(52, "GPIO_52"),
+	PINCTRL_PIN(53, "GPIO_53"),
+	PINCTRL_PIN(54, "GPIO_54"),
+	PINCTRL_PIN(55, "GPIO_55"),
+	PINCTRL_PIN(56, "GPIO_56"),
+	PINCTRL_PIN(57, "GPIO_57"),
+	PINCTRL_PIN(58, "GPIO_58"),
+	PINCTRL_PIN(59, "GPIO_59"),
+	PINCTRL_PIN(60, "GPIO_60"),
+	PINCTRL_PIN(61, "GPIO_61"),
+	PINCTRL_PIN(62, "GPIO_62"),
+	PINCTRL_PIN(63, "GPIO_63"),
+	PINCTRL_PIN(64, "GPIO_64"),
+	PINCTRL_PIN(65, "GPIO_65"),
+	PINCTRL_PIN(66, "GPIO_66"),
+	PINCTRL_PIN(67, "GPIO_67"),
+	PINCTRL_PIN(68, "GPIO_68"),
+	PINCTRL_PIN(69, "GPIO_69"),
+};
+
+#define DECLARE_MSM_GPIO_PINS(pin) \
+	static const unsigned int gpio##pin##_pins[] = { pin }
+DECLARE_MSM_GPIO_PINS(0);
+DECLARE_MSM_GPIO_PINS(1);
+DECLARE_MSM_GPIO_PINS(2);
+DECLARE_MSM_GPIO_PINS(3);
+DECLARE_MSM_GPIO_PINS(4);
+DECLARE_MSM_GPIO_PINS(5);
+DECLARE_MSM_GPIO_PINS(6);
+DECLARE_MSM_GPIO_PINS(7);
+DECLARE_MSM_GPIO_PINS(8);
+DECLARE_MSM_GPIO_PINS(9);
+DECLARE_MSM_GPIO_PINS(10);
+DECLARE_MSM_GPIO_PINS(11);
+DECLARE_MSM_GPIO_PINS(12);
+DECLARE_MSM_GPIO_PINS(13);
+DECLARE_MSM_GPIO_PINS(14);
+DECLARE_MSM_GPIO_PINS(15);
+DECLARE_MSM_GPIO_PINS(16);
+DECLARE_MSM_GPIO_PINS(17);
+DECLARE_MSM_GPIO_PINS(18);
+DECLARE_MSM_GPIO_PINS(19);
+DECLARE_MSM_GPIO_PINS(20);
+DECLARE_MSM_GPIO_PINS(21);
+DECLARE_MSM_GPIO_PINS(22);
+DECLARE_MSM_GPIO_PINS(23);
+DECLARE_MSM_GPIO_PINS(24);
+DECLARE_MSM_GPIO_PINS(25);
+DECLARE_MSM_GPIO_PINS(26);
+DECLARE_MSM_GPIO_PINS(27);
+DECLARE_MSM_GPIO_PINS(28);
+DECLARE_MSM_GPIO_PINS(29);
+DECLARE_MSM_GPIO_PINS(30);
+DECLARE_MSM_GPIO_PINS(31);
+DECLARE_MSM_GPIO_PINS(32);
+DECLARE_MSM_GPIO_PINS(33);
+DECLARE_MSM_GPIO_PINS(34);
+DECLARE_MSM_GPIO_PINS(35);
+DECLARE_MSM_GPIO_PINS(36);
+DECLARE_MSM_GPIO_PINS(37);
+DECLARE_MSM_GPIO_PINS(38);
+DECLARE_MSM_GPIO_PINS(39);
+DECLARE_MSM_GPIO_PINS(40);
+DECLARE_MSM_GPIO_PINS(41);
+DECLARE_MSM_GPIO_PINS(42);
+DECLARE_MSM_GPIO_PINS(43);
+DECLARE_MSM_GPIO_PINS(44);
+DECLARE_MSM_GPIO_PINS(45);
+DECLARE_MSM_GPIO_PINS(46);
+DECLARE_MSM_GPIO_PINS(47);
+DECLARE_MSM_GPIO_PINS(48);
+DECLARE_MSM_GPIO_PINS(49);
+DECLARE_MSM_GPIO_PINS(50);
+DECLARE_MSM_GPIO_PINS(51);
+DECLARE_MSM_GPIO_PINS(52);
+DECLARE_MSM_GPIO_PINS(53);
+DECLARE_MSM_GPIO_PINS(54);
+DECLARE_MSM_GPIO_PINS(55);
+DECLARE_MSM_GPIO_PINS(56);
+DECLARE_MSM_GPIO_PINS(57);
+DECLARE_MSM_GPIO_PINS(58);
+DECLARE_MSM_GPIO_PINS(59);
+DECLARE_MSM_GPIO_PINS(60);
+DECLARE_MSM_GPIO_PINS(61);
+DECLARE_MSM_GPIO_PINS(62);
+DECLARE_MSM_GPIO_PINS(63);
+DECLARE_MSM_GPIO_PINS(64);
+DECLARE_MSM_GPIO_PINS(65);
+DECLARE_MSM_GPIO_PINS(66);
+DECLARE_MSM_GPIO_PINS(67);
+DECLARE_MSM_GPIO_PINS(68);
+DECLARE_MSM_GPIO_PINS(69);
+
+enum ipq8074_functions {
+	msm_mux_gpio,
+	msm_mux_qpic_pad,
+	msm_mux_blsp5_i2c,
+	msm_mux_blsp5_spi,
+	msm_mux_wci20,
+	msm_mux_blsp3_spi3,
+	msm_mux_burn0,
+	msm_mux_pcm_zsi0,
+	msm_mux_blsp5_uart,
+	msm_mux_mac12,
+	msm_mux_blsp3_spi0,
+	msm_mux_burn1,
+	msm_mux_mac01,
+	msm_mux_qdss_cti_trig_out_b0,
+	msm_mux_qdss_cti_trig_in_b0,
+	msm_mux_qpic_pad4,
+	msm_mux_blsp4_uart0,
+	msm_mux_blsp4_i2c0,
+	msm_mux_blsp4_spi0,
+	msm_mux_mac21,
+	msm_mux_qdss_cti_trig_out_b1,
+	msm_mux_qpic_pad5,
+	msm_mux_qdss_cti_trig_in_b1,
+	msm_mux_qpic_pad6,
+	msm_mux_qpic_pad7,
+	msm_mux_cxc0,
+	msm_mux_mac13,
+	msm_mux_qdss_cti_trig_in_a1,
+	msm_mux_qdss_cti_trig_out_a1,
+	msm_mux_wci22,
+	msm_mux_qdss_cti_trig_in_a0,
+	msm_mux_qpic_pad1,
+	msm_mux_qdss_cti_trig_out_a0,
+	msm_mux_qpic_pad2,
+	msm_mux_qpic_pad3,
+	msm_mux_qdss_traceclk_b,
+	msm_mux_qpic_pad0,
+	msm_mux_qdss_tracectl_b,
+	msm_mux_qpic_pad8,
+	msm_mux_pcm_zsi1,
+	msm_mux_qdss_tracedata_b,
+	msm_mux_led0,
+	msm_mux_pwm04,
+	msm_mux_led1,
+	msm_mux_pwm14,
+	msm_mux_led2,
+	msm_mux_pwm24,
+	msm_mux_pwm00,
+	msm_mux_blsp4_uart1,
+	msm_mux_blsp4_i2c1,
+	msm_mux_blsp4_spi1,
+	msm_mux_wci23,
+	msm_mux_mac11,
+	msm_mux_blsp3_spi2,
+	msm_mux_pwm10,
+	msm_mux_pwm20,
+	msm_mux_pwm30,
+	msm_mux_audio_txmclk,
+	msm_mux_pwm02,
+	msm_mux_audio_txbclk,
+	msm_mux_pwm12,
+	msm_mux_audio_txfsync,
+	msm_mux_pwm22,
+	msm_mux_audio_txd,
+	msm_mux_pwm32,
+	msm_mux_audio_rxmclk,
+	msm_mux_pwm03,
+	msm_mux_atest_char0,
+	msm_mux_audio_rxbclk,
+	msm_mux_pwm13,
+	msm_mux_atest_char1,
+	msm_mux_audio_rxfsync,
+	msm_mux_pwm23,
+	msm_mux_atest_char2,
+	msm_mux_audio_rxd,
+	msm_mux_pwm33,
+	msm_mux_atest_char3,
+	msm_mux_pcm_drx,
+	msm_mux_mac10,
+	msm_mux_mac00,
+	msm_mux_pcm_dtx,
+	msm_mux_pcm_fsync,
+	msm_mux_mac20,
+	msm_mux_qdss_traceclk_a,
+	msm_mux_pcm_pclk,
+	msm_mux_qdss_tracectl_a,
+	msm_mux_atest_char,
+	msm_mux_qdss_tracedata_a,
+	msm_mux_blsp0_uart,
+	msm_mux_blsp0_i2c,
+	msm_mux_blsp0_spi,
+	msm_mux_blsp1_uart,
+	msm_mux_blsp1_i2c,
+	msm_mux_blsp1_spi,
+	msm_mux_blsp2_uart,
+	msm_mux_blsp2_i2c,
+	msm_mux_blsp2_spi,
+	msm_mux_blsp3_uart,
+	msm_mux_blsp3_i2c,
+	msm_mux_blsp3_spi,
+	msm_mux_pta2_0,
+	msm_mux_wci21,
+	msm_mux_cxc1,
+	msm_mux_blsp3_spi1,
+	msm_mux_pta2_1,
+	msm_mux_pta2_2,
+	msm_mux_pcie0_clk,
+	msm_mux_dbg_out,
+	msm_mux_cri_trng0,
+	msm_mux_pcie0_rst,
+	msm_mux_cri_trng1,
+	msm_mux_pcie0_wake,
+	msm_mux_cri_trng,
+	msm_mux_pcie1_clk,
+	msm_mux_rx2,
+	msm_mux_ldo_update,
+	msm_mux_pcie1_rst,
+	msm_mux_ldo_en,
+	msm_mux_pcie1_wake,
+	msm_mux_gcc_plltest,
+	msm_mux_sd_card,
+	msm_mux_pwm01,
+	msm_mux_pta1_1,
+	msm_mux_pwm11,
+	msm_mux_rx1,
+	msm_mux_pta1_2,
+	msm_mux_gcc_tlmm,
+	msm_mux_pta1_0,
+	msm_mux_pwm21,
+	msm_mux_prng_rosc,
+	msm_mux_sd_write,
+	msm_mux_pwm31,
+	msm_mux_rx0,
+	msm_mux_tsens_max,
+	msm_mux_mdc,
+	msm_mux_mdio,
+	msm_mux_NA,
+};
+
+static const char * const qpic_pad_groups[] = {
+	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio9", "gpio10",
+	"gpio11", "gpio17",
+};
+
+static const char * const _groups[] = {
+	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
+};
+
+static const char * const blsp5_i2c_groups[] = {
+	"gpio0", "gpio2",
+};
+
+static const char * const blsp5_spi_groups[] = {
+	"gpio0", "gpio2", "gpio9", "gpio16",
+};
+
+static const char * const wci20_groups[] = {
+	"gpio0", "gpio2",
+};
+
+static const char * const blsp3_spi3_groups[] = {
+	"gpio0", "gpio2", "gpio9",
+};
+
+static const char * const burn0_groups[] = {
+	"gpio0",
+};
+
+static const char * const pcm_zsi0_groups[] = {
+	"gpio1",
+};
+
+static const char * const blsp5_uart_groups[] = {
+	"gpio0", "gpio2", "gpio9", "gpio16",
+};
+
+static const char * const mac12_groups[] = {
+	"gpio1", "gpio11",
+};
+
+static const char * const blsp3_spi0_groups[] = {
+	"gpio1", "gpio3", "gpio4",
+};
+
+static const char * const burn1_groups[] = {
+	"gpio1",
+};
+
+static const char * const mac01_groups[] = {
+	"gpio3", "gpio4",
+};
+
+static const char * const qdss_cti_trig_out_b0_groups[] = {
+	"gpio3",
+};
+
+static const char * const qdss_cti_trig_in_b0_groups[] = {
+	"gpio4",
+};
+
+static const char * const qpic_pad4_groups[] = {
+	"gpio5",
+};
+
+static const char * const blsp4_uart0_groups[] = {
+	"gpio5", "gpio6", "gpio7", "gpio8",
+};
+
+static const char * const blsp4_i2c0_groups[] = {
+	"gpio5", "gpio6",
+};
+
+static const char * const blsp4_spi0_groups[] = {
+	"gpio5", "gpio6", "gpio7", "gpio8",
+};
+
+static const char * const mac21_groups[] = {
+	"gpio5", "gpio6",
+};
+
+static const char * const qdss_cti_trig_out_b1_groups[] = {
+	"gpio5",
+};
+
+static const char * const qpic_pad5_groups[] = {
+	"gpio6",
+};
+
+static const char * const qdss_cti_trig_in_b1_groups[] = {
+	"gpio6",
+};
+
+static const char * const qpic_pad6_groups[] = {
+	"gpio7",
+};
+
+static const char * const qpic_pad7_groups[] = {
+	"gpio8",
+};
+
+static const char * const cxc0_groups[] = {
+	"gpio9", "gpio16",
+};
+
+static const char * const mac13_groups[] = {
+	"gpio9", "gpio16",
+};
+
+static const char * const qdss_cti_trig_in_a1_groups[] = {
+	"gpio9",
+};
+
+static const char * const qdss_cti_trig_out_a1_groups[] = {
+	"gpio10",
+};
+
+static const char * const wci22_groups[] = {
+	"gpio11", "gpio17",
+};
+
+static const char * const qdss_cti_trig_in_a0_groups[] = {
+	"gpio11",
+};
+
+static const char * const qpic_pad1_groups[] = {
+	"gpio12",
+};
+
+static const char * const qdss_cti_trig_out_a0_groups[] = {
+	"gpio12",
+};
+
+static const char * const qpic_pad2_groups[] = {
+	"gpio13",
+};
+
+static const char * const qpic_pad3_groups[] = {
+	"gpio14",
+};
+
+static const char * const qdss_traceclk_b_groups[] = {
+	"gpio14",
+};
+
+static const char * const qpic_pad0_groups[] = {
+	"gpio15",
+};
+
+static const char * const qdss_tracectl_b_groups[] = {
+	"gpio15",
+};
+
+static const char * const qpic_pad8_groups[] = {
+	"gpio16",
+};
+
+static const char * const pcm_zsi1_groups[] = {
+	"gpio16",
+};
+
+static const char * const qdss_tracedata_b_groups[] = {
+	"gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21", "gpio22",
+	"gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28", "gpio29",
+	"gpio30", "gpio31",
+};
+
+static const char * const led0_groups[] = {
+	"gpio18",
+};
+
+static const char * const pwm04_groups[] = {
+	"gpio18",
+};
+
+static const char * const led1_groups[] = {
+	"gpio19",
+};
+
+static const char * const pwm14_groups[] = {
+	"gpio19",
+};
+
+static const char * const led2_groups[] = {
+	"gpio20",
+};
+
+static const char * const pwm24_groups[] = {
+	"gpio20",
+};
+
+static const char * const pwm00_groups[] = {
+	"gpio21",
+};
+
+static const char * const blsp4_uart1_groups[] = {
+	"gpio21", "gpio22", "gpio23", "gpio24",
+};
+
+static const char * const blsp4_i2c1_groups[] = {
+	"gpio21", "gpio22",
+};
+
+static const char * const blsp4_spi1_groups[] = {
+	"gpio21", "gpio22", "gpio23", "gpio24",
+};
+
+static const char * const wci23_groups[] = {
+	"gpio21", "gpio22",
+};
+
+static const char * const mac11_groups[] = {
+	"gpio21", "gpio22",
+};
+
+static const char * const blsp3_spi2_groups[] = {
+	"gpio21", "gpio22", "gpio23",
+};
+
+static const char * const pwm10_groups[] = {
+	"gpio22",
+};
+
+static const char * const pwm20_groups[] = {
+	"gpio23",
+};
+
+static const char * const pwm30_groups[] = {
+	"gpio24",
+};
+
+static const char * const audio_txmclk_groups[] = {
+	"gpio25",
+};
+
+static const char * const pwm02_groups[] = {
+	"gpio25",
+};
+
+static const char * const audio_txbclk_groups[] = {
+	"gpio26",
+};
+
+static const char * const pwm12_groups[] = {
+	"gpio26",
+};
+
+static const char * const audio_txfsync_groups[] = {
+	"gpio27",
+};
+
+static const char * const pwm22_groups[] = {
+	"gpio27",
+};
+
+static const char * const audio_txd_groups[] = {
+	"gpio28",
+};
+
+static const char * const pwm32_groups[] = {
+	"gpio28",
+};
+
+static const char * const audio_rxmclk_groups[] = {
+	"gpio29",
+};
+
+static const char * const pwm03_groups[] = {
+	"gpio29",
+};
+
+static const char * const atest_char0_groups[] = {
+	"gpio29",
+};
+
+static const char * const audio_rxbclk_groups[] = {
+	"gpio30",
+};
+
+static const char * const pwm13_groups[] = {
+	"gpio30",
+};
+
+static const char * const atest_char1_groups[] = {
+	"gpio30",
+};
+
+static const char * const audio_rxfsync_groups[] = {
+	"gpio31",
+};
+
+static const char * const pwm23_groups[] = {
+	"gpio31",
+};
+
+static const char * const atest_char2_groups[] = {
+	"gpio31",
+};
+
+static const char * const audio_rxd_groups[] = {
+	"gpio32",
+};
+
+static const char * const pwm33_groups[] = {
+	"gpio32",
+};
+
+static const char * const atest_char3_groups[] = {
+	"gpio32",
+};
+
+static const char * const pcm_drx_groups[] = {
+	"gpio33",
+};
+
+static const char * const mac10_groups[] = {
+	"gpio33", "gpio34",
+};
+
+static const char * const mac00_groups[] = {
+	"gpio33", "gpio34",
+};
+
+static const char * const pcm_dtx_groups[] = {
+	"gpio34",
+};
+
+static const char * const pcm_fsync_groups[] = {
+	"gpio35",
+};
+
+static const char * const mac20_groups[] = {
+	"gpio35", "gpio36",
+};
+
+static const char * const qdss_traceclk_a_groups[] = {
+	"gpio35",
+};
+
+static const char * const pcm_pclk_groups[] = {
+	"gpio36",
+};
+
+static const char * const qdss_tracectl_a_groups[] = {
+	"gpio36",
+};
+
+static const char * const atest_char_groups[] = {
+	"gpio37",
+};
+
+static const char * const qdss_tracedata_a_groups[] = {
+	"gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42", "gpio43",
+	"gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49", "gpio50",
+	"gpio51", "gpio52",
+};
+
+static const char * const blsp0_uart_groups[] = {
+	"gpio38", "gpio39", "gpio40", "gpio41",
+};
+
+static const char * const blsp0_i2c_groups[] = {
+	"gpio38", "gpio39",
+};
+
+static const char * const blsp0_spi_groups[] = {
+	"gpio38", "gpio39", "gpio40", "gpio41",
+};
+
+static const char * const blsp1_uart_groups[] = {
+	"gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const blsp1_i2c_groups[] = {
+	"gpio42", "gpio43",
+};
+
+static const char * const blsp1_spi_groups[] = {
+	"gpio42", "gpio43", "gpio44", "gpio45",
+};
+
+static const char * const blsp2_uart_groups[] = {
+	"gpio46", "gpio47", "gpio48", "gpio49",
+};
+
+static const char * const blsp2_i2c_groups[] = {
+	"gpio46", "gpio47",
+};
+
+static const char * const blsp2_spi_groups[] = {
+	"gpio46", "gpio47", "gpio48", "gpio49",
+};
+
+static const char * const blsp3_uart_groups[] = {
+	"gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char * const blsp3_i2c_groups[] = {
+	"gpio50", "gpio51",
+};
+
+static const char * const blsp3_spi_groups[] = {
+	"gpio50", "gpio51", "gpio52", "gpio53",
+};
+
+static const char * const pta2_0_groups[] = {
+	"gpio54",
+};
+
+static const char * const wci21_groups[] = {
+	"gpio54", "gpio56",
+};
+
+static const char * const cxc1_groups[] = {
+	"gpio54", "gpio56",
+};
+
+static const char * const blsp3_spi1_groups[] = {
+	"gpio54", "gpio55", "gpio56",
+};
+
+static const char * const pta2_1_groups[] = {
+	"gpio55",
+};
+
+static const char * const pta2_2_groups[] = {
+	"gpio56",
+};
+
+static const char * const pcie0_clk_groups[] = {
+	"gpio57",
+};
+
+static const char * const dbg_out_groups[] = {
+	"gpio57",
+};
+
+static const char * const cri_trng0_groups[] = {
+	"gpio57",
+};
+
+static const char * const pcie0_rst_groups[] = {
+	"gpio58",
+};
+
+static const char * const cri_trng1_groups[] = {
+	"gpio58",
+};
+
+static const char * const pcie0_wake_groups[] = {
+	"gpio59",
+};
+
+static const char * const cri_trng_groups[] = {
+	"gpio59",
+};
+
+static const char * const pcie1_clk_groups[] = {
+	"gpio60",
+};
+
+static const char * const rx2_groups[] = {
+	"gpio60",
+};
+
+static const char * const ldo_update_groups[] = {
+	"gpio60",
+};
+
+static const char * const pcie1_rst_groups[] = {
+	"gpio61",
+};
+
+static const char * const ldo_en_groups[] = {
+	"gpio61",
+};
+
+static const char * const pcie1_wake_groups[] = {
+	"gpio62",
+};
+
+static const char * const gcc_plltest_groups[] = {
+	"gpio62", "gpio63",
+};
+
+static const char * const sd_card_groups[] = {
+	"gpio63",
+};
+
+static const char * const pwm01_groups[] = {
+	"gpio63",
+};
+
+static const char * const pta1_1_groups[] = {
+	"gpio64",
+};
+
+static const char * const pwm11_groups[] = {
+	"gpio64",
+};
+
+static const char * const rx1_groups[] = {
+	"gpio64",
+};
+
+static const char * const pta1_2_groups[] = {
+	"gpio65",
+};
+
+static const char * const gcc_tlmm_groups[] = {
+	"gpio65",
+};
+
+static const char * const pta1_0_groups[] = {
+	"gpio66",
+};
+
+static const char * const pwm21_groups[] = {
+	"gpio66",
+};
+
+static const char * const prng_rosc_groups[] = {
+	"gpio66",
+};
+
+static const char * const sd_write_groups[] = {
+	"gpio67",
+};
+
+static const char * const pwm31_groups[] = {
+	"gpio67",
+};
+
+static const char * const rx0_groups[] = {
+	"gpio67",
+};
+
+static const char * const tsens_max_groups[] = {
+	"gpio67",
+};
+
+static const char * const mdc_groups[] = {
+	"gpio68",
+};
+
+static const char * const mdio_groups[] = {
+	"gpio69",
+};
+
+static const char * const gpio_groups[] = {
+	"gpio0", "gpio1", "gpio2", "gpio3", "gpio4", "gpio5", "gpio6", "gpio7",
+	"gpio8", "gpio9", "gpio10", "gpio11", "gpio12", "gpio13", "gpio14",
+	"gpio15", "gpio16", "gpio17", "gpio18", "gpio19", "gpio20", "gpio21",
+	"gpio22", "gpio23", "gpio24", "gpio25", "gpio26", "gpio27", "gpio28",
+	"gpio29", "gpio30", "gpio31", "gpio32", "gpio33", "gpio34", "gpio35",
+	"gpio36", "gpio37", "gpio38", "gpio39", "gpio40", "gpio41", "gpio42",
+	"gpio43", "gpio44", "gpio45", "gpio46", "gpio47", "gpio48", "gpio49",
+	"gpio50", "gpio51", "gpio52", "gpio53", "gpio54", "gpio55", "gpio56",
+	"gpio57", "gpio58", "gpio59", "gpio60", "gpio61", "gpio62", "gpio63",
+	"gpio64", "gpio65", "gpio66", "gpio67", "gpio68", "gpio69",
+};
+
+static const struct msm_function ipq8074_functions[] = {
+	FUNCTION(gpio),
+	FUNCTION(qpic_pad),
+	FUNCTION(blsp5_i2c),
+	FUNCTION(blsp5_spi),
+	FUNCTION(wci20),
+	FUNCTION(blsp3_spi3),
+	FUNCTION(burn0),
+	FUNCTION(pcm_zsi0),
+	FUNCTION(blsp5_uart),
+	FUNCTION(mac12),
+	FUNCTION(blsp3_spi0),
+	FUNCTION(burn1),
+	FUNCTION(mac01),
+	FUNCTION(qdss_cti_trig_out_b0),
+	FUNCTION(qdss_cti_trig_in_b0),
+	FUNCTION(qpic_pad4),
+	FUNCTION(blsp4_uart0),
+	FUNCTION(blsp4_i2c0),
+	FUNCTION(blsp4_spi0),
+	FUNCTION(mac21),
+	FUNCTION(qdss_cti_trig_out_b1),
+	FUNCTION(qpic_pad5),
+	FUNCTION(qdss_cti_trig_in_b1),
+	FUNCTION(qpic_pad6),
+	FUNCTION(qpic_pad7),
+	FUNCTION(cxc0),
+	FUNCTION(mac13),
+	FUNCTION(qdss_cti_trig_in_a1),
+	FUNCTION(qdss_cti_trig_out_a1),
+	FUNCTION(wci22),
+	FUNCTION(qdss_cti_trig_in_a0),
+	FUNCTION(qpic_pad1),
+	FUNCTION(qdss_cti_trig_out_a0),
+	FUNCTION(qpic_pad2),
+	FUNCTION(qpic_pad3),
+	FUNCTION(qdss_traceclk_b),
+	FUNCTION(qpic_pad0),
+	FUNCTION(qdss_tracectl_b),
+	FUNCTION(qpic_pad8),
+	FUNCTION(pcm_zsi1),
+	FUNCTION(qdss_tracedata_b),
+	FUNCTION(led0),
+	FUNCTION(pwm04),
+	FUNCTION(led1),
+	FUNCTION(pwm14),
+	FUNCTION(led2),
+	FUNCTION(pwm24),
+	FUNCTION(pwm00),
+	FUNCTION(blsp4_uart1),
+	FUNCTION(blsp4_i2c1),
+	FUNCTION(blsp4_spi1),
+	FUNCTION(wci23),
+	FUNCTION(mac11),
+	FUNCTION(blsp3_spi2),
+	FUNCTION(pwm10),
+	FUNCTION(pwm20),
+	FUNCTION(pwm30),
+	FUNCTION(audio_txmclk),
+	FUNCTION(pwm02),
+	FUNCTION(audio_txbclk),
+	FUNCTION(pwm12),
+	FUNCTION(audio_txfsync),
+	FUNCTION(pwm22),
+	FUNCTION(audio_txd),
+	FUNCTION(pwm32),
+	FUNCTION(audio_rxmclk),
+	FUNCTION(pwm03),
+	FUNCTION(atest_char0),
+	FUNCTION(audio_rxbclk),
+	FUNCTION(pwm13),
+	FUNCTION(atest_char1),
+	FUNCTION(audio_rxfsync),
+	FUNCTION(pwm23),
+	FUNCTION(atest_char2),
+	FUNCTION(audio_rxd),
+	FUNCTION(pwm33),
+	FUNCTION(atest_char3),
+	FUNCTION(pcm_drx),
+	FUNCTION(mac10),
+	FUNCTION(mac00),
+	FUNCTION(pcm_dtx),
+	FUNCTION(pcm_fsync),
+	FUNCTION(mac20),
+	FUNCTION(qdss_traceclk_a),
+	FUNCTION(pcm_pclk),
+	FUNCTION(qdss_tracectl_a),
+	FUNCTION(atest_char),
+	FUNCTION(qdss_tracedata_a),
+	FUNCTION(blsp0_uart),
+	FUNCTION(blsp0_i2c),
+	FUNCTION(blsp0_spi),
+	FUNCTION(blsp1_uart),
+	FUNCTION(blsp1_i2c),
+	FUNCTION(blsp1_spi),
+	FUNCTION(blsp2_uart),
+	FUNCTION(blsp2_i2c),
+	FUNCTION(blsp2_spi),
+	FUNCTION(blsp3_uart),
+	FUNCTION(blsp3_i2c),
+	FUNCTION(blsp3_spi),
+	FUNCTION(pta2_0),
+	FUNCTION(wci21),
+	FUNCTION(cxc1),
+	FUNCTION(blsp3_spi1),
+	FUNCTION(pta2_1),
+	FUNCTION(pta2_2),
+	FUNCTION(pcie0_clk),
+	FUNCTION(dbg_out),
+	FUNCTION(cri_trng0),
+	FUNCTION(pcie0_rst),
+	FUNCTION(cri_trng1),
+	FUNCTION(pcie0_wake),
+	FUNCTION(cri_trng),
+	FUNCTION(pcie1_clk),
+	FUNCTION(rx2),
+	FUNCTION(ldo_update),
+	FUNCTION(pcie1_rst),
+	FUNCTION(ldo_en),
+	FUNCTION(pcie1_wake),
+	FUNCTION(gcc_plltest),
+	FUNCTION(sd_card),
+	FUNCTION(pwm01),
+	FUNCTION(pta1_1),
+	FUNCTION(pwm11),
+	FUNCTION(rx1),
+	FUNCTION(pta1_2),
+	FUNCTION(gcc_tlmm),
+	FUNCTION(pta1_0),
+	FUNCTION(pwm21),
+	FUNCTION(prng_rosc),
+	FUNCTION(sd_write),
+	FUNCTION(pwm31),
+	FUNCTION(rx0),
+	FUNCTION(tsens_max),
+	FUNCTION(mdc),
+	FUNCTION(mdio),
+};
+
+static const struct msm_pingroup ipq8074_groups[] = {
+	PINGROUP(0, qpic_pad, blsp5_uart, blsp5_i2c, blsp5_spi, wci20,
+		 blsp3_spi3, NA, burn0, NA),
+	PINGROUP(1, qpic_pad, pcm_zsi0, mac12, blsp3_spi0, NA, burn1, NA, NA,
+		 NA),
+	PINGROUP(2, qpic_pad, blsp5_uart, blsp5_i2c, blsp5_spi, wci20,
+		 blsp3_spi3, NA, NA, NA),
+	PINGROUP(3, qpic_pad, mac01, blsp3_spi0, qdss_cti_trig_out_b0, NA, NA,
+		 NA, NA, NA),
+	PINGROUP(4, qpic_pad, mac01, blsp3_spi0, qdss_cti_trig_in_b0, NA, NA,
+		 NA, NA, NA),
+	PINGROUP(5, qpic_pad4, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+		 qdss_cti_trig_out_b1, NA, NA, NA),
+	PINGROUP(6, qpic_pad5, blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+		 qdss_cti_trig_in_b1, NA, NA, NA),
+	PINGROUP(7, qpic_pad6, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA),
+	PINGROUP(8, qpic_pad7, blsp4_uart0, blsp4_spi0, NA, NA, NA, NA, NA, NA),
+	PINGROUP(9, qpic_pad, blsp5_uart, blsp5_spi, cxc0, mac13, blsp3_spi3,
+		 qdss_cti_trig_in_a1, NA, NA),
+	PINGROUP(10, qpic_pad, qdss_cti_trig_out_a1, NA, NA, NA, NA, NA, NA,
+		 NA),
+	PINGROUP(11, qpic_pad, wci22, mac12, qdss_cti_trig_in_a0, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(12, qpic_pad1, qdss_cti_trig_out_a0, NA, NA, NA, NA, NA, NA,
+		 NA),
+	PINGROUP(13, qpic_pad2, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(14, qpic_pad3, qdss_traceclk_b, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(15, qpic_pad0, qdss_tracectl_b, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(16, qpic_pad8, blsp5_uart, pcm_zsi1, blsp5_spi, cxc0, mac13,
+		 qdss_tracedata_b, NA, NA),
+	PINGROUP(17, qpic_pad, wci22, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
+	PINGROUP(18, led0, pwm04, qdss_tracedata_b, NA, NA, NA, NA, NA, NA),
+	PINGROUP(19, led1, pwm14, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
+	PINGROUP(20, led2, pwm24, NA, qdss_tracedata_b, NA, NA, NA, NA, NA),
+	PINGROUP(21, pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+		 blsp3_spi2, NA, qdss_tracedata_b),
+	PINGROUP(22, pwm10, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+		 blsp3_spi2, NA, qdss_tracedata_b),
+	PINGROUP(23, pwm20, blsp4_uart1, blsp4_spi1, blsp3_spi2, NA,
+		 qdss_tracedata_b, NA, NA, NA),
+	PINGROUP(24, pwm30, blsp4_uart1, blsp4_spi1, NA, qdss_tracedata_b, NA,
+		 NA, NA, NA),
+	PINGROUP(25, audio_txmclk, pwm02, NA, qdss_tracedata_b, NA, NA, NA, NA,
+		 NA),
+	PINGROUP(26, audio_txbclk, pwm12, NA, qdss_tracedata_b, NA, NA, NA, NA,
+		 NA),
+	PINGROUP(27, audio_txfsync, pwm22, NA, qdss_tracedata_b, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(28, audio_txd, pwm32, NA, qdss_tracedata_b, NA, NA, NA, NA,
+		 NA),
+	PINGROUP(29, audio_rxmclk, pwm03, atest_char0, NA, qdss_tracedata_b,
+		 NA, NA, NA, NA),
+	PINGROUP(30, audio_rxbclk, pwm13, atest_char1, NA, qdss_tracedata_b,
+		 NA, NA, NA, NA),
+	PINGROUP(31, audio_rxfsync, pwm23, atest_char2, NA, qdss_tracedata_b,
+		 NA, NA, NA, NA),
+	PINGROUP(32, audio_rxd, pwm33, atest_char3, NA, NA, NA, NA, NA, NA),
+	PINGROUP(33, pcm_drx, mac10, mac00, NA, NA, NA, NA, NA, NA),
+	PINGROUP(34, pcm_dtx, mac10, mac00, NA, NA, NA, NA, NA, NA),
+	PINGROUP(35, pcm_fsync, mac20, qdss_traceclk_a, NA, NA, NA, NA, NA, NA),
+	PINGROUP(36, pcm_pclk, mac20, NA, qdss_tracectl_a, NA, NA, NA, NA, NA),
+	PINGROUP(37, atest_char, NA, qdss_tracedata_a, NA, NA, NA, NA, NA, NA),
+	PINGROUP(38, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a,
+		 NA, NA, NA, NA),
+	PINGROUP(39, blsp0_uart, blsp0_i2c, blsp0_spi, NA, qdss_tracedata_a,
+		 NA, NA, NA, NA),
+	PINGROUP(40, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(41, blsp0_uart, blsp0_spi, NA, qdss_tracedata_a, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(42, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a,
+		 NA, NA, NA, NA),
+	PINGROUP(43, blsp1_uart, blsp1_i2c, blsp1_spi, NA, qdss_tracedata_a,
+		 NA, NA, NA, NA),
+	PINGROUP(44, blsp1_uart, blsp1_spi, NA, qdss_tracedata_a, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(45, blsp1_uart, blsp1_spi, qdss_tracedata_a, NA, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(46, blsp2_uart, blsp2_i2c, blsp2_spi, qdss_tracedata_a, NA,
+		 NA, NA, NA, NA),
+	PINGROUP(47, blsp2_uart, blsp2_i2c, blsp2_spi, NA, qdss_tracedata_a,
+		 NA, NA, NA, NA),
+	PINGROUP(48, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(49, blsp2_uart, blsp2_spi, NA, qdss_tracedata_a, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(50, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a,
+		 NA, NA, NA, NA),
+	PINGROUP(51, blsp3_uart, blsp3_i2c, blsp3_spi, NA, qdss_tracedata_a,
+		 NA, NA, NA, NA),
+	PINGROUP(52, blsp3_uart, blsp3_spi, NA, qdss_tracedata_a, NA, NA, NA,
+		 NA, NA),
+	PINGROUP(53, blsp3_uart, blsp3_spi, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(54, pta2_0, wci21, cxc1, blsp3_spi1, NA, NA, NA, NA, NA),
+	PINGROUP(55, pta2_1, blsp3_spi1, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(56, pta2_2, wci21, cxc1, blsp3_spi1, NA, NA, NA, NA, NA),
+	PINGROUP(57, pcie0_clk, NA, dbg_out, cri_trng0, NA, NA, NA, NA, NA),
+	PINGROUP(58, pcie0_rst, NA, cri_trng1, NA, NA, NA, NA, NA, NA),
+	PINGROUP(59, pcie0_wake, NA, cri_trng, NA, NA, NA, NA, NA, NA),
+	PINGROUP(60, pcie1_clk, rx2, ldo_update, NA, NA, NA, NA, NA, NA),
+	PINGROUP(61, pcie1_rst, ldo_en, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(62, pcie1_wake, gcc_plltest, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(63, sd_card, pwm01, NA, gcc_plltest, NA, NA, NA, NA, NA),
+	PINGROUP(64, pta1_1, pwm11, NA, rx1, NA, NA, NA, NA, NA),
+	PINGROUP(65, pta1_2, NA, gcc_tlmm, NA, NA, NA, NA, NA, NA),
+	PINGROUP(66, pta1_0, pwm21, prng_rosc, NA, NA, NA, NA, NA, NA),
+	PINGROUP(67, sd_write, pwm31, rx0, tsens_max, NA, NA, NA, NA, NA),
+	PINGROUP(68, mdc, NA, NA, NA, NA, NA, NA, NA, NA),
+	PINGROUP(69, mdio, NA, NA, NA, NA, NA, NA, NA, NA),
+};
+
+static const struct msm_pinctrl_soc_data ipq8074_pinctrl = {
+	.pins = ipq8074_pins,
+	.npins = ARRAY_SIZE(ipq8074_pins),
+	.functions = ipq8074_functions,
+	.nfunctions = ARRAY_SIZE(ipq8074_functions),
+	.groups = ipq8074_groups,
+	.ngroups = ARRAY_SIZE(ipq8074_groups),
+	.ngpios = 70,
+};
+
+static int ipq8074_pinctrl_probe(struct platform_device *pdev)
+{
+	return msm_pinctrl_probe(pdev, &ipq8074_pinctrl);
+}
+
+static const struct of_device_id ipq8074_pinctrl_of_match[] = {
+	{ .compatible = "qcom,ipq8074-pinctrl", },
+	{ },
+};
+
+static struct platform_driver ipq8074_pinctrl_driver = {
+	.driver = {
+		.name = "ipq8074-pinctrl",
+		.of_match_table = ipq8074_pinctrl_of_match,
+	},
+	.probe = ipq8074_pinctrl_probe,
+	.remove = msm_pinctrl_remove,
+};
+
+static int __init ipq8074_pinctrl_init(void)
+{
+	return platform_driver_register(&ipq8074_pinctrl_driver);
+}
+arch_initcall(ipq8074_pinctrl_init);
+
+static void __exit ipq8074_pinctrl_exit(void)
+{
+	platform_driver_unregister(&ipq8074_pinctrl_driver);
+}
+module_exit(ipq8074_pinctrl_exit);
+
+MODULE_DESCRIPTION("Qualcomm ipq8074 pinctrl driver");
+MODULE_LICENSE("GPL v2");
+MODULE_DEVICE_TABLE(of, ipq8074_pinctrl_of_match);

Add initial pinctrl driver to support pin configuration with pinctrl framework for ipq8074.

Signed-off-by Manoharan Vijaya Raghavan <[email protected]>

Signed-off-by Varadarajan Narayanan <[email protected]>

---
 .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt      |  187 +++

 drivers/pinctrl/qcom/Kconfig                       |   10 +
 drivers/pinctrl/qcom/Makefile                      |    1 +
 drivers/pinctrl/qcom/pinctrl-ipq8074.c             | 1217 ++++++++++++++++++++
 4 files changed, 1415 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c

Add initial pinctrl driver to support pin configuration with pinctrl framework for ipq8074.

Signed-off-by Manoharan Vijaya Raghavan <[email protected]>

Signed-off-by Varadarajan Narayanan <[email protected]>

---
 .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt      |  187 +++
 drivers/pinctrl/qcom/Kconfig                       |   10 +
 drivers/pinctrl/qcom/Makefile                      |    1 +
 drivers/pinctrl/qcom/pinctrl-ipq8074.c             | 1217 ++++++++++++++++++++
 4 files changed, 1415 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt
 create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +0 -0

+- pins:

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +6 -0

+	Usage: required
+	Value type: <string-array>
+	Definition: List of gpio pins affected by the properties specified in
+		    this subnode.  Valid pins are:
+		    gpio0-gpio121,
+		    sdc1_clk,

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +23 -0

+
+- function:
+	Usage: required
+	Value type: <string>
+	Definition: Specify the alternative function to be configured for the
+		    specified pins. Functions are only valid for gpio pins.
+		    Valid values are:
+	gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
+	burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
+	qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
+	blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+	qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
+	qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
+	qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
+	qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
+	qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
+	qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
+	pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+	blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
+	audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
+	audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
+	atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
+	pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,

+

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +7 -0

+
+- drive-strength:
+	Usage: optional
+	Value type: <u32>
+	Definition: Selects the drive strength for the specified pins, in mA.
+		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+

drivers/pinctrl/qcom/pinctrl-ipq8074.c +0 -0

drivers/pinctrl/qcom/pinctrl-ipq8074.c +17 -0

+	msm_mux_blsp4_uart0,
+	msm_mux_blsp4_i2c0,
+	msm_mux_blsp4_spi0,
+	msm_mux_mac21,
+	msm_mux_qdss_cti_trig_out_b1,
+	msm_mux_qpic_pad5,
+	msm_mux_qdss_cti_trig_in_b1,
+	msm_mux_qpic_pad6,
+	msm_mux_qpic_pad7,
+	msm_mux_cxc0,
+	msm_mux_mac13,
+	msm_mux_qdss_cti_trig_in_a1,
+	msm_mux_qdss_cti_trig_out_a1,
+	msm_mux_wci22,
+	msm_mux_qdss_cti_trig_in_a0,
+	msm_mux_qpic_pad1,
+	msm_mux_qdss_cti_trig_out_a0,

+static const struct msm_function ipq8074_functions[] = {

Quoted 15 lines · Varadarajan Narayanan

Add initial pinctrl driver to support pin configuration with pinctrl framework for ipq8074.

Signed-off-by Manoharan Vijaya Raghavan <[email protected]>

Signed-off-by Varadarajan Narayanan <[email protected]>

---
  .../bindings/pinctrl/qcom,ipq8074-pinctrl.txt      |  187 +++
  drivers/pinctrl/qcom/Kconfig                       |   10 +
  drivers/pinctrl/qcom/Makefile                      |    1 +
  drivers/pinctrl/qcom/pinctrl-ipq8074.c             | 1217 ++++++++++++++++++++
  4 files changed, 1415 insertions(+)

create mode 100644 Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt create mode 100644 drivers/pinctrl/qcom/pinctrl-ipq8074.c

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +0 -0

[..]

Quoted 11 lines

+- pins:

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +10 -0

+	Usage: required
+	Value type: <string-array>
+	Definition: List of gpio pins affected by the properties specified in
+		    this subnode.  Valid pins are:
+		    gpio0-gpio121,
+		    sdc1_clk,
+		    sdc1_cmd,
+		    sdc1_data
+		    sdc2_clk,
+		    sdc2_cmd,

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt line 88

Quoted 6 lines

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +6 -0

+		    sdc2_data,
+		    qdsd_cmd,
+		    qdsd_data0,
+		    qdsd_data1,
+		    qdsd_data2,
+		    qdsd_data3

These doesn't match the implementation.

Quoted 27 lines

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +27 -0

+
+- function:
+	Usage: required
+	Value type: <string>
+	Definition: Specify the alternative function to be configured for the
+		    specified pins. Functions are only valid for gpio pins.
+		    Valid values are:
+	gpio, qpic_pad, blsp5_i2c, blsp5_spi, wci20, blsp3_spi3,
+	burn0, pcm_zsi0, blsp5_uart, mac12, blsp3_spi0, burn1, mac01,
+	qdss_cti_trig_out_b0, qdss_cti_trig_in_b0, qpic_pad4,
+	blsp4_uart0, blsp4_i2c0, blsp4_spi0, mac21,
+	qdss_cti_trig_out_b1, qpic_pad5, qdss_cti_trig_in_b1,
+	qpic_pad6, qpic_pad7, cxc0, mac13, qdss_cti_trig_in_a1,
+	qdss_cti_trig_out_a1, wci22, qdss_cti_trig_in_a0, qpic_pad1,
+	qdss_cti_trig_out_a0, qpic_pad2, qpic_pad3, qdss_traceclk_b,
+	qpic_pad0, qdss_tracectl_b, qpic_pad8, pcm_zsi1,
+	qdss_tracedata_b, led0, pwm04, led1, pwm14, led2, pwm24,
+	pwm00, blsp4_uart1, blsp4_i2c1, blsp4_spi1, wci23, mac11,
+	blsp3_spi2, pwm10, pwm20, pwm30, audio_txmclk, pwm02,
+	audio_txbclk, pwm12, audio_txfsync, pwm22, audio_txd, pwm32,
+	audio_rxmclk, pwm03, atest_char0, audio_rxbclk, pwm13,
+	atest_char1, audio_rxfsync, pwm23, atest_char2, audio_rxd,
+	pwm33, atest_char3, pcm_drx, mac10, mac00, pcm_dtx, pcm_fsync,
+	mac20, qdss_traceclk_a, pcm_pclk, qdss_tracectl_a, atest_char,
+	qdss_tracedata_a, blsp0_uart, blsp0_i2c, blsp0_spi,
+	blsp1_uart, blsp1_i2c, blsp1_spi, blsp2_uart, blsp2_i2c,
+	blsp2_spi, blsp3_uart, blsp3_i2c, blsp3_spi, pta2_0, wci21,

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt line 121

Quoted 6 lines

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +6 -0

+	cxc1, blsp3_spi1, pta2_1, pta2_2, pcie0_clk, dbg_out,
+	cri_trng0, pcie0_rst, cri_trng1, pcie0_wake, cri_trng,
+	pcie1_clk, rx2, ldo_update, pcie1_rst, ldo_en, pcie1_wake,
+	gcc_plltest, sd_card, pwm01, pta1_1, pwm11, rx1, pta1_2,
+	gcc_tlmm, pta1_0, pwm21, prng_rosc, sd_write, pwm31, rx0,
+	tsens_max, mdc, mdio, NA

Please indent these to the same level as the description.

Quoted 1 line

+

[..]

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt line 143

Quoted 7 lines

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +7 -0

+
+- output-high:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins are configured in output mode, driven
+		    high.
+		    Not valid for sdc pins.

If you don't have any sdc pins, drop this.

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt line 150

Quoted 7 lines

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +7 -0

+
+- output-low:
+	Usage: optional
+	Value type: <none>
+	Definition: The specified pins are configured in output mode, driven
+		    low.
+		    Not valid for sdc pins.

If you don't have any sdc pins, drop this.

Quoted 7 lines

Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.txt +7 -0

+
+- drive-strength:
+	Usage: optional
+	Value type: <u32>
+	Definition: Selects the drive strength for the specified pins, in mA.
+		    Valid values are: 2, 4, 6, 8, 10, 12, 14 and 16
+

[..]

Quoted 1 line

drivers/pinctrl/qcom/pinctrl-ipq8074.c +0 -0

[..]

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 213

Quoted 2 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c +2 -0

+
+enum ipq8074_functions {

Please keep these sorted alphabetically.

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 218

Quoted 5 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c +5 -0

+	msm_mux_gpio,
+	msm_mux_qpic_pad,
+	msm_mux_blsp5_i2c,
+	msm_mux_blsp5_spi,
+	msm_mux_wci20,

What does "20" mean here?

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 223

Quoted 5 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c +5 -0

+	msm_mux_blsp3_spi3,
+	msm_mux_burn0,
+	msm_mux_pcm_zsi0,
+	msm_mux_blsp5_uart,
+	msm_mux_mac12,

What does "12" mean here?

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 229

Quoted 6 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c +6 -0

+	msm_mux_blsp3_spi0,
+	msm_mux_burn1,
+	msm_mux_mac01,
+	msm_mux_qdss_cti_trig_out_b0,
+	msm_mux_qdss_cti_trig_in_b0,
+	msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions, alternative muxings...?

Quoted 21 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c +21 -0

+	msm_mux_blsp4_uart0,
+	msm_mux_blsp4_i2c0,
+	msm_mux_blsp4_spi0,
+	msm_mux_mac21,
+	msm_mux_qdss_cti_trig_out_b1,
+	msm_mux_qpic_pad5,
+	msm_mux_qdss_cti_trig_in_b1,
+	msm_mux_qpic_pad6,
+	msm_mux_qpic_pad7,
+	msm_mux_cxc0,
+	msm_mux_mac13,
+	msm_mux_qdss_cti_trig_in_a1,
+	msm_mux_qdss_cti_trig_out_a1,
+	msm_mux_wci22,
+	msm_mux_qdss_cti_trig_in_a0,
+	msm_mux_qpic_pad1,
+	msm_mux_qdss_cti_trig_out_a0,
+	msm_mux_qpic_pad2,
+	msm_mux_qpic_pad3,
+	msm_mux_qdss_traceclk_b,
+	msm_mux_qpic_pad0,

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 256

Quoted 6 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c +6 -0

+	msm_mux_qdss_tracectl_b,
+	msm_mux_qpic_pad8,
+	msm_mux_pcm_zsi1,
+	msm_mux_qdss_tracedata_b,
+	msm_mux_led0,
+	msm_mux_pwm04,

What does "04" mean here?

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 262

Quoted 7 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c +6 -0

+	msm_mux_led1,
+	msm_mux_pwm14,
+	msm_mux_led2,
+	msm_mux_pwm24,
+	msm_mux_pwm00,
+	msm_mux_blsp4_uart1,

Are uart0 vs uart1 alternative muxes?

[..]

Quoted 1 line

+static const struct msm_function ipq8074_functions[] = {

Please keep these sorted alphabetically too.

Regards,
Bjorn

Quoted 2 lines · Bjorn Andersson

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

Quoted 3 lines

Quoted 1 line

+enum ipq8074_functions {

Please keep these sorted alphabetically.

Ok

Quoted 7 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 218

Quoted 5 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +5 -0

+	msm_mux_gpio,
+	msm_mux_qpic_pad,
+	msm_mux_blsp5_i2c,
+	msm_mux_blsp5_spi,
+	msm_mux_wci20,

What does "20" mean here?

This is for Wireless Coex Interface. The same functionality can be muxed on to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1 are for the muxing to different GPIOs (alternate muxes).

Quoted 7 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 223

Quoted 5 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +5 -0

+	msm_mux_blsp3_spi3,
+	msm_mux_burn0,
+	msm_mux_pcm_zsi0,
+	msm_mux_blsp5_uart,
+	msm_mux_mac12,

What does "12" mean here?

The SoC has three MAC cores. Each core has two pins for the smart antenna feature. macXY indicates the function select for MAC no. X and smart antenna no. Y.

Quoted 9 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 229

Quoted 6 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +6 -0

+	msm_mux_blsp3_spi0,
+	msm_mux_burn1,
+	msm_mux_mac01,
+	msm_mux_qdss_cti_trig_out_b0,
+	msm_mux_qdss_cti_trig_in_b0,
+	msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions, alternative muxings...?

This is for the NAND and LCD display. The pins listed are the 9 data pins.

Quoted 21 lines

Quoted 21 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +21 -0

+	msm_mux_blsp4_uart0,
+	msm_mux_blsp4_i2c0,
+	msm_mux_blsp4_spi0,
+	msm_mux_mac21,
+	msm_mux_qdss_cti_trig_out_b1,
+	msm_mux_qpic_pad5,
+	msm_mux_qdss_cti_trig_in_b1,
+	msm_mux_qpic_pad6,
+	msm_mux_qpic_pad7,
+	msm_mux_cxc0,
+	msm_mux_mac13,
+	msm_mux_qdss_cti_trig_in_a1,
+	msm_mux_qdss_cti_trig_out_a1,
+	msm_mux_wci22,
+	msm_mux_qdss_cti_trig_in_a0,
+	msm_mux_qpic_pad1,
+	msm_mux_qdss_cti_trig_out_a0,
+	msm_mux_qpic_pad2,
+	msm_mux_qpic_pad3,
+	msm_mux_qdss_traceclk_b,
+	msm_mux_qpic_pad0,

Quoted 8 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 256

Quoted 6 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +6 -0

+	msm_mux_qdss_tracectl_b,
+	msm_mux_qpic_pad8,
+	msm_mux_pcm_zsi1,
+	msm_mux_qdss_tracedata_b,
+	msm_mux_led0,
+	msm_mux_pwm04,

What does "04" mean here?

There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin Y.

Quoted 9 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 262

Quoted 7 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +6 -0

+	msm_mux_led1,
+	msm_mux_pwm14,
+	msm_mux_led2,
+	msm_mux_pwm24,
+	msm_mux_pwm00,
+	msm_mux_blsp4_uart1,

Are uart0 vs uart1 alternative muxes?

These are two different uarts available at two independent pins.

Quoted 3 lines · Varadarajan Narayanan

Quoted 2 lines · Bjorn Andersson

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

[..]

Quoted 14 lines

Quoted 3 lines

Quoted 1 line

+enum ipq8074_functions {

Please keep these sorted alphabetically.

Ok

Quoted 7 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 218

Quoted 5 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +5 -0

+	msm_mux_gpio,
+	msm_mux_qpic_pad,
+	msm_mux_blsp5_i2c,
+	msm_mux_blsp5_spi,
+	msm_mux_wci20,

What does "20" mean here?

Quoted 4 lines

This is for Wireless Coex Interface. The same functionality can be muxed on to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1 are for the muxing to different GPIOs (alternate muxes).

In other Qualcomm platforms the alternative muxes are denoted by letters (a,b,c...). Would you mind picking up this naming scheme, or do you see any problems with that? (E.g. wci2a in this case)

Btw, do you need any additional configuration for selecting alternative muxing or is that automagical these days?

Quoted 8 lines

Quoted 7 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 223

Quoted 5 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +5 -0

+	msm_mux_blsp3_spi3,
+	msm_mux_burn0,
+	msm_mux_pcm_zsi0,
+	msm_mux_blsp5_uart,
+	msm_mux_mac12,

What does "12" mean here?

Quoted 4 lines

The SoC has three MAC cores. Each core has two pins for the smart antenna feature. macXY indicates the function select for MAC no. X and smart antenna no. Y.

Ok

Quoted 10 lines

Quoted 9 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 229

Quoted 6 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +6 -0

+	msm_mux_blsp3_spi0,
+	msm_mux_burn1,
+	msm_mux_mac01,
+	msm_mux_qdss_cti_trig_out_b0,
+	msm_mux_qdss_cti_trig_in_b0,
+	msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions, alternative muxings...?

Quoted 2 lines

This is for the NAND and LCD display. The pins listed are the 9 data pins.

Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's possible to reference a partial group in the DTS, if that's necessary)

Quoted 30 lines

Quoted 29 lines

Quoted 17 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +17 -0

+	msm_mux_blsp4_uart0,
+	msm_mux_blsp4_i2c0,
+	msm_mux_blsp4_spi0,
+	msm_mux_mac21,
+	msm_mux_qdss_cti_trig_out_b1,
+	msm_mux_qpic_pad5,
+	msm_mux_qdss_cti_trig_in_b1,
+	msm_mux_qpic_pad6,
+	msm_mux_qpic_pad7,
+	msm_mux_cxc0,
+	msm_mux_mac13,
+	msm_mux_qdss_cti_trig_in_a1,
+	msm_mux_qdss_cti_trig_out_a1,
+	msm_mux_wci22,
+	msm_mux_qdss_cti_trig_in_a0,
+	msm_mux_qpic_pad1,
+	msm_mux_qdss_cti_trig_out_a0,

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 256

Quoted 10 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +10 -0

+	msm_mux_qpic_pad2,
+	msm_mux_qpic_pad3,
+	msm_mux_qdss_traceclk_b,
+	msm_mux_qpic_pad0,
+	msm_mux_qdss_tracectl_b,
+	msm_mux_qpic_pad8,
+	msm_mux_pcm_zsi1,
+	msm_mux_qdss_tracedata_b,
+	msm_mux_led0,
+	msm_mux_pwm04,

What does "04" mean here?

Quoted 2 lines

There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin Y.

So Y is alternative mux? Can we use letters for this as well?

Quoted 9 lines

Quoted 8 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 262

Quoted 6 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +6 -0

+	msm_mux_led1,
+	msm_mux_pwm14,
+	msm_mux_led2,
+	msm_mux_pwm24,
+	msm_mux_pwm00,
+	msm_mux_blsp4_uart1,

Are uart0 vs uart1 alternative muxes?

Quoted 2 lines

These are two different uarts available at two independent pins.

Ok, then I'm happy with the naming of this :)

Thanks,
Bjorn

Quoted 27 lines · Bjorn Andersson

Quoted 3 lines · Varadarajan Narayanan

Quoted 2 lines · Bjorn Andersson

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

[..]

Quoted 12 lines

Quoted 3 lines

Quoted 1 line

+enum ipq8074_functions {

Please keep these sorted alphabetically.

Ok

Quoted 6 lines

Quoted 5 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +5 -0

+    msm_mux_gpio,
+    msm_mux_qpic_pad,
+    msm_mux_blsp5_i2c,
+    msm_mux_blsp5_spi,
+    msm_mux_wci20,

Quoted 8 lines

Quoted 1 line

What does "20" mean here?

This is for Wireless Coex Interface. The same functionality can be muxed on
to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
are for the muxing to different GPIOs (alternate muxes).

Quoted 3 lines

In other Qualcomm platforms the alternative muxes are denoted by letters (a,b,c...). Would you mind picking up this naming scheme, or do you see any problems with that? (E.g. wci2a in this case)

Ok

Quoted 2 lines

Btw, do you need any additional configuration for selecting alternative muxing or is that automagical these days?

No additional configuration is needed.

Quoted 27 lines

Quoted 6 lines

Quoted 6 lines

Quoted 5 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +5 -0

+    msm_mux_blsp3_spi3,
+    msm_mux_burn0,
+    msm_mux_pcm_zsi0,
+    msm_mux_blsp5_uart,
+    msm_mux_mac12,

Quoted 8 lines

Quoted 1 line

What does "12" mean here?

The SoC has three MAC cores. Each core has two pins for the smart antenna
feature. macXY indicates the function select for MAC no. X and smart antenna
no. Y.

Ok

Quoted 10 lines

Quoted 9 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 229

Quoted 6 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +6 -0

+    msm_mux_blsp3_spi0,
+    msm_mux_burn1,
+    msm_mux_mac01,
+    msm_mux_qdss_cti_trig_out_b0,
+    msm_mux_qdss_cti_trig_in_b0,
+    msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions, alternative muxings...?

Quoted 6 lines

Quoted 3 lines

This is for the NAND and LCD display. The pins listed are the 9 data pins.

Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's possible to reference a partial group in the DTS, if that's necessary)

There are two sets of 9 pins, either of which can go to NAND or LCD. Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b. Is that ok?

Quoted 30 lines

Quoted 30 lines

Quoted 29 lines

Quoted 17 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +17 -0

+    msm_mux_blsp4_uart0,
+    msm_mux_blsp4_i2c0,
+    msm_mux_blsp4_spi0,
+    msm_mux_mac21,
+    msm_mux_qdss_cti_trig_out_b1,
+    msm_mux_qpic_pad5,
+    msm_mux_qdss_cti_trig_in_b1,
+    msm_mux_qpic_pad6,
+    msm_mux_qpic_pad7,
+    msm_mux_cxc0,
+    msm_mux_mac13,
+    msm_mux_qdss_cti_trig_in_a1,
+    msm_mux_qdss_cti_trig_out_a1,
+    msm_mux_wci22,
+    msm_mux_qdss_cti_trig_in_a0,
+    msm_mux_qpic_pad1,
+    msm_mux_qdss_cti_trig_out_a0,

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 256

Quoted 10 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +10 -0

+    msm_mux_qpic_pad2,
+    msm_mux_qpic_pad3,
+    msm_mux_qdss_traceclk_b,
+    msm_mux_qpic_pad0,
+    msm_mux_qdss_tracectl_b,
+    msm_mux_qpic_pad8,
+    msm_mux_pcm_zsi1,
+    msm_mux_qdss_tracedata_b,
+    msm_mux_led0,
+    msm_mux_pwm04,

What does "04" mean here?

Quoted 5 lines

Quoted 3 lines

There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
Y.

So Y is alternative mux? Can we use letters for this as well?

Ok

Quoted 9 lines

Quoted 9 lines

Quoted 8 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 262

Quoted 6 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +6 -0

+    msm_mux_led1,
+    msm_mux_pwm14,
+    msm_mux_led2,
+    msm_mux_pwm24,
+    msm_mux_pwm00,
+    msm_mux_blsp4_uart1,

Are uart0 vs uart1 alternative muxes?

Quoted 8 lines

Quoted 2 lines

These are two different uarts available at two independent pins.

Ok, then I'm happy with the naming of this :)

Thanks,
Bjorn

Thanks
Varada

Quoted 111 lines · Varadarajan Narayanan

Quoted 27 lines · Bjorn Andersson

Quoted 3 lines · Varadarajan Narayanan

Quoted 2 lines · Bjorn Andersson

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

[..]

Quoted 12 lines

Quoted 3 lines

Quoted 1 line

+enum ipq8074_functions {

Please keep these sorted alphabetically.

Ok

Quoted 6 lines

Quoted 5 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +5 -0

+    msm_mux_gpio,
+    msm_mux_qpic_pad,
+    msm_mux_blsp5_i2c,
+    msm_mux_blsp5_spi,
+    msm_mux_wci20,

Quoted 8 lines

Quoted 1 line

What does "20" mean here?

This is for Wireless Coex Interface. The same functionality can be muxed on
to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
are for the muxing to different GPIOs (alternate muxes).

Quoted 3 lines

In other Qualcomm platforms the alternative muxes are denoted by letters (a,b,c...). Would you mind picking up this naming scheme, or do you see any problems with that? (E.g. wci2a in this case)

Ok

Quoted 2 lines

Btw, do you need any additional configuration for selecting alternative muxing or is that automagical these days?

No additional configuration is needed.

Quoted 27 lines

Quoted 6 lines

Quoted 6 lines

Quoted 5 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +5 -0

+    msm_mux_blsp3_spi3,
+    msm_mux_burn0,
+    msm_mux_pcm_zsi0,
+    msm_mux_blsp5_uart,
+    msm_mux_mac12,

Quoted 8 lines

Quoted 1 line

What does "12" mean here?

The SoC has three MAC cores. Each core has two pins for the smart antenna
feature. macXY indicates the function select for MAC no. X and smart antenna
no. Y.

Ok

Quoted 10 lines

Quoted 9 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 229

Quoted 6 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +6 -0

+    msm_mux_blsp3_spi0,
+    msm_mux_burn1,
+    msm_mux_mac01,
+    msm_mux_qdss_cti_trig_out_b0,
+    msm_mux_qdss_cti_trig_in_b0,
+    msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions, alternative muxings...?

Quoted 6 lines

Quoted 3 lines

This is for the NAND and LCD display. The pins listed are the 9 data pins.

Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's possible to reference a partial group in the DTS, if that's necessary)

There are two sets of 9 pins, either of which can go to NAND or LCD. Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b. Is that ok?

Quoted 34 lines

Quoted 33 lines

Quoted 28 lines

Quoted 17 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +17 -0

+    msm_mux_blsp4_uart0,
+    msm_mux_blsp4_i2c0,
+    msm_mux_blsp4_spi0,
+    msm_mux_mac21,
+    msm_mux_qdss_cti_trig_out_b1,
+    msm_mux_qpic_pad5,
+    msm_mux_qdss_cti_trig_in_b1,
+    msm_mux_qpic_pad6,
+    msm_mux_qpic_pad7,
+    msm_mux_cxc0,
+    msm_mux_mac13,
+    msm_mux_qdss_cti_trig_in_a1,
+    msm_mux_qdss_cti_trig_out_a1,
+    msm_mux_wci22,
+    msm_mux_qdss_cti_trig_in_a0,
+    msm_mux_qpic_pad1,
+    msm_mux_qdss_cti_trig_out_a0,

drivers/pinctrl/qcom/pinctrl-ipq8074.c line 256

Quoted 10 lines

drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +10 -0

+    msm_mux_qpic_pad2,
+    msm_mux_qpic_pad3,
+    msm_mux_qdss_traceclk_b,
+    msm_mux_qpic_pad0,
+    msm_mux_qdss_tracectl_b,
+    msm_mux_qpic_pad8,
+    msm_mux_pcm_zsi1,
+    msm_mux_qdss_tracedata_b,
+    msm_mux_led0,
+    msm_mux_pwm04,

Quoted 1 line

What does "04" mean here?

There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
Y.

Quoted 3 lines

Quoted 1 line

So Y is alternative mux? Can we use letters for this as well?

Ok

Sorry, actually they are not alternative muxes. There are 4 different PWM instances. Each PWM instance can handle 'n' different GPIOs (for example, that can be connected to LED etc.).

Quoted 114 lines · Varadarajan Narayanan

Quoted 111 lines · Varadarajan Narayanan

Quoted 27 lines · Bjorn Andersson

Quoted 3 lines · Varadarajan Narayanan

Quoted 2 lines · Bjorn Andersson

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

[..]

Quoted 12 lines

Quoted 3 lines

Quoted 1 line

+enum ipq8074_functions {

Please keep these sorted alphabetically.

Ok

Quoted 6 lines

Quoted 5 lines

(quoted diff) +5 -0

+    msm_mux_gpio,
+    msm_mux_qpic_pad,
+    msm_mux_blsp5_i2c,
+    msm_mux_blsp5_spi,
+    msm_mux_wci20,

Quoted 8 lines

Quoted 1 line

What does "20" mean here?

This is for Wireless Coex Interface. The same functionality can be muxed on
to different GPIOs. WCI2, is the 2nd edition of the WCI standard and 0, 1
are for the muxing to different GPIOs (alternate muxes).

Quoted 3 lines

In other Qualcomm platforms the alternative muxes are denoted by letters (a,b,c...). Would you mind picking up this naming scheme, or do you see any problems with that? (E.g. wci2a in this case)

Ok

Quoted 2 lines

Btw, do you need any additional configuration for selecting alternative muxing or is that automagical these days?

No additional configuration is needed.

Quoted 27 lines

Quoted 6 lines

Quoted 6 lines

Quoted 5 lines

(quoted diff) +5 -0

+    msm_mux_blsp3_spi3,
+    msm_mux_burn0,
+    msm_mux_pcm_zsi0,
+    msm_mux_blsp5_uart,
+    msm_mux_mac12,

Quoted 8 lines

Quoted 1 line

What does "12" mean here?

The SoC has three MAC cores. Each core has two pins for the smart antenna
feature. macXY indicates the function select for MAC no. X and smart antenna
no. Y.

Ok

Quoted 10 lines

Quoted 9 lines

Review

Quoted 6 lines

(quoted diff) +6 -0

+    msm_mux_blsp3_spi0,
+    msm_mux_burn1,
+    msm_mux_mac01,
+    msm_mux_qdss_cti_trig_out_b0,
+    msm_mux_qdss_cti_trig_in_b0,
+    msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions, alternative muxings...?

Quoted 6 lines

Quoted 3 lines

This is for the NAND and LCD display. The pins listed are the 9 data pins.

Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's possible to reference a partial group in the DTS, if that's necessary)

There are two sets of 9 pins, either of which can go to NAND or LCD. Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b. Is that ok?

Quoted 34 lines

Quoted 33 lines

Quoted 28 lines

Quoted 17 lines

(quoted diff) +17 -0

+    msm_mux_blsp4_uart0,
+    msm_mux_blsp4_i2c0,
+    msm_mux_blsp4_spi0,
+    msm_mux_mac21,
+    msm_mux_qdss_cti_trig_out_b1,
+    msm_mux_qpic_pad5,
+    msm_mux_qdss_cti_trig_in_b1,
+    msm_mux_qpic_pad6,
+    msm_mux_qpic_pad7,
+    msm_mux_cxc0,
+    msm_mux_mac13,
+    msm_mux_qdss_cti_trig_in_a1,
+    msm_mux_qdss_cti_trig_out_a1,
+    msm_mux_wci22,
+    msm_mux_qdss_cti_trig_in_a0,
+    msm_mux_qpic_pad1,
+    msm_mux_qdss_cti_trig_out_a0,

Review

Quoted 10 lines

(quoted diff) +10 -0

+    msm_mux_qpic_pad2,
+    msm_mux_qpic_pad3,
+    msm_mux_qdss_traceclk_b,
+    msm_mux_qpic_pad0,
+    msm_mux_qdss_tracectl_b,
+    msm_mux_qpic_pad8,
+    msm_mux_pcm_zsi1,
+    msm_mux_qdss_tracedata_b,
+    msm_mux_led0,
+    msm_mux_pwm04,

Quoted 1 line

What does "04" mean here?

There are 4 Pulse Width Modulation channels, pwmXY is pwm channel X and pin
Y.

Quoted 8 lines

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So Y is alternative mux? Can we use letters for this as well?

Ok

Sorry, actually they are not alternative muxes. There are 4 different PWM instances. Each PWM instance can handle 'n' different GPIOs (for example, that can be connected to LED etc.).

So we have 4 PWMs and the output from a single PWM can muxed to drive the output of 4 pins?

Then skip the last digit and just go pwm0, ... pwm3 and include all four pins that can be part of each instance. As the pingroup configuration is per pin in the TLMM it's possible to configure subsets of the pins in a group.

Regards,
Bjorn

Quoted 4 lines · Bjorn Andersson

Quoted 2 lines · Varadarajan Narayanan

Quoted 1 line · Bjorn Andersson

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

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drivers/pinctrl/qcom/pinctrl-ipq8074.c line 229

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drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +1 -0

+	msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions, alternative muxings...?

This is for the NAND and LCD display. The pins listed are the 9 data pins.

Quoted 2 lines

Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's possible to reference a partial group in the DTS, if that's necessary)

There are two sets of 9 pins, either of which can go to NAND or LCD. Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b. Is that ok?

Quoted 5 lines · Varadarajan Narayanan

Quoted 4 lines · Bjorn Andersson

Quoted 2 lines · Varadarajan Narayanan

Quoted 1 line · Bjorn Andersson

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

[..]

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drivers/pinctrl/qcom/pinctrl-ipq8074.c line 229

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drivers/pinctrl/qcom/pinctrl-ipq8074.c new file +1 -0

+	msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions, alternative muxings...?

This is for the NAND and LCD display. The pins listed are the 9 data pins.

Quoted 7 lines

Quoted 2 lines

Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's possible to reference a partial group in the DTS, if that's necessary)

There are two sets of 9 pins, either of which can go to NAND or LCD. Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b. Is that ok?

So you have NAND and LCD hardware muxed to either "a" or "b" and then you mux either "a" or "b" out onto actual pins?

How is this first mux configured?

I think the a/b scheme sounds reasonable, if above is how it works.

Regards,
Bjorn

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Quoted 29 lines · Bjorn Andersson

Quoted 5 lines · Varadarajan Narayanan

Quoted 4 lines · Bjorn Andersson

Quoted 2 lines · Varadarajan Narayanan

Quoted 1 line · Bjorn Andersson

On Thu 04 May 04:53 PDT 2017, Varadarajan Narayanan wrote:

[..]

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Review

Quoted 1 line

(quoted diff) +1 -0

+	msm_mux_qpic_pad4,

What are qpic_pad and qpic_pad0 through qpic_pad8? Different functions, alternative muxings...?

This is for the NAND and LCD display. The pins listed are the 9 data pins.

Quoted 7 lines

Quoted 2 lines

Then you can describe them all as "qpic_pad" (or simply "qpic"?). (It's possible to reference a partial group in the DTS, if that's necessary)

There are two sets of 9 pins, either of which can go to NAND or LCD. Will rename qpic_pad as qpic_a and qpic_pad[0-8] as qpic_b. Is that ok?

So you have NAND and LCD hardware muxed to either "a" or "b" and then you mux either "a" or "b" out onto actual pins?

How is this first mux configured?

Quoted 1 line

I think the a/b scheme sounds reasonable, if above is how it works.

Sorry, I was wrong. I had misread the documentation.

There are 18 pins. 15 pins are common between LCD and NAND. The QPIC controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3 groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?

Quoted 5 lines · Varadarajan Narayanan

There are 18 pins. 15 pins are common between LCD and NAND. The QPIC controller arbitrates between LCD and NAND. Of the remaining 4, 2 are for NAND and 2 are for LCD exclusively. We plan to group the qpic pins into 3 groups namely, qpic_common, qpic_nand and qpic_lcd. Is that ok?

If you consider that you are defining the available functions for this pinmuxer and then define the sets of pins exposing these available functions it does make sense to just name it "qpic".

I think that naming them _common, _lcd and _nand is just adding confusion when it comes to writing the dts files.

@Linus, do you have a different preference here?

Signed-off-by Varadarajan Narayanan <[email protected]>

---
 Documentation/devicetree/bindings/arm/qcom.txt | 2 ++
 1 file changed, 2 insertions(+)

From: Abhishek Sahu <[email protected]>

This patch adds support for the global clock controller found on the IPQ8074 based devices. This includes UART, I2C, SPI etc.

Signed-off-by Abhishek Sahu <[email protected]>

Signed-off-by Varadarajan Narayanan <[email protected]>

---
 .../devicetree/bindings/clock/qcom,gcc.txt         |    1 +
 drivers/clk/qcom/Kconfig                           |    9 +
 drivers/clk/qcom/Makefile                          |    1 +
 drivers/clk/qcom/gcc-ipq8074.c                     | 1032 ++++++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-ipq8074.h       |  152 +++

 5 files changed, 1195 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-ipq8074.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-ipq8074.h