cryptodev: add compile support for AMD CCP crypto PMD
Subsystems (2)
PATCH v4 9/20 crypto/ccp: support ccp hwrng feature
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_dev.c | 20 ++++++++++++++++++++ drivers/crypto/ccp/ccp_dev.h | 11 +++++++++++ 2 files changed, 31 insertions(+)
drivers/crypto/ccp/ccp_dev.c +20 -0
@@ -88,6 +88,26 @@ ccp_allot_queue(struct rte_cryptodev *cdev, int slot_req)return NULL ; } +int +ccp_read_hwrng (uint32_t *value) +{ +struct ccp_device *dev; + + TAILQ_FOREACH(dev, &ccp_list, next) { +void *vaddr = (void *)(dev->pci.mem_resource[2 ].addr); + +while (dev->hwrng_retries++ <CCP_MAX_TRNG_RETRIES ) { + *value =CCP_READ_REG (vaddr,TRNG_OUT_REG ); +if (*value) { + dev->hwrng_retries =0 ; +return 0 ; + } + } + dev->hwrng_retries =0 ; + } +return -1 ; +} +static const struct rte_memzone * ccp_queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
drivers/crypto/ccp/ccp_dev.h +11 -0
@@ -47,6 +47,7 @@/**< CCP sspecific */ #define MAX_HW_QUEUES 5 +#define CCP_MAX_TRNG_RETRIES 10/**< CCP Register Mappings */ #define Q_MASK_REG 0x000
@@ -223,6 +224,8 @@ struct ccp_device {/**< protection for shared lsb region allocation */ int qidx;/**< current queue index */ +int hwrng_retries; +/**< retry counter for CCP TRNG */ } __rte_cache_aligned;/**< CCP H/W engine related */
@@ -454,4 +457,12 @@ int ccp_probe_devices(const struct rte_pci_id *ccp_id);*/ struct ccp_queue *ccp_allot_queue (struct rte_cryptodev *dev,int slot_req); +/** +* read hwrng value +* +* @param trng_value data pointer to write RNG value +* @return 0 on success otherwise -1 +*/ +int ccp_read_hwrng (uint32_t *trng_value); +#endif /* _CCP_DEV_H_ */
Signature · 1 line
2.7.4
PATCH v4 10/20 crypto/ccp: support aes cipher algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 197 ++++++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_crypto.h | 13 +++ drivers/crypto/ccp/ccp_dev.h | 53 +++++++++++ drivers/crypto/ccp/ccp_pmd_ops.c | 60 ++++++++++++ 4 files changed, 321 insertions(+), 2 deletions(-)
drivers/crypto/ccp/ccp_crypto.c +195 -2
@@ -80,6 +80,7 @@ ccp_configure_session_cipher(struct ccp_session *sess, const struct rte_crypto_sym_xform *xform) {const struct rte_crypto_cipher_xform *cipher_xform =NULL ; +size_t i; cipher_xform = &xform->cipher;
@@ -99,6 +100,21 @@ ccp_configure_session_cipher(struct ccp_session *sess, sess->iv.length = cipher_xform->iv.length;switch (cipher_xform->algo) { +case RTE_CRYPTO_CIPHER_AES_CTR : + sess->cipher.algo =CCP_CIPHER_ALGO_AES_CTR ; + sess->cipher.um.aes_mode =CCP_AES_MODE_CTR ; + sess->cipher.engine =CCP_ENGINE_AES ; +break ; +case RTE_CRYPTO_CIPHER_AES_ECB : + sess->cipher.algo =CCP_CIPHER_ALGO_AES_CBC ; + sess->cipher.um.aes_mode =CCP_AES_MODE_ECB ; + sess->cipher.engine =CCP_ENGINE_AES ; +break ; +case RTE_CRYPTO_CIPHER_AES_CBC : + sess->cipher.algo =CCP_CIPHER_ALGO_AES_CBC ; + sess->cipher.um.aes_mode =CCP_AES_MODE_CBC ; + sess->cipher.engine =CCP_ENGINE_AES ; +break ;default :CCP_LOG_ERR ("Unsupported cipher algo" );return -1 ;
@@ -106,10 +122,27 @@ ccp_configure_session_cipher(struct ccp_session *sess,switch (sess->cipher.engine) { +case CCP_ENGINE_AES : +if (sess->cipher.key_length ==16 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_128 ; +else if (sess->cipher.key_length ==24 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_192 ; +else if (sess->cipher.key_length ==32 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_256 ; +else { +CCP_LOG_ERR ("Invalid cipher key length" ); +return -1 ; + } +for (i =0 ; i < sess->cipher.key_length ; i++) + sess->cipher.key_ccp[sess->cipher.key_length - i -1 ] = + sess->cipher.key[i]; +break ;default :CCP_LOG_ERR ("Invalid CCP Engine" );return -ENOTSUP ; } + sess->cipher.nonce_phys =rte_mem_virt2phy (sess->cipher.nonce); + sess->cipher.key_phys =rte_mem_virt2phy (sess->cipher.key_ccp);return 0 ; }
@@ -235,6 +268,18 @@ ccp_cipher_slot(struct ccp_session *session)int count =0 ;switch (session->cipher.algo) { +case CCP_CIPHER_ALGO_AES_CBC : + count =2 ; +/**< op + passthrough for iv */ +break ; +case CCP_CIPHER_ALGO_AES_ECB : + count =1 ; +/**<only op*/ +break ; +case CCP_CIPHER_ALGO_AES_CTR : + count =2 ; +/**< op + passthrough for iv */ +break ;default :CCP_LOG_ERR ("Unsupported cipher algo %d" , session->cipher.algo);
@@ -297,10 +342,146 @@ ccp_compute_slot_count(struct ccp_session *session)return count; } +static void +ccp_perform_passthru (struct ccp_passthru *pst, +struct ccp_queue *cmd_q) +{ +struct ccp_desc *desc; +union ccp_function function; + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_PASSTHRU ; + +CCP_CMD_SOC (desc) =0 ; +CCP_CMD_IOC (desc) =0 ; +CCP_CMD_INIT (desc) =0 ; +CCP_CMD_EOM (desc) =0 ; +CCP_CMD_PROT (desc) =0 ; + + function.raw =0 ; +CCP_PT_BYTESWAP (&function) = pst->byte_swap; +CCP_PT_BITWISE (&function) = pst->bit_mod; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = pst->len; + +if (pst->dir) { +CCP_CMD_SRC_LO (desc) = (uint32_t )(pst->src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (pst->src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = (uint32_t )(pst->dest_addr); +CCP_CMD_DST_HI (desc) =0 ; +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SB ; + +if (pst->bit_mod !=CCP_PASSTHRU_BITWISE_NOOP ) +CCP_CMD_LSB_ID (desc) = cmd_q->sb_key; + }else { + +CCP_CMD_SRC_LO (desc) = (uint32_t )(pst->src_addr); +CCP_CMD_SRC_HI (desc) =0 ; +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SB ; + +CCP_CMD_DST_LO (desc) = (uint32_t )(pst->dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (pst->dest_addr); +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + } + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; +} + +static int +ccp_perform_aes (struct rte_crypto_op *op, +struct ccp_queue *cmd_q, +struct ccp_batch_info *b_info) +{ +struct ccp_session *session; +union ccp_function function; +uint8_t *lsb_buf; +struct ccp_passthru pst = {0 }; +struct ccp_desc *desc; +phys_addr_t src_addr, dest_addr, key_addr; +uint8_t *iv; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + function.raw =0 ; + + iv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset); +if (session->cipher.um.aes_mode !=CCP_AES_MODE_ECB ) { +if (session->cipher.um.aes_mode ==CCP_AES_MODE_CTR ) { +rte_memcpy (session->cipher.nonce +AES_BLOCK_SIZE , + iv, session->iv.length); + pst.src_addr = (phys_addr_t )session->cipher.nonce_phys; +CCP_AES_SIZE (&function) =0x1F ; + }else { + lsb_buf = + &(b_info->lsb_buf[b_info->lsb_buf_idx*CCP_SB_BYTES ]); +rte_memcpy (lsb_buf + + (CCP_SB_BYTES - session->iv.length), + iv, session->iv.length); + pst.src_addr = b_info->lsb_buf_phys + + (b_info->lsb_buf_idx *CCP_SB_BYTES ); + b_info->lsb_buf_idx++; + } + + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + } + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->cipher.data.offset); +if (likely (op->sym->m_dst !=NULL )) + dest_addr =rte_pktmbuf_mtophys_offset (op->sym->m_dst, + op->sym->cipher.data.offset); +else + dest_addr = src_addr; + key_addr = session->cipher.key_phys; + +/* prepare desc for aes command */ +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; + +CCP_AES_ENCRYPT (&function) = session->cipher.dir; +CCP_AES_MODE (&function) = session->cipher.um.aes_mode; +CCP_AES_TYPE (&function) = session->cipher.ut.aes_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->cipher.data.length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = ((uint32_t )dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (dest_addr); +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +if (session->cipher.um.aes_mode !=CCP_AES_MODE_ECB ) +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} +static inline int ccp_crypto_cipher (struct rte_crypto_op *op, - struct ccp_queue *cmd_q __rte_unused, - struct ccp_batch_info *b_info __rte_unused) +struct ccp_queue *cmd_q, +struct ccp_batch_info *b_info) {int result =0 ;struct ccp_session *session;
@@ -310,6 +491,18 @@ ccp_crypto_cipher(struct rte_crypto_op *op, ccp_cryptodev_driver_id);switch (session->cipher.algo) { +case CCP_CIPHER_ALGO_AES_CBC : + result =ccp_perform_aes (op, cmd_q, b_info); + b_info->desccnt +=2 ; +break ; +case CCP_CIPHER_ALGO_AES_CTR : + result =ccp_perform_aes (op, cmd_q, b_info); + b_info->desccnt +=2 ; +break ; +case CCP_CIPHER_ALGO_AES_ECB : + result =ccp_perform_aes (op, cmd_q, b_info); + b_info->desccnt +=1 ; +break ;default :CCP_LOG_ERR ("Unsupported cipher algo %d" , session->cipher.algo);
drivers/crypto/ccp/ccp_crypto.h +13 -0
@@ -46,7 +46,20 @@#include "ccp_dev.h" +#define AES_BLOCK_SIZE 16 +#define CMAC_PAD_VALUE 0x80 +#define CTR_NONCE_SIZE 4 +#define CTR_IV_SIZE 8#define CCP_SHA3_CTX_SIZE 200 + +/**Macro helpers for CCP command creation*/ +#define CCP_AES_SIZE (p) ((p)->aes.size) +#define CCP_AES_ENCRYPT (p) ((p)->aes.encrypt) +#define CCP_AES_MODE (p) ((p)->aes.mode) +#define CCP_AES_TYPE (p) ((p)->aes.type) +#define CCP_PT_BYTESWAP (p) ((p)->pt.byteswap) +#define CCP_PT_BITWISE (p) ((p)->pt.bitwise) +/** * CCP supported AES modes */
drivers/crypto/ccp/ccp_dev.h +53 -0
75 lines not on this page · raw message
drivers/crypto/ccp/ccp_pmd_ops.c +60 -0
66 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v4 11/20 crypto/ccp: support 3des cipher algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 132 ++++++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_crypto.h | 3 + drivers/crypto/ccp/ccp_pmd_ops.c | 20 ++++++ 3 files changed, 154 insertions(+), 1 deletion(-)
drivers/crypto/ccp/ccp_crypto.c +131 -1
@@ -80,7 +80,7 @@ ccp_configure_session_cipher(struct ccp_session *sess, const struct rte_crypto_sym_xform *xform) {const struct rte_crypto_cipher_xform *cipher_xform =NULL ; -size_t i; +size_t i, j, x; cipher_xform = &xform->cipher;
@@ -115,6 +115,11 @@ ccp_configure_session_cipher(struct ccp_session *sess, sess->cipher.um.aes_mode =CCP_AES_MODE_CBC ; sess->cipher.engine =CCP_ENGINE_AES ;break ; +case RTE_CRYPTO_CIPHER_3DES_CBC : + sess->cipher.algo =CCP_CIPHER_ALGO_3DES_CBC ; + sess->cipher.um.des_mode =CCP_DES_MODE_CBC ; + sess->cipher.engine =CCP_ENGINE_3DES ; +break ;default :CCP_LOG_ERR ("Unsupported cipher algo" );return -1 ;
@@ -137,6 +142,20 @@ ccp_configure_session_cipher(struct ccp_session *sess, sess->cipher.key_ccp[sess->cipher.key_length - i -1 ] = sess->cipher.key[i];break ; +case CCP_ENGINE_3DES : +if (sess->cipher.key_length ==16 ) + sess->cipher.ut.des_type =CCP_DES_TYPE_128 ; +else if (sess->cipher.key_length ==24 ) + sess->cipher.ut.des_type =CCP_DES_TYPE_192 ; +else { +CCP_LOG_ERR ("Invalid cipher key length" ); +return -1 ; + } +for (j =0 , x =0 ; j < sess->cipher.key_length/8 ; j++, x +=8 ) +for (i =0 ; i <8 ; i++) + sess->cipher.key_ccp[(8 + x) - i -1 ] = + sess->cipher.key[i + x]; +break ;default :CCP_LOG_ERR ("Invalid CCP Engine" );return -ENOTSUP ;
@@ -280,6 +299,10 @@ ccp_cipher_slot(struct ccp_session *session) count =2 ;/**< op + passthrough for iv */ break ; +case CCP_CIPHER_ALGO_3DES_CBC : + count =2 ; +/**< op + passthrough for iv */ +break ;default :CCP_LOG_ERR ("Unsupported cipher algo %d" , session->cipher.algo);
@@ -478,6 +501,109 @@ ccp_perform_aes(struct rte_crypto_op *op,return 0 ; } +static int +ccp_perform_3des (struct rte_crypto_op *op, +struct ccp_queue *cmd_q, +struct ccp_batch_info *b_info) +{ +struct ccp_session *session; +union ccp_function function; +unsigned char *lsb_buf; +struct ccp_passthru pst; +struct ccp_desc *desc; +uint32_t tail; +uint8_t *iv; +phys_addr_t src_addr, dest_addr, key_addr; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + + iv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset); +switch (session->cipher.um.des_mode) { +case CCP_DES_MODE_CBC : + lsb_buf = &(b_info->lsb_buf[b_info->lsb_buf_idx*CCP_SB_BYTES ]); + b_info->lsb_buf_idx++; + +rte_memcpy (lsb_buf + (CCP_SB_BYTES - session->iv.length), + iv, session->iv.length); + + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *) lsb_buf); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); +break ; +case CCP_DES_MODE_CFB : +case CCP_DES_MODE_ECB : +CCP_LOG_ERR ("Unsupported DES cipher mode" ); +return -ENOTSUP ; + } + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->cipher.data.offset); +if (unlikely (op->sym->m_dst !=NULL )) + dest_addr = +rte_pktmbuf_mtophys_offset (op->sym->m_dst, + op->sym->cipher.data.offset); +else + dest_addr = src_addr; + + key_addr =rte_mem_virt2phy (session->cipher.key_ccp); + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; + +memset (desc,0 ,Q_DESC_SIZE ); + +/* prepare desc for des command */ +CCP_CMD_ENGINE (desc) =CCP_ENGINE_3DES ; + +CCP_CMD_SOC (desc) =0 ; +CCP_CMD_IOC (desc) =0 ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_PROT (desc) =0 ; + + function.raw =0 ; +CCP_DES_ENCRYPT (&function) = session->cipher.dir; +CCP_DES_MODE (&function) = session->cipher.um.des_mode; +CCP_DES_TYPE (&function) = session->cipher.ut.des_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->cipher.data.length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = ((uint32_t )dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (dest_addr); +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +if (session->cipher.um.des_mode) +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + +/* Write the new tail address back to the queue register */ + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +/* Turn the queue back on using our cached control register */ +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} + static inline int ccp_crypto_cipher(struct rte_crypto_op *op, struct ccp_queue *cmd_q,
@@ -503,6 +629,10 @@ ccp_crypto_cipher(struct rte_crypto_op *op, result =ccp_perform_aes (op, cmd_q, b_info); b_info->desccnt +=1 ;break ; +case CCP_CIPHER_ALGO_3DES_CBC : + result =ccp_perform_3des (op, cmd_q, b_info); + b_info->desccnt +=2 ; +break ;default :CCP_LOG_ERR ("Unsupported cipher algo %d" , session->cipher.algo);
drivers/crypto/ccp/ccp_crypto.h +3 -0
@@ -57,6 +57,9 @@#define CCP_AES_ENCRYPT (p) ((p)->aes.encrypt)#define CCP_AES_MODE (p) ((p)->aes.mode)#define CCP_AES_TYPE (p) ((p)->aes.type) +#define CCP_DES_ENCRYPT (p) ((p)->des.encrypt) +#define CCP_DES_MODE (p) ((p)->des.mode) +#define CCP_DES_TYPE (p) ((p)->des.type)#define CCP_PT_BYTESWAP (p) ((p)->pt.byteswap)#define CCP_PT_BITWISE (p) ((p)->pt.bitwise)
drivers/crypto/ccp/ccp_pmd_ops.c +20 -0
@@ -99,6 +99,26 @@ static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = { }, } }, } }, + {/* 3DES CBC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type =RTE_CRYPTO_SYM_XFORM_CIPHER , + {.cipher = { + .algo =RTE_CRYPTO_CIPHER_3DES_CBC , + .block_size = 8, + .key_size = { + .min =16 , + .max = 24, + .increment = 8 + }, + .iv_size = { + .min =8 , + .max = 8, + .increment = 0 + } + }, } + }, } + },RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST () };
Signature · 1 line
2.7.4
PATCH v4 12/20 crypto/ccp: support aes-cmac auth algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 277 ++++++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_pmd_ops.c | 20 +++ 2 files changed, 295 insertions(+), 2 deletions(-)
drivers/crypto/ccp/ccp_crypto.c +275 -2
@@ -36,6 +36,8 @@#include <sys/queue.h> #include <sys/types.h> #include <unistd.h> +#include <openssl/cmac.h> /*sub key apis*/ +#include <openssl/evp.h> /*sub key apis*/ #include <rte_hexdump.h> #include <rte_memzone.h>
@@ -74,6 +76,84 @@ ccp_get_cmd_id(const struct rte_crypto_sym_xform *xform)return res; } +/* prepare temporary keys K1 and K2 */ +static void prepare_key (unsigned char *k,unsigned char *l,int bl) +{ +int i; +/* Shift block to left, including carry */ +for (i =0 ; i < bl; i++) { + k[i] = l[i] <<1 ; +if (i < bl -1 && l[i +1 ] &0x80 ) + k[i] |=1 ; + } +/* If MSB set fixup with R */ +if (l[0 ] &0x80 ) + k[bl -1 ] ^= bl ==16 ?0x87 :0x1b ; +} + +/* subkeys K1 and K2 generation for CMAC */ +static int +generate_cmac_subkeys (struct ccp_session *sess) +{ +const EVP_CIPHER *algo; +EVP_CIPHER_CTX *ctx; +unsigned char *ccp_ctx; +size_t i; +int dstlen, totlen; +unsigned char zero_iv[AES_BLOCK_SIZE ] = {0 }; +unsigned char dst[2 *AES_BLOCK_SIZE ] = {0 }; +unsigned char k1[AES_BLOCK_SIZE ] = {0 }; +unsigned char k2[AES_BLOCK_SIZE ] = {0 }; + +if (sess->auth.ut.aes_type ==CCP_AES_TYPE_128 ) + algo =EVP_aes_128_cbc (); +else if (sess->auth.ut.aes_type ==CCP_AES_TYPE_192 ) + algo =EVP_aes_192_cbc (); +else if (sess->auth.ut.aes_type ==CCP_AES_TYPE_256 ) + algo =EVP_aes_256_cbc (); +else { +CCP_LOG_ERR ("Invalid CMAC type length" ); +return -1 ; + } + + ctx =EVP_CIPHER_CTX_new (); +if (!ctx) { +CCP_LOG_ERR ("ctx creation failed" ); +return -1 ; + } +if (EVP_EncryptInit (ctx, algo, (unsigned char *)sess->auth.key, + (unsigned char *)zero_iv) <=0 ) + goto key_generate_err; +if (EVP_CIPHER_CTX_set_padding (ctx,0 ) <=0 ) + goto key_generate_err; +if (EVP_EncryptUpdate (ctx, dst, &dstlen, zero_iv, +AES_BLOCK_SIZE ) <=0 ) + goto key_generate_err; +if (EVP_EncryptFinal_ex (ctx, dst + dstlen, &totlen) <=0 ) + goto key_generate_err; + +memset (sess->auth.pre_compute,0 ,CCP_SB_BYTES *2 ); + + ccp_ctx = (unsigned char *)(sess->auth.pre_compute +CCP_SB_BYTES -1 ); +prepare_key (k1, dst,AES_BLOCK_SIZE ); +for (i =0 ; i <AES_BLOCK_SIZE ; i++, ccp_ctx--) + *ccp_ctx = k1[i]; + + ccp_ctx = (unsigned char *)(sess->auth.pre_compute + + (2 *CCP_SB_BYTES ) -1 ); +prepare_key (k2, k1,AES_BLOCK_SIZE ); +for (i =0 ; i <AES_BLOCK_SIZE ; i++, ccp_ctx--) + *ccp_ctx = k2[i]; + +EVP_CIPHER_CTX_free (ctx); + +return 0 ; + +key_generate_err: +CCP_LOG_ERR ("CMAC Init failed" ); +return -1 ; +} +/* configure session */ static int ccp_configure_session_cipher(struct ccp_session *sess,
@@ -170,6 +250,7 @@ ccp_configure_session_auth(struct ccp_session *sess, const struct rte_crypto_sym_xform *xform) {const struct rte_crypto_auth_xform *auth_xform =NULL ; +size_t i; auth_xform = &xform->auth;
@@ -179,6 +260,33 @@ ccp_configure_session_auth(struct ccp_session *sess,else sess->auth.op =CCP_AUTH_OP_VERIFY ;switch (auth_xform->algo) { +case RTE_CRYPTO_AUTH_AES_CMAC : + sess->auth.algo =CCP_AUTH_ALGO_AES_CMAC ; + sess->auth.engine =CCP_ENGINE_AES ; + sess->auth.um.aes_mode =CCP_AES_MODE_CMAC ; + sess->auth.key_length = auth_xform->key.length; +/**<padding and hash result*/ + sess->auth.ctx_len =CCP_SB_BYTES <<1 ; + sess->auth.offset =AES_BLOCK_SIZE ; + sess->auth.block_size =AES_BLOCK_SIZE ; +if (sess->auth.key_length ==16 ) + sess->auth.ut.aes_type =CCP_AES_TYPE_128 ; +else if (sess->auth.key_length ==24 ) + sess->auth.ut.aes_type =CCP_AES_TYPE_192 ; +else if (sess->auth.key_length ==32 ) + sess->auth.ut.aes_type =CCP_AES_TYPE_256 ; +else { +CCP_LOG_ERR ("Invalid CMAC key length" ); +return -1 ; + } +rte_memcpy (sess->auth.key, auth_xform->key.data, + sess->auth.key_length); +for (i =0 ; i < sess->auth.key_length; i++) + sess->auth.key_ccp[sess->auth.key_length - i -1 ] = + sess->auth.key[i]; +if (generate_cmac_subkeys (sess)) +return -1 ; +break ;default :CCP_LOG_ERR ("Unsupported hash algo" );return -ENOTSUP ;
@@ -316,6 +424,15 @@ ccp_auth_slot(struct ccp_session *session)int count =0 ;switch (session->auth.algo) { +case CCP_AUTH_ALGO_AES_CMAC : + count =4 ; +/** +* op +* extra descriptor in padding case +* (k1/k2(255:128) with iv(127:0)) +* Retrieve result +*/ +break ;default :CCP_LOG_ERR ("Unsupported auth algo %d" , session->auth.algo);
@@ -415,6 +532,158 @@ ccp_perform_passthru(struct ccp_passthru *pst, }static int +ccp_perform_aes_cmac (struct rte_crypto_op *op, +struct ccp_queue *cmd_q) +{ +struct ccp_session *session; +union ccp_function function; +struct ccp_passthru pst; +struct ccp_desc *desc; +uint32_t tail; +uint8_t *src_tb, *append_ptr, *ctx_addr; +phys_addr_t src_addr, dest_addr, key_addr; +int length, non_align_len; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + key_addr =rte_mem_virt2phy (session->auth.key_ccp); + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->auth.data.offset); + append_ptr = (uint8_t *)rte_pktmbuf_append (op->sym->m_src, + session->auth.ctx_len); + dest_addr = (phys_addr_t )rte_mem_virt2phy ((void *)append_ptr); + + function.raw =0 ; +CCP_AES_ENCRYPT (&function) =CCP_CIPHER_DIR_ENCRYPT ; +CCP_AES_MODE (&function) = session->auth.um.aes_mode; +CCP_AES_TYPE (&function) = session->auth.ut.aes_type; + +if (op->sym->auth.data.length % session->auth.block_size ==0 ) { + + ctx_addr = session->auth.pre_compute; +memset (ctx_addr,0 ,AES_BLOCK_SIZE ); + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *)ctx_addr); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +/* prepare desc for aes-cmac command */ +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->auth.data.length; +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + + tail = + (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + }else { + ctx_addr = session->auth.pre_compute +CCP_SB_BYTES ; +memset (ctx_addr,0 ,AES_BLOCK_SIZE ); + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *)ctx_addr); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + + length = (op->sym->auth.data.length /AES_BLOCK_SIZE ); + length *=AES_BLOCK_SIZE ; + non_align_len = op->sym->auth.data.length - length; +/* prepare desc for aes-cmac command */ +/*Command 1*/ + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = length; +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +/*Command 2*/ + append_ptr = append_ptr +CCP_SB_BYTES ; +memset (append_ptr,0 ,AES_BLOCK_SIZE ); + src_tb =rte_pktmbuf_mtod_offset (op->sym->m_src, + uint8_t *, + op->sym->auth.data.offset + + length); +rte_memcpy (append_ptr, src_tb, non_align_len); + append_ptr[non_align_len] =CMAC_PAD_VALUE ; + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_FUNCTION (desc) = function.raw; +CCP_CMD_LEN (desc) =AES_BLOCK_SIZE ; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )(dest_addr +CCP_SB_BYTES )); +CCP_CMD_SRC_HI (desc) =high32_value (dest_addr +CCP_SB_BYTES ); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + tail = + (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + } +/* Retrieve result */ + pst.dest_addr = dest_addr; + pst.src_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} + +static int ccp_perform_aes (struct rte_crypto_op *op,struct ccp_queue *cmd_q,struct ccp_batch_info *b_info)
@@ -643,8 +912,8 @@ ccp_crypto_cipher(struct rte_crypto_op *op,static inline int ccp_crypto_auth (struct rte_crypto_op *op, - struct ccp_queue *cmd_q __rte_unused, - struct ccp_batch_info *b_info __rte_unused) +struct ccp_queue *cmd_q, +struct ccp_batch_info *b_info) {int result =0 ;
@@ -655,6 +924,10 @@ ccp_crypto_auth(struct rte_crypto_op *op, ccp_cryptodev_driver_id);switch (session->auth.algo) { +case CCP_AUTH_ALGO_AES_CMAC : + result =ccp_perform_aes_cmac (op, cmd_q); + b_info->desccnt +=4 ; +break ;default :CCP_LOG_ERR ("Unsupported auth algo %d" , session->auth.algo);
drivers/crypto/ccp/ccp_pmd_ops.c +20 -0
@@ -39,6 +39,26 @@#include "ccp_crypto.h" static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = { + {/*AES-CMAC */ + .op =RTE_CRYPTO_OP_TYPE_SYMMETRIC , + {.sym = { + .xform_type =RTE_CRYPTO_SYM_XFORM_AUTH , + {.auth = { + .algo =RTE_CRYPTO_AUTH_AES_CMAC , + .block_size =16 , + .key_size = { + .min =16 , + .max =32 , + .increment =8 + }, + .digest_size = { + .min =16 , + .max =16 , + .increment =0 + }, + }, } + }, } + }, {/* AES ECB */ .op =RTE_CRYPTO_OP_TYPE_SYMMETRIC , {.sym = {
Signature · 1 line
2.7.4
PATCH v4 13/20 crypto/ccp: support aes-gcm aead algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 235 ++++++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_pmd_ops.c | 30 +++++ 2 files changed, 261 insertions(+), 4 deletions(-)
drivers/crypto/ccp/ccp_crypto.c +231 -4
@@ -299,6 +299,7 @@ ccp_configure_session_aead(struct ccp_session *sess, const struct rte_crypto_sym_xform *xform) {const struct rte_crypto_aead_xform *aead_xform =NULL ; +size_t i; aead_xform = &xform->aead;
@@ -313,6 +314,7 @@ ccp_configure_session_aead(struct ccp_session *sess, sess->cipher.dir =CCP_CIPHER_DIR_DECRYPT ; sess->auth.op =CCP_AUTH_OP_VERIFY ; } + sess->aead_algo = aead_xform->algo; sess->auth.aad_length = aead_xform->aad_length; sess->auth.digest_length = aead_xform->digest_length;
@@ -321,10 +323,37 @@ ccp_configure_session_aead(struct ccp_session *sess, sess->iv.length = aead_xform->iv.length;switch (aead_xform->algo) { +case RTE_CRYPTO_AEAD_AES_GCM : + sess->cipher.algo =CCP_CIPHER_ALGO_AES_GCM ; + sess->cipher.um.aes_mode =CCP_AES_MODE_GCTR ; + sess->cipher.engine =CCP_ENGINE_AES ; +if (sess->cipher.key_length ==16 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_128 ; +else if (sess->cipher.key_length ==24 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_192 ; +else if (sess->cipher.key_length ==32 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_256 ; +else { +CCP_LOG_ERR ("Invalid aead key length" ); +return -1 ; + } +for (i =0 ; i < sess->cipher.key_length; i++) + sess->cipher.key_ccp[sess->cipher.key_length - i -1 ] = + sess->cipher.key[i]; + sess->auth.algo =CCP_AUTH_ALGO_AES_GCM ; + sess->auth.engine =CCP_ENGINE_AES ; + sess->auth.um.aes_mode =CCP_AES_MODE_GHASH ; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =0 ; + sess->auth.block_size =AES_BLOCK_SIZE ; + sess->cmd_id =CCP_CMD_COMBINED ; +break ;default :CCP_LOG_ERR ("Unsupported aead algo" );return -ENOTSUP ; } + sess->cipher.nonce_phys =rte_mem_virt2phy (sess->cipher.nonce); + sess->cipher.key_phys =rte_mem_virt2phy (sess->cipher.key_ccp);return 0 ; }
@@ -447,10 +476,27 @@ ccp_aead_slot(struct ccp_session *session)int count =0 ;switch (session->aead_algo) { +case RTE_CRYPTO_AEAD_AES_GCM : +break ;default :CCP_LOG_ERR ("Unsupported aead algo %d" , session->aead_algo); } +switch (session->auth.algo) { +case CCP_AUTH_ALGO_AES_GCM : + count =5 ; +/** +* 1. Passthru iv +* 2. Hash AAD +* 3. GCTR +* 4. Reload passthru +* 5. Hash Final tag +*/ +break ; +default : +CCP_LOG_ERR ("Unsupported combined auth ALGO %d" , + session->auth.algo); + }return count; }
@@ -873,6 +919,179 @@ ccp_perform_3des(struct rte_crypto_op *op,return 0 ; } +static int +ccp_perform_aes_gcm (struct rte_crypto_op *op,struct ccp_queue *cmd_q) +{ +struct ccp_session *session; +union ccp_function function; +uint8_t *iv; +struct ccp_passthru pst; +struct ccp_desc *desc; +uint32_t tail; +uint64_t *temp; +phys_addr_t src_addr, dest_addr, key_addr, aad_addr; +phys_addr_t digest_dest_addr; +int length, non_align_len; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + iv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset); + key_addr = session->cipher.key_phys; + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->aead.data.offset); +if (unlikely (op->sym->m_dst !=NULL )) + dest_addr =rte_pktmbuf_mtophys_offset (op->sym->m_dst, + op->sym->aead.data.offset); +else + dest_addr = src_addr; +rte_pktmbuf_append (op->sym->m_src, session->auth.ctx_len); + digest_dest_addr = op->sym->aead.digest.phys_addr; + temp = (uint64_t *)(op->sym->aead.digest.data +AES_BLOCK_SIZE ); + *temp++ =rte_bswap64 (session->auth.aad_length <<3 ); + *temp =rte_bswap64 (op->sym->aead.data.length <<3 ); + + non_align_len = op->sym->aead.data.length %AES_BLOCK_SIZE ; + length =CCP_ALIGN (op->sym->aead.data.length,AES_BLOCK_SIZE ); + + aad_addr = op->sym->aead.aad.phys_addr; + +/* CMD1 IV Passthru */ +rte_memcpy (session->cipher.nonce +AES_BLOCK_SIZE , iv, + session->iv.length); + pst.src_addr = session->cipher.nonce_phys; + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + +/* CMD2 GHASH-AAD */ + function.raw =0 ; +CCP_AES_ENCRYPT (&function) =CCP_AES_MODE_GHASH_AAD ; +CCP_AES_MODE (&function) =CCP_AES_MODE_GHASH ; +CCP_AES_TYPE (&function) = session->cipher.ut.aes_type; + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = session->auth.aad_length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )aad_addr); +CCP_CMD_SRC_HI (desc) =high32_value (aad_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* CMD3 : GCTR Plain text */ + function.raw =0 ; +CCP_AES_ENCRYPT (&function) = session->cipher.dir; +CCP_AES_MODE (&function) =CCP_AES_MODE_GCTR ; +CCP_AES_TYPE (&function) = session->cipher.ut.aes_type; +if (non_align_len ==0 ) +CCP_AES_SIZE (&function) = (AES_BLOCK_SIZE <<3 ) -1 ; +else +CCP_AES_SIZE (&function) = (non_align_len <<3 ) -1 ; + + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = ((uint32_t )dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (dest_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* CMD4 : PT to copy IV */ + pst.src_addr = session->cipher.nonce_phys; + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =AES_BLOCK_SIZE ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + +/* CMD5 : GHASH-Final */ + function.raw =0 ; +CCP_AES_ENCRYPT (&function) =CCP_AES_MODE_GHASH_FINAL ; +CCP_AES_MODE (&function) =CCP_AES_MODE_GHASH ; +CCP_AES_TYPE (&function) = session->cipher.ut.aes_type; + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_FUNCTION (desc) = function.raw; +/* Last block (AAD_len || PT_len)*/ +CCP_CMD_LEN (desc) =AES_BLOCK_SIZE ; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )digest_dest_addr +AES_BLOCK_SIZE ); +CCP_CMD_SRC_HI (desc) =high32_value (digest_dest_addr +AES_BLOCK_SIZE ); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = ((uint32_t )digest_dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (digest_dest_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} + static inline int ccp_crypto_cipher(struct rte_crypto_op *op, struct ccp_queue *cmd_q,
@@ -939,17 +1158,25 @@ ccp_crypto_auth(struct rte_crypto_op *op,static inline int ccp_crypto_aead (struct rte_crypto_op *op, - struct ccp_queue *cmd_q __rte_unused, - struct ccp_batch_info *b_info __rte_unused) +struct ccp_queue *cmd_q, +struct ccp_batch_info *b_info) {int result =0 ;struct ccp_session *session; session = (struct ccp_session *)get_session_private_data ( - op->sym->session, + op->sym->session, ccp_cryptodev_driver_id); -switch (session->aead_algo) { +switch (session->auth.algo) { +case CCP_AUTH_ALGO_AES_GCM : +if (session->cipher.algo !=CCP_CIPHER_ALGO_AES_GCM ) { +CCP_LOG_ERR ("Incorrect chain order" ); +return -1 ; + } + result =ccp_perform_aes_gcm (op, cmd_q); + b_info->desccnt +=5 ; +break ;default :CCP_LOG_ERR ("Unsupported aead algo %d" , session->aead_algo);
drivers/crypto/ccp/ccp_pmd_ops.c +30 -0
@@ -139,6 +139,36 @@ static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = { }, } }, } }, + {/* AES GCM */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type =RTE_CRYPTO_SYM_XFORM_AEAD , + {.aead = { + .algo =RTE_CRYPTO_AEAD_AES_GCM , + .block_size = 16, + .key_size = { + .min =16 , + .max = 32, + .increment = 8 + }, + .digest_size = { + .min =16 , + .max = 16, + .increment = 0 + }, + .aad_size = { + .min =0 , + .max = 65535, + .increment = 1 + }, + .iv_size = { + .min =12 , + .max = 16, + .increment = 4 + }, + }, } + }, } + },RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST () };
Signature · 1 line
2.7.4
PATCH v4 14/20 crypto/ccp: support sha1 authentication algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 367 +++++++++++++++++++++++++++++++++++++++ drivers/crypto/ccp/ccp_crypto.h | 23 +++ drivers/crypto/ccp/ccp_pmd_ops.c | 42 +++++ 3 files changed, 432 insertions(+)
drivers/crypto/ccp/ccp_crypto.c +367 -0
@@ -36,6 +36,7 @@#include <sys/queue.h> #include <sys/types.h> #include <unistd.h> +#include <openssl/sha.h> #include <openssl/cmac.h> /*sub key apis*/ #include <openssl/evp.h> /*sub key apis*/
@@ -52,6 +53,14 @@#include "ccp_pci.h" #include "ccp_pmd_private.h" +/* SHA initial context values */ +static uint32_t ccp_sha1_init[SHA_COMMON_DIGEST_SIZE /sizeof (uint32_t )] = { +SHA1_H4 ,SHA1_H3 , +SHA1_H2 ,SHA1_H1 , +SHA1_H0 ,0x0U , +0x0U ,0x0U , +}; +static enum ccp_cmd_order ccp_get_cmd_id (const struct rte_crypto_sym_xform *xform) {
@@ -76,6 +85,59 @@ ccp_get_cmd_id(const struct rte_crypto_sym_xform *xform)return res; } +/* partial hash using openssl */ +static int partial_hash_sha1 (uint8_t *data_in,uint8_t *data_out) +{ +SHA_CTX ctx; + +if (!SHA1_Init (&ctx)) +return -EFAULT ; +SHA1_Transform (&ctx, data_in); +rte_memcpy (data_out, &ctx,SHA_DIGEST_LENGTH ); +return 0 ; +} + +static int generate_partial_hash (struct ccp_session *sess) +{ + +uint8_t ipad[sess->auth.block_size]; +uint8_t opad[sess->auth.block_size]; +uint8_t *ipad_t, *opad_t; +uint32_t *hash_value_be32, hash_temp32[8 ]; +int i, count; + + opad_t = ipad_t = (uint8_t *)sess->auth.key; + + hash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute); + +/* considering key size is always equal to block size of algorithm */ +for (i =0 ; i < sess->auth.block_size; i++) { + ipad[i] = (ipad_t[i] ^HMAC_IPAD_VALUE ); + opad[i] = (opad_t[i] ^HMAC_OPAD_VALUE ); + } + +switch (sess->auth.algo) { +case CCP_AUTH_ALGO_SHA1_HMAC : + count =SHA1_DIGEST_SIZE >>2 ; + +if (partial_hash_sha1 (ipad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; + + hash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha1 (opad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; +return 0 ; +default : +CCP_LOG_ERR ("Invalid auth algo" ); +return -1 ; + } +} +/* prepare temporary keys K1 and K2 */ static void prepare_key (unsigned char *k,unsigned char *l,int bl) {
@@ -260,6 +322,31 @@ ccp_configure_session_auth(struct ccp_session *sess,else sess->auth.op =CCP_AUTH_OP_VERIFY ;switch (auth_xform->algo) { +case RTE_CRYPTO_AUTH_SHA1 : + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.algo =CCP_AUTH_ALGO_SHA1 ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_1 ; + sess->auth.ctx = (void *)ccp_sha1_init; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA1_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA1_HMAC : +if (auth_xform->key.length >SHA1_BLOCK_SIZE ) +return -1 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.algo =CCP_AUTH_ALGO_SHA1_HMAC ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_1 ; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA1_DIGEST_SIZE ; + sess->auth.block_size =SHA1_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 , sess->auth.ctx_len <<1 ); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ;case RTE_CRYPTO_AUTH_AES_CMAC : sess->auth.algo =CCP_AUTH_ALGO_AES_CMAC ; sess->auth.engine =CCP_ENGINE_AES ;
@@ -453,6 +540,13 @@ ccp_auth_slot(struct ccp_session *session)int count =0 ;switch (session->auth.algo) { +case CCP_AUTH_ALGO_SHA1 : + count =3 ; +/**< op + lsb passthrough cpy to/from*/ +break ; +case CCP_AUTH_ALGO_SHA1_HMAC : + count =6 ; +break ;case CCP_AUTH_ALGO_AES_CMAC : count =4 ;/**
@@ -578,6 +672,271 @@ ccp_perform_passthru(struct ccp_passthru *pst, }static int +ccp_perform_hmac (struct rte_crypto_op *op, +struct ccp_queue *cmd_q) +{ + +struct ccp_session *session; +union ccp_function function; +struct ccp_desc *desc; +uint32_t tail; +phys_addr_t src_addr, dest_addr, dest_addr_t; +struct ccp_passthru pst; +uint64_t auth_msg_bits; +void *append_ptr; +uint8_t *addr; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + addr = session->auth.pre_compute; + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->auth.data.offset); + append_ptr = (void *)rte_pktmbuf_append (op->sym->m_src, + session->auth.ctx_len); + dest_addr = (phys_addr_t )rte_mem_virt2phy (append_ptr); + dest_addr_t = dest_addr; + +/** Load PHash1 to LSB*/ + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *)addr); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.len = session->auth.ctx_len; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + +/**sha engine command descriptor for IntermediateHash*/ + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; + +CCP_CMD_SOC (desc) =0 ; +CCP_CMD_IOC (desc) =0 ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_PROT (desc) =0 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->auth.data.length; + auth_msg_bits = (op->sym->auth.data.length + + session->auth.block_size) *8 ; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_sha; +CCP_CMD_SHA_LO (desc) = ((uint32_t )auth_msg_bits); +CCP_CMD_SHA_HI (desc) =high32_value (auth_msg_bits); + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* Intermediate Hash value retrieve */ +if ((session->auth.ut.sha_type ==CCP_SHA_TYPE_384 ) || + (session->auth.ut.sha_type ==CCP_SHA_TYPE_512 )) { + + pst.src_addr = + (phys_addr_t)((cmd_q->sb_sha +1 ) *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t; + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t +CCP_SB_BYTES ; + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + }else { + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t; + pst.len = session->auth.ctx_len; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + } + +/** Load PHash2 to LSB*/ + addr += session->auth.ctx_len; + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *)addr); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.len = session->auth.ctx_len; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + +/**sha engine command descriptor for FinalHash*/ + dest_addr_t += session->auth.offset; + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; + +CCP_CMD_SOC (desc) =0 ; +CCP_CMD_IOC (desc) =0 ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_PROT (desc) =0 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = (session->auth.ctx_len - + session->auth.offset); + auth_msg_bits = (session->auth.block_size + + session->auth.ctx_len - + session->auth.offset) *8 ; + +CCP_CMD_SRC_LO (desc) = (uint32_t )(dest_addr_t); +CCP_CMD_SRC_HI (desc) =high32_value (dest_addr_t); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_sha; +CCP_CMD_SHA_LO (desc) = ((uint32_t )auth_msg_bits); +CCP_CMD_SHA_HI (desc) =high32_value (auth_msg_bits); + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* Retrieve hmac output */ + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr; + pst.len = session->auth.ctx_len; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; +if ((session->auth.ut.sha_type ==CCP_SHA_TYPE_384 ) || + (session->auth.ut.sha_type ==CCP_SHA_TYPE_512 )) + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +else + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; + +} + +static int +ccp_perform_sha (struct rte_crypto_op *op, +struct ccp_queue *cmd_q) +{ +struct ccp_session *session; +union ccp_function function; +struct ccp_desc *desc; +uint32_t tail; +phys_addr_t src_addr, dest_addr; +struct ccp_passthru pst; +void *append_ptr; +uint64_t auth_msg_bits; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->auth.data.offset); + + append_ptr = (void *)rte_pktmbuf_append (op->sym->m_src, + session->auth.ctx_len); + dest_addr = (phys_addr_t )rte_mem_virt2phy (append_ptr); + +/** Passthru sha context*/ + + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *) + session->auth.ctx); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.len = session->auth.ctx_len; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + +/**prepare sha command descriptor*/ + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; + +CCP_CMD_SOC (desc) =0 ; +CCP_CMD_IOC (desc) =0 ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_PROT (desc) =0 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->auth.data.length; + auth_msg_bits = op->sym->auth.data.length *8 ; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_sha; +CCP_CMD_SHA_LO (desc) = ((uint32_t )auth_msg_bits); +CCP_CMD_SHA_HI (desc) =high32_value (auth_msg_bits); + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* Hash value retrieve */ + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr; + pst.len = session->auth.ctx_len; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; +if ((session->auth.ut.sha_type ==CCP_SHA_TYPE_384 ) || + (session->auth.ut.sha_type ==CCP_SHA_TYPE_512 )) + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +else + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; + +} + +static int ccp_perform_aes_cmac (struct rte_crypto_op *op,struct ccp_queue *cmd_q) {
@@ -1143,6 +1502,14 @@ ccp_crypto_auth(struct rte_crypto_op *op, ccp_cryptodev_driver_id);switch (session->auth.algo) { +case CCP_AUTH_ALGO_SHA1 : + result =ccp_perform_sha (op, cmd_q); + b_info->desccnt +=3 ; +break ; +case CCP_AUTH_ALGO_SHA1_HMAC : + result =ccp_perform_hmac (op, cmd_q); + b_info->desccnt +=6 ; +break ;case CCP_AUTH_ALGO_AES_CMAC : result =ccp_perform_aes_cmac (op, cmd_q); b_info->desccnt +=4 ;
drivers/crypto/ccp/ccp_crypto.h +23 -0
@@ -60,9 +60,32 @@#define CCP_DES_ENCRYPT (p) ((p)->des.encrypt)#define CCP_DES_MODE (p) ((p)->des.mode)#define CCP_DES_TYPE (p) ((p)->des.type) +#define CCP_SHA_TYPE (p) ((p)->sha.type)#define CCP_PT_BYTESWAP (p) ((p)->pt.byteswap)#define CCP_PT_BITWISE (p) ((p)->pt.bitwise) +/* HMAC */ +#define HMAC_IPAD_VALUE 0x36 +#define HMAC_OPAD_VALUE 0x5c + +#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH +#define MD5_DIGEST_SIZE 16 +#define MD5_BLOCK_SIZE 64 +#endif + +/* SHA */ +#define SHA_COMMON_DIGEST_SIZE 32 +#define SHA1_DIGEST_SIZE 20 +#define SHA1_BLOCK_SIZE 64 + +/* SHA LSB intialiazation values */ + +#define SHA1_H0 0x67452301UL +#define SHA1_H1 0xefcdab89UL +#define SHA1_H2 0x98badcfeUL +#define SHA1_H3 0x10325476UL +#define SHA1_H4 0xc3d2e1f0UL +/** * CCP supported AES modes */
drivers/crypto/ccp/ccp_pmd_ops.c +42 -0
48 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v4 15/20 crypto/ccp: support sha2 family authentication algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 270 +++++++++++++++++++++++++++++++++++++++ drivers/crypto/ccp/ccp_crypto.h | 48 +++++++ drivers/crypto/ccp/ccp_pmd_ops.c | 168 ++++++++++++++++++++++++ 3 files changed, 486 insertions(+)
drivers/crypto/ccp/ccp_crypto.c +270 -0
@@ -61,6 +61,34 @@ static uint32_t ccp_sha1_init[SHA_COMMON_DIGEST_SIZE / sizeof(uint32_t)] = { 0x0U, 0x0U, }; +uint32_t ccp_sha224_init[SHA256_DIGEST_SIZE /sizeof (uint32_t )] = { +SHA224_H7 ,SHA224_H6 , +SHA224_H5 ,SHA224_H4 , +SHA224_H3 ,SHA224_H2 , +SHA224_H1 ,SHA224_H0 , +}; + +uint32_t ccp_sha256_init[SHA256_DIGEST_SIZE /sizeof (uint32_t )] = { +SHA256_H7 ,SHA256_H6 , +SHA256_H5 ,SHA256_H4 , +SHA256_H3 ,SHA256_H2 , +SHA256_H1 ,SHA256_H0 , +}; + +uint64_t ccp_sha384_init[SHA512_DIGEST_SIZE /sizeof (uint64_t )] = { +SHA384_H7 ,SHA384_H6 , +SHA384_H5 ,SHA384_H4 , +SHA384_H3 ,SHA384_H2 , +SHA384_H1 ,SHA384_H0 , +}; + +uint64_t ccp_sha512_init[SHA512_DIGEST_SIZE /sizeof (uint64_t )] = { +SHA512_H7 ,SHA512_H6 , +SHA512_H5 ,SHA512_H4 , +SHA512_H3 ,SHA512_H2 , +SHA512_H1 ,SHA512_H0 , +}; +static enum ccp_cmd_order ccp_get_cmd_id (const struct rte_crypto_sym_xform *xform) {
@@ -97,6 +125,54 @@ static int partial_hash_sha1(uint8_t *data_in, uint8_t *data_out)return 0 ; } +static int partial_hash_sha224 (uint8_t *data_in,uint8_t *data_out) +{ +SHA256_CTX ctx; + +if (!SHA224_Init (&ctx)) +return -EFAULT ; +SHA256_Transform (&ctx, data_in); +rte_memcpy (data_out, &ctx, +SHA256_DIGEST_LENGTH ); +return 0 ; +} + +static int partial_hash_sha256 (uint8_t *data_in,uint8_t *data_out) +{ +SHA256_CTX ctx; + +if (!SHA256_Init (&ctx)) +return -EFAULT ; +SHA256_Transform (&ctx, data_in); +rte_memcpy (data_out, &ctx, +SHA256_DIGEST_LENGTH ); +return 0 ; +} + +static int partial_hash_sha384 (uint8_t *data_in,uint8_t *data_out) +{ +SHA512_CTX ctx; + +if (!SHA384_Init (&ctx)) +return -EFAULT ; +SHA512_Transform (&ctx, data_in); +rte_memcpy (data_out, &ctx, +SHA512_DIGEST_LENGTH ); +return 0 ; +} + +static int partial_hash_sha512 (uint8_t *data_in,uint8_t *data_out) +{ +SHA512_CTX ctx; + +if (!SHA512_Init (&ctx)) +return -EFAULT ; +SHA512_Transform (&ctx, data_in); +rte_memcpy (data_out, &ctx, +SHA512_DIGEST_LENGTH ); +return 0 ; +} +static int generate_partial_hash (struct ccp_session *sess) {
@@ -104,11 +180,13 @@ static int generate_partial_hash(struct ccp_session *sess)uint8_t opad[sess->auth.block_size];uint8_t *ipad_t, *opad_t;uint32_t *hash_value_be32, hash_temp32[8 ]; +uint64_t *hash_value_be64, hash_temp64[8 ];int i, count; opad_t = ipad_t = (uint8_t *)sess->auth.key; hash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute); + hash_value_be64 = (uint64_t *)((uint8_t *)sess->auth.pre_compute);/* considering key size is always equal to block size of algorithm */ for (i =0 ; i < sess->auth.block_size; i++) {
@@ -132,6 +210,66 @@ static int generate_partial_hash(struct ccp_session *sess)for (i =0 ; i < count; i++, hash_value_be32++) *hash_value_be32 = hash_temp32[count -1 - i];return 0 ; +case CCP_AUTH_ALGO_SHA224_HMAC : + count =SHA256_DIGEST_SIZE >>2 ; + +if (partial_hash_sha224 (ipad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; + + hash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha224 (opad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; +return 0 ; +case CCP_AUTH_ALGO_SHA256_HMAC : + count =SHA256_DIGEST_SIZE >>2 ; + +if (partial_hash_sha256 (ipad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; + + hash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha256 (opad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; +return 0 ; +case CCP_AUTH_ALGO_SHA384_HMAC : + count =SHA512_DIGEST_SIZE >>3 ; + +if (partial_hash_sha384 (ipad, (uint8_t *)hash_temp64)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be64++) + *hash_value_be64 = hash_temp64[count -1 - i]; + + hash_value_be64 = (uint64_t *)((uint8_t *)sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha384 (opad, (uint8_t *)hash_temp64)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be64++) + *hash_value_be64 = hash_temp64[count -1 - i]; +return 0 ; +case CCP_AUTH_ALGO_SHA512_HMAC : + count =SHA512_DIGEST_SIZE >>3 ; + +if (partial_hash_sha512 (ipad, (uint8_t *)hash_temp64)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be64++) + *hash_value_be64 = hash_temp64[count -1 - i]; + + hash_value_be64 = (uint64_t *)((uint8_t *)sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha512 (opad, (uint8_t *)hash_temp64)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be64++) + *hash_value_be64 = hash_temp64[count -1 - i]; +return 0 ;default :CCP_LOG_ERR ("Invalid auth algo" );return -1 ;
@@ -347,6 +485,107 @@ ccp_configure_session_auth(struct ccp_session *sess,if (generate_partial_hash (sess))return -1 ;break ; +case RTE_CRYPTO_AUTH_SHA224 : + sess->auth.algo =CCP_AUTH_ALGO_SHA224 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_224 ; + sess->auth.ctx = (void *)ccp_sha224_init; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA224_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA224_HMAC : +if (auth_xform->key.length >SHA224_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA224_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_224 ; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA224_DIGEST_SIZE ; + sess->auth.block_size =SHA224_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 , sess->auth.ctx_len <<1 ); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ; +case RTE_CRYPTO_AUTH_SHA256 : + sess->auth.algo =CCP_AUTH_ALGO_SHA256 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_256 ; + sess->auth.ctx = (void *)ccp_sha256_init; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA256_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA256_HMAC : +if (auth_xform->key.length >SHA256_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA256_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_256 ; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA256_DIGEST_SIZE ; + sess->auth.block_size =SHA256_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 , sess->auth.ctx_len <<1 ); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ; +case RTE_CRYPTO_AUTH_SHA384 : + sess->auth.algo =CCP_AUTH_ALGO_SHA384 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_384 ; + sess->auth.ctx = (void *)ccp_sha384_init; + sess->auth.ctx_len =CCP_SB_BYTES <<1 ; + sess->auth.offset = (CCP_SB_BYTES <<1 ) -SHA384_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA384_HMAC : +if (auth_xform->key.length >SHA384_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA384_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_384 ; + sess->auth.ctx_len =CCP_SB_BYTES <<1 ; + sess->auth.offset = (CCP_SB_BYTES <<1 ) -SHA384_DIGEST_SIZE ; + sess->auth.block_size =SHA384_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 , sess->auth.ctx_len <<1 ); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ; +case RTE_CRYPTO_AUTH_SHA512 : + sess->auth.algo =CCP_AUTH_ALGO_SHA512 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_512 ; + sess->auth.ctx = (void *)ccp_sha512_init; + sess->auth.ctx_len =CCP_SB_BYTES <<1 ; + sess->auth.offset = (CCP_SB_BYTES <<1 ) -SHA512_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA512_HMAC : +if (auth_xform->key.length >SHA512_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA512_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_512 ; + sess->auth.ctx_len =CCP_SB_BYTES <<1 ; + sess->auth.offset = (CCP_SB_BYTES <<1 ) -SHA512_DIGEST_SIZE ; + sess->auth.block_size =SHA512_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 , sess->auth.ctx_len <<1 ); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ; +case RTE_CRYPTO_AUTH_AES_CMAC : sess->auth.algo =CCP_AUTH_ALGO_AES_CMAC ; sess->auth.engine =CCP_ENGINE_AES ;
@@ -541,12 +780,32 @@ ccp_auth_slot(struct ccp_session *session)switch (session->auth.algo) {case CCP_AUTH_ALGO_SHA1 : +case CCP_AUTH_ALGO_SHA224 : +case CCP_AUTH_ALGO_SHA256 : +case CCP_AUTH_ALGO_SHA384 : +case CCP_AUTH_ALGO_SHA512 : count =3 ;/**< op + lsb passthrough cpy to/from*/ break ;case CCP_AUTH_ALGO_SHA1_HMAC : +case CCP_AUTH_ALGO_SHA224_HMAC : +case CCP_AUTH_ALGO_SHA256_HMAC : count =6 ;break ; +case CCP_AUTH_ALGO_SHA384_HMAC : +case CCP_AUTH_ALGO_SHA512_HMAC : + count =7 ; +/** +* 1. Load PHash1 = H(k ^ ipad); to LSB +* 2. generate IHash = H(hash on meassage with PHash1 +* as init values); +* 3. Retrieve IHash 2 slots for 384/512 +* 4. Load Phash2 = H(k ^ opad); to LSB +* 5. generate FHash = H(hash on Ihash with Phash2 +* as init value); +* 6. Retrieve HMAC output from LSB to host memory +*/ +break ;case CCP_AUTH_ALGO_AES_CMAC : count =4 ;/**
@@ -1503,13 +1762,24 @@ ccp_crypto_auth(struct rte_crypto_op *op,switch (session->auth.algo) {case CCP_AUTH_ALGO_SHA1 : +case CCP_AUTH_ALGO_SHA224 : +case CCP_AUTH_ALGO_SHA256 : +case CCP_AUTH_ALGO_SHA384 : +case CCP_AUTH_ALGO_SHA512 : result =ccp_perform_sha (op, cmd_q); b_info->desccnt +=3 ;break ;case CCP_AUTH_ALGO_SHA1_HMAC : +case CCP_AUTH_ALGO_SHA224_HMAC : +case CCP_AUTH_ALGO_SHA256_HMAC : result =ccp_perform_hmac (op, cmd_q); b_info->desccnt +=6 ;break ; +case CCP_AUTH_ALGO_SHA384_HMAC : +case CCP_AUTH_ALGO_SHA512_HMAC : + result =ccp_perform_hmac (op, cmd_q); + b_info->desccnt +=7 ; +break ;case CCP_AUTH_ALGO_AES_CMAC : result =ccp_perform_aes_cmac (op, cmd_q); b_info->desccnt +=4 ;
drivers/crypto/ccp/ccp_crypto.h +48 -0
60 lines not on this page · raw message
drivers/crypto/ccp/ccp_pmd_ops.c +168 -0
174 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v4 16/20 crypto/ccp: support sha3 family authentication algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 667 +++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_crypto.h | 22 ++ drivers/crypto/ccp/ccp_pmd_ops.c | 168 +++++++++ lib/librte_cryptodev/rte_crypto_sym.h | 17 + 4 files changed, 873 insertions(+), 1 deletion(-)
drivers/crypto/ccp/ccp_crypto.c +666 -1
@@ -89,6 +89,74 @@ uint64_t ccp_sha512_init[SHA512_DIGEST_SIZE / sizeof(uint64_t)] = { SHA512_H1, SHA512_H0, }; +#if defined(_MSC_VER) +#define SHA3_CONST (x) x +#else +#define SHA3_CONST (x) x##L +#endif + +/** 'Words' here refers to uint64_t */ +#define SHA3_KECCAK_SPONGE_WORDS \ + (((1600) / 8) / sizeof(uint64_t)) +typedef struct sha3_context_ { +uint64_t saved; +/** +* The portion of the input message that we +* didn't consume yet +*/ +union { +uint64_t s[SHA3_KECCAK_SPONGE_WORDS ]; +/* Keccak's state */ +uint8_t sb[SHA3_KECCAK_SPONGE_WORDS *8 ]; +/**total 200 ctx size**/ + }; +unsigned int byteIndex; +/** +* 0..7--the next byte after the set one +* (starts from 0; 0--none are buffered) +*/ +unsigned int wordIndex; +/** +* 0..24--the next word to integrate input +* (starts from 0) +*/ +unsigned int capacityWords; +/** +* the double size of the hash output in +* words (e.g. 16 for Keccak 512) +*/ +}sha3_context ; + +#ifndef SHA3_ROTL64 +#define SHA3_ROTL64 (x, y) \ + (((x) << (y)) | ((x) >> ((sizeof(uint64_t)*8) - (y)))) +#endif + +static const uint64_t keccakf_rndc[24 ] = { +SHA3_CONST (0x0000000000000001UL ),SHA3_CONST (0x0000000000008082UL ), +SHA3_CONST (0x800000000000808aUL ),SHA3_CONST (0x8000000080008000UL ), +SHA3_CONST (0x000000000000808bUL ),SHA3_CONST (0x0000000080000001UL ), +SHA3_CONST (0x8000000080008081UL ),SHA3_CONST (0x8000000000008009UL ), +SHA3_CONST (0x000000000000008aUL ),SHA3_CONST (0x0000000000000088UL ), +SHA3_CONST (0x0000000080008009UL ),SHA3_CONST (0x000000008000000aUL ), +SHA3_CONST (0x000000008000808bUL ),SHA3_CONST (0x800000000000008bUL ), +SHA3_CONST (0x8000000000008089UL ),SHA3_CONST (0x8000000000008003UL ), +SHA3_CONST (0x8000000000008002UL ),SHA3_CONST (0x8000000000000080UL ), +SHA3_CONST (0x000000000000800aUL ),SHA3_CONST (0x800000008000000aUL ), +SHA3_CONST (0x8000000080008081UL ),SHA3_CONST (0x8000000000008080UL ), +SHA3_CONST (0x0000000080000001UL ),SHA3_CONST (0x8000000080008008UL ) +}; + +static const unsigned int keccakf_rotc[24 ] = { +1 ,3 ,6 ,10 ,15 ,21 ,28 ,36 ,45 ,55 ,2 ,14 ,27 ,41 ,56 ,8 ,25 ,43 ,62 , +18 ,39 ,61 ,20 ,44 +}; + +static const unsigned int keccakf_piln[24 ] = { +10 ,7 ,11 ,17 ,18 ,3 ,5 ,16 ,8 ,21 ,24 ,4 ,15 ,23 ,19 ,13 ,12 ,2 ,20 , +14 ,22 ,9 ,6 ,1 +}; +static enum ccp_cmd_order ccp_get_cmd_id (const struct rte_crypto_sym_xform *xform) {
@@ -173,6 +241,223 @@ static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)return 0 ; } +static void +keccakf (uint64_t s[25 ]) +{ +int i, j, round; +uint64_t t, bc[5 ]; +#define KECCAK_ROUNDS 24 + +for (round =0 ; round <KECCAK_ROUNDS ; round++) { + +/* Theta */ +for (i =0 ; i <5 ; i++) + bc[i] = s[i] ^ s[i +5 ] ^ s[i +10 ] ^ s[i +15 ] ^ + s[i +20 ]; + +for (i =0 ; i <5 ; i++) { + t = bc[(i +4 ) %5 ] ^SHA3_ROTL64 (bc[(i +1 ) %5 ],1 ); +for (j =0 ; j <25 ; j +=5 ) + s[j + i] ^= t; + } + +/* Rho Pi */ + t = s[1 ]; +for (i =0 ; i <24 ; i++) { + j = keccakf_piln[i]; + bc[0 ] = s[j]; + s[j] =SHA3_ROTL64 (t, keccakf_rotc[i]); + t = bc[0 ]; + } + +/* Chi */ +for (j =0 ; j <25 ; j +=5 ) { +for (i =0 ; i <5 ; i++) + bc[i] = s[j + i]; +for (i =0 ; i <5 ; i++) + s[j + i] ^= (~bc[(i +1 ) %5 ]) & + bc[(i +2 ) %5 ]; + } + +/* Iota */ + s[0 ] ^= keccakf_rndc[round]; + } +} + +static void +sha3_Init224 (void *priv) +{ +sha3_context *ctx = (sha3_context *) priv; + +memset (ctx,0 ,sizeof (*ctx)); + ctx->capacityWords =2 *224 / (8 *sizeof (uint64_t )); +} + +static void +sha3_Init256 (void *priv) +{ +sha3_context *ctx = (sha3_context *) priv; + +memset (ctx,0 ,sizeof (*ctx)); + ctx->capacityWords =2 *256 / (8 *sizeof (uint64_t )); +} + +static void +sha3_Init384 (void *priv) +{ +sha3_context *ctx = (sha3_context *) priv; + +memset (ctx,0 ,sizeof (*ctx)); + ctx->capacityWords =2 *384 / (8 *sizeof (uint64_t )); +} + +static void +sha3_Init512 (void *priv) +{ +sha3_context *ctx = (sha3_context *) priv; + +memset (ctx,0 ,sizeof (*ctx)); + ctx->capacityWords =2 *512 / (8 *sizeof (uint64_t )); +} + + +/* This is simply the 'update' with the padding block. +* The padding block is 0x01 || 0x00* || 0x80. First 0x01 and last 0x80 +* bytes are always present, but they can be the same byte. +*/ +static void +sha3_Update (void *priv,void const *bufIn,size_t len) +{ +sha3_context *ctx = (sha3_context *) priv; +unsigned int old_tail = (8 - ctx->byteIndex) &7 ; +size_t words; +unsigned int tail; +size_t i; +const uint8_t *buf = bufIn; + +if (len < old_tail) { +while (len--) + ctx->saved |= (uint64_t ) (*(buf++)) << + ((ctx->byteIndex++) *8 ); +return ; + } + +if (old_tail) { + len -= old_tail; +while (old_tail--) + ctx->saved |= (uint64_t ) (*(buf++)) << + ((ctx->byteIndex++) *8 ); + + ctx->s[ctx->wordIndex] ^= ctx->saved; + ctx->byteIndex =0 ; + ctx->saved =0 ; +if (++ctx->wordIndex == + (SHA3_KECCAK_SPONGE_WORDS - ctx->capacityWords)) { +keccakf (ctx->s); + ctx->wordIndex =0 ; + } + } + + words = len /sizeof (uint64_t ); + tail = len - words *sizeof (uint64_t ); + +for (i =0 ; i < words; i++, buf +=sizeof (uint64_t )) { +const uint64_t t = (uint64_t ) (buf[0 ]) | + ((uint64_t ) (buf[1 ]) <<8 *1 ) | + ((uint64_t ) (buf[2 ]) <<8 *2 ) | + ((uint64_t ) (buf[3 ]) <<8 *3 ) | + ((uint64_t ) (buf[4 ]) <<8 *4 ) | + ((uint64_t ) (buf[5 ]) <<8 *5 ) | + ((uint64_t ) (buf[6 ]) <<8 *6 ) | + ((uint64_t ) (buf[7 ]) <<8 *7 ); + ctx->s[ctx->wordIndex] ^= t; +if (++ctx->wordIndex == + (SHA3_KECCAK_SPONGE_WORDS - ctx->capacityWords)) { +keccakf (ctx->s); + ctx->wordIndex =0 ; + } + } + +while (tail--) + ctx->saved |= (uint64_t ) (*(buf++)) << ((ctx->byteIndex++) *8 ); +} + +int partial_hash_sha3_224 (uint8_t *data_in,uint8_t *data_out) +{ +sha3_context *ctx; +int i; + + ctx =rte_zmalloc ("sha3-ctx" ,sizeof (sha3_context),0 ); +if (!ctx) { +CCP_LOG_ERR ("sha3-ctx creation failed" ); +return -ENOMEM ; + } +sha3_Init224 (ctx); +sha3_Update (ctx, data_in,SHA3_224_BLOCK_SIZE ); +for (i =0 ; i <CCP_SHA3_CTX_SIZE ; i++, data_out++) + *data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i -1 ]; +rte_free (ctx); + +return 0 ; +} + +int partial_hash_sha3_256 (uint8_t *data_in,uint8_t *data_out) +{ +sha3_context *ctx; +int i; + + ctx =rte_zmalloc ("sha3-ctx" ,sizeof (sha3_context),0 ); +if (!ctx) { +CCP_LOG_ERR ("sha3-ctx creation failed" ); +return -ENOMEM ; + } +sha3_Init256 (ctx); +sha3_Update (ctx, data_in,SHA3_256_BLOCK_SIZE ); +for (i =0 ; i <CCP_SHA3_CTX_SIZE ; i++, data_out++) + *data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i -1 ]; +rte_free (ctx); + +return 0 ; +} + +int partial_hash_sha3_384 (uint8_t *data_in,uint8_t *data_out) +{ +sha3_context *ctx; +int i; + + ctx =rte_zmalloc ("sha3-ctx" ,sizeof (sha3_context),0 ); +if (!ctx) { +CCP_LOG_ERR ("sha3-ctx creation failed" ); +return -ENOMEM ; + } +sha3_Init384 (ctx); +sha3_Update (ctx, data_in,SHA3_384_BLOCK_SIZE ); +for (i =0 ; i <CCP_SHA3_CTX_SIZE ; i++, data_out++) + *data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i -1 ]; +rte_free (ctx); + +return 0 ; +} + +int partial_hash_sha3_512 (uint8_t *data_in,uint8_t *data_out) +{ +sha3_context *ctx; +int i; + + ctx =rte_zmalloc ("sha3-ctx" ,sizeof (sha3_context),0 ); +if (!ctx) { +CCP_LOG_ERR ("sha3-ctx creation failed" ); +return -ENOMEM ; + } +sha3_Init512 (ctx); +sha3_Update (ctx, data_in,SHA3_512_BLOCK_SIZE ); +for (i =0 ; i <CCP_SHA3_CTX_SIZE ; i++, data_out++) + *data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i -1 ]; +rte_free (ctx); + +return 0 ; +} +static int generate_partial_hash (struct ccp_session *sess) {
@@ -182,6 +467,7 @@ static int generate_partial_hash(struct ccp_session *sess)uint32_t *hash_value_be32, hash_temp32[8 ];uint64_t *hash_value_be64, hash_temp64[8 ];int i, count; +uint8_t *hash_value_sha3; opad_t = ipad_t = (uint8_t *)sess->auth.key;
@@ -225,6 +511,16 @@ static int generate_partial_hash(struct ccp_session *sess)for (i =0 ; i < count; i++, hash_value_be32++) *hash_value_be32 = hash_temp32[count -1 - i];return 0 ; +case CCP_AUTH_ALGO_SHA3_224_HMAC : + hash_value_sha3 = sess->auth.pre_compute; +if (partial_hash_sha3_224 (ipad, hash_value_sha3)) +return -1 ; + + hash_value_sha3 = (uint8_t *)(sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha3_224 (opad, hash_value_sha3)) +return -1 ; +return 0 ;case CCP_AUTH_ALGO_SHA256_HMAC : count =SHA256_DIGEST_SIZE >>2 ;
@@ -240,6 +536,16 @@ static int generate_partial_hash(struct ccp_session *sess)for (i =0 ; i < count; i++, hash_value_be32++) *hash_value_be32 = hash_temp32[count -1 - i];return 0 ; +case CCP_AUTH_ALGO_SHA3_256_HMAC : + hash_value_sha3 = sess->auth.pre_compute; +if (partial_hash_sha3_256 (ipad, hash_value_sha3)) +return -1 ; + + hash_value_sha3 = (uint8_t *)(sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha3_256 (opad, hash_value_sha3)) +return -1 ; +return 0 ;case CCP_AUTH_ALGO_SHA384_HMAC : count =SHA512_DIGEST_SIZE >>3 ;
@@ -255,6 +561,16 @@ static int generate_partial_hash(struct ccp_session *sess)for (i =0 ; i < count; i++, hash_value_be64++) *hash_value_be64 = hash_temp64[count -1 - i];return 0 ; +case CCP_AUTH_ALGO_SHA3_384_HMAC : + hash_value_sha3 = sess->auth.pre_compute; +if (partial_hash_sha3_384 (ipad, hash_value_sha3)) +return -1 ; + + hash_value_sha3 = (uint8_t *)(sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha3_384 (opad, hash_value_sha3)) +return -1 ; +return 0 ;case CCP_AUTH_ALGO_SHA512_HMAC : count =SHA512_DIGEST_SIZE >>3 ;
@@ -270,6 +586,16 @@ static int generate_partial_hash(struct ccp_session *sess)for (i =0 ; i < count; i++, hash_value_be64++) *hash_value_be64 = hash_temp64[count -1 - i];return 0 ; +case CCP_AUTH_ALGO_SHA3_512_HMAC : + hash_value_sha3 = sess->auth.pre_compute; +if (partial_hash_sha3_512 (ipad, hash_value_sha3)) +return -1 ; + + hash_value_sha3 = (uint8_t *)(sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha3_512 (opad, hash_value_sha3)) +return -1 ; +return 0 ;default :CCP_LOG_ERR ("Invalid auth algo" );return -1 ;
@@ -510,6 +836,30 @@ ccp_configure_session_auth(struct ccp_session *sess,if (generate_partial_hash (sess))return -1 ;break ; +case RTE_CRYPTO_AUTH_SHA3_224 : + sess->auth.algo =CCP_AUTH_ALGO_SHA3_224 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_224 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA224_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA3_224_HMAC : +if (auth_xform->key.length >SHA3_224_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA3_224_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_224 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA224_DIGEST_SIZE ; + sess->auth.block_size =SHA3_224_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 ,2 * sess->auth.ctx_len); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ;case RTE_CRYPTO_AUTH_SHA256 : sess->auth.algo =CCP_AUTH_ALGO_SHA256 ; sess->auth.engine =CCP_ENGINE_SHA ;
@@ -535,6 +885,30 @@ ccp_configure_session_auth(struct ccp_session *sess,if (generate_partial_hash (sess))return -1 ;break ; +case RTE_CRYPTO_AUTH_SHA3_256 : + sess->auth.algo =CCP_AUTH_ALGO_SHA3_256 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_256 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA256_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA3_256_HMAC : +if (auth_xform->key.length >SHA3_256_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA3_256_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_256 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA256_DIGEST_SIZE ; + sess->auth.block_size =SHA3_256_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 ,2 * sess->auth.ctx_len); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ;case RTE_CRYPTO_AUTH_SHA384 : sess->auth.algo =CCP_AUTH_ALGO_SHA384 ; sess->auth.engine =CCP_ENGINE_SHA ;
@@ -560,6 +934,30 @@ ccp_configure_session_auth(struct ccp_session *sess,if (generate_partial_hash (sess))return -1 ;break ; +case RTE_CRYPTO_AUTH_SHA3_384 : + sess->auth.algo =CCP_AUTH_ALGO_SHA3_384 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_384 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA384_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA3_384_HMAC : +if (auth_xform->key.length >SHA3_384_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA3_384_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_384 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA384_DIGEST_SIZE ; + sess->auth.block_size =SHA3_384_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 ,2 * sess->auth.ctx_len); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ;case RTE_CRYPTO_AUTH_SHA512 : sess->auth.algo =CCP_AUTH_ALGO_SHA512 ; sess->auth.engine =CCP_ENGINE_SHA ;
@@ -585,7 +983,30 @@ ccp_configure_session_auth(struct ccp_session *sess,if (generate_partial_hash (sess))return -1 ;break ; - +case RTE_CRYPTO_AUTH_SHA3_512 : + sess->auth.algo =CCP_AUTH_ALGO_SHA3_512 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_512 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA512_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA3_512_HMAC : +if (auth_xform->key.length >SHA3_512_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA3_512_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_512 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA512_DIGEST_SIZE ; + sess->auth.block_size =SHA3_512_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 ,2 * sess->auth.ctx_len); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ;case RTE_CRYPTO_AUTH_AES_CMAC : sess->auth.algo =CCP_AUTH_ALGO_AES_CMAC ; sess->auth.engine =CCP_ENGINE_AES ;
@@ -806,6 +1227,26 @@ ccp_auth_slot(struct ccp_session *session)* 6. Retrieve HMAC output from LSB to host memory */ break ; +case CCP_AUTH_ALGO_SHA3_224 : +case CCP_AUTH_ALGO_SHA3_256 : +case CCP_AUTH_ALGO_SHA3_384 : +case CCP_AUTH_ALGO_SHA3_512 : + count =1 ; +/**< only op ctx and dst in host memory*/ +break ; +case CCP_AUTH_ALGO_SHA3_224_HMAC : +case CCP_AUTH_ALGO_SHA3_256_HMAC : + count =3 ; +break ; +case CCP_AUTH_ALGO_SHA3_384_HMAC : +case CCP_AUTH_ALGO_SHA3_512_HMAC : + count =4 ; +/** +* 1. Op to Perform Ihash +* 2. Retrieve result from LSB to host memory +* 3. Perform final hash +*/ +break ;case CCP_AUTH_ALGO_AES_CMAC : count =4 ;/**
@@ -1196,6 +1637,213 @@ ccp_perform_sha(struct rte_crypto_op *op, }static int +ccp_perform_sha3_hmac (struct rte_crypto_op *op, +struct ccp_queue *cmd_q) +{ +struct ccp_session *session; +struct ccp_passthru pst; +union ccp_function function; +struct ccp_desc *desc; +uint8_t *append_ptr; +uint32_t tail; +phys_addr_t src_addr, dest_addr, ctx_paddr, dest_addr_t; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->auth.data.offset); + append_ptr = (uint8_t *)rte_pktmbuf_append (op->sym->m_src, + session->auth.ctx_len); +if (!append_ptr) { +CCP_LOG_ERR ("CCP MBUF append failed\n" ); +return -1 ; + } + dest_addr = (phys_addr_t )rte_mem_virt2phy ((void *)append_ptr); + dest_addr_t = dest_addr + (session->auth.ctx_len /2 ); + ctx_paddr = (phys_addr_t )rte_mem_virt2phy ((void + *)session->auth.pre_compute); + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +/*desc1 for SHA3-Ihash operation */ +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; +CCP_CMD_LEN (desc) = op->sym->auth.data.length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = (cmd_q->sb_sha *CCP_SB_BYTES ); +CCP_CMD_DST_HI (desc) =0 ; +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SB ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )ctx_paddr); +CCP_CMD_KEY_HI (desc) =high32_value (ctx_paddr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* Intermediate Hash value retrieve */ +if ((session->auth.ut.sha_type ==CCP_SHA3_TYPE_384 ) || + (session->auth.ut.sha_type ==CCP_SHA3_TYPE_512 )) { + + pst.src_addr = + (phys_addr_t)((cmd_q->sb_sha +1 ) *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t; + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t +CCP_SB_BYTES ; + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + }else { + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t; + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + } + +/**sha engine command descriptor for FinalHash*/ + ctx_paddr +=CCP_SHA3_CTX_SIZE ; + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +if (session->auth.ut.sha_type ==CCP_SHA3_TYPE_224 ) { + dest_addr_t += (CCP_SB_BYTES -SHA224_DIGEST_SIZE ); +CCP_CMD_LEN (desc) =SHA224_DIGEST_SIZE ; + }else if (session->auth.ut.sha_type ==CCP_SHA3_TYPE_256 ) { +CCP_CMD_LEN (desc) =SHA256_DIGEST_SIZE ; + }else if (session->auth.ut.sha_type ==CCP_SHA3_TYPE_384 ) { + dest_addr_t += (2 *CCP_SB_BYTES -SHA384_DIGEST_SIZE ); +CCP_CMD_LEN (desc) =SHA384_DIGEST_SIZE ; + }else { +CCP_CMD_LEN (desc) =SHA512_DIGEST_SIZE ; + } + +CCP_CMD_SRC_LO (desc) = ((uint32_t )dest_addr_t); +CCP_CMD_SRC_HI (desc) =high32_value (dest_addr_t); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = (uint32_t )dest_addr; +CCP_CMD_DST_HI (desc) =high32_value (dest_addr); +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )ctx_paddr); +CCP_CMD_KEY_HI (desc) =high32_value (ctx_paddr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} + +static int +ccp_perform_sha3 (struct rte_crypto_op *op, +struct ccp_queue *cmd_q) +{ +struct ccp_session *session; +union ccp_function function; +struct ccp_desc *desc; +uint8_t *ctx_addr, *append_ptr; +uint32_t tail; +phys_addr_t src_addr, dest_addr, ctx_paddr; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->auth.data.offset); + append_ptr = (uint8_t *)rte_pktmbuf_append (op->sym->m_src, + session->auth.ctx_len); +if (!append_ptr) { +CCP_LOG_ERR ("CCP MBUF append failed\n" ); +return -1 ; + } + dest_addr = (phys_addr_t )rte_mem_virt2phy ((void *)append_ptr); + ctx_addr = session->auth.sha3_ctx; + ctx_paddr = (phys_addr_t )rte_mem_virt2phy ((void *)ctx_addr); + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +/* prepare desc for SHA3 operation */ +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->auth.data.length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = ((uint32_t )dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (dest_addr); +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )ctx_paddr); +CCP_CMD_KEY_HI (desc) =high32_value (ctx_paddr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} + +static int ccp_perform_aes_cmac (struct rte_crypto_op *op,struct ccp_queue *cmd_q) {
@@ -1780,6 +2428,23 @@ ccp_crypto_auth(struct rte_crypto_op *op, result =ccp_perform_hmac (op, cmd_q); b_info->desccnt +=7 ;break ; +case CCP_AUTH_ALGO_SHA3_224 : +case CCP_AUTH_ALGO_SHA3_256 : +case CCP_AUTH_ALGO_SHA3_384 : +case CCP_AUTH_ALGO_SHA3_512 : + result =ccp_perform_sha3 (op, cmd_q); + b_info->desccnt +=1 ; +break ; +case CCP_AUTH_ALGO_SHA3_224_HMAC : +case CCP_AUTH_ALGO_SHA3_256_HMAC : + result =ccp_perform_sha3_hmac (op, cmd_q); + b_info->desccnt +=3 ; +break ; +case CCP_AUTH_ALGO_SHA3_384_HMAC : +case CCP_AUTH_ALGO_SHA3_512_HMAC : + result =ccp_perform_sha3_hmac (op, cmd_q); + b_info->desccnt +=4 ; +break ;case CCP_AUTH_ALGO_AES_CMAC : result =ccp_perform_aes_cmac (op, cmd_q); b_info->desccnt +=4 ;
drivers/crypto/ccp/ccp_crypto.h +22 -0
@@ -80,15 +80,19 @@#define SHA224_DIGEST_SIZE 28#define SHA224_BLOCK_SIZE 64 +#define SHA3_224_BLOCK_SIZE 144#define SHA256_DIGEST_SIZE 32#define SHA256_BLOCK_SIZE 64 +#define SHA3_256_BLOCK_SIZE 136#define SHA384_DIGEST_SIZE 48#define SHA384_BLOCK_SIZE 128 +#define SHA3_384_BLOCK_SIZE 104#define SHA512_DIGEST_SIZE 64#define SHA512_BLOCK_SIZE 128 +#define SHA3_512_BLOCK_SIZE 72/* SHA LSB intialiazation values */
@@ -386,4 +390,22 @@ int process_ops_to_dequeue(struct ccp_qp *qp,struct rte_crypto_op **op, uint16_t nb_ops); + +/** +* Apis for SHA3 partial hash generation +* @param data_in buffer pointer on which phash is applied +* @param data_out phash result in ccp be format is written +*/ +int partial_hash_sha3_224 (uint8_t *data_in, +uint8_t *data_out); + +int partial_hash_sha3_256 (uint8_t *data_in, +uint8_t *data_out); + +int partial_hash_sha3_384 (uint8_t *data_in, +uint8_t *data_out); + +int partial_hash_sha3_512 (uint8_t *data_in, +uint8_t *data_out); +#endif /* _CCP_CRYPTO_H_ */
drivers/crypto/ccp/ccp_pmd_ops.c +168 -0
192 lines not on this page · raw message
lib/librte_cryptodev/rte_crypto_sym.h +17 -0
@@ -245,6 +245,23 @@ enum rte_crypto_auth_algorithm {RTE_CRYPTO_AUTH_ZUC_EIA3 ,/**< ZUC algorithm in EIA3 mode */ +RTE_CRYPTO_AUTH_SHA3_224 , +/**< 224 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_224_HMAC , +/**< HMAC using 224 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_256 , +/**< 256 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_256_HMAC , +/**< HMAC using 256 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_384 , +/**< 384 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_384_HMAC , +/**< HMAC using 384 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_512 , +/**< 512 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_512_HMAC , +/**< HMAC using 512 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_LIST_END };
Signature · 1 line
2.7.4
PATCH v4 17/20 crypto/ccp: support cpu based md5 and sha2 family authentication algo
In reply to Ravi Kumar--- config/common_base | 1 + drivers/crypto/ccp/ccp_crypto.c | 282 ++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_crypto.h | 5 +- drivers/crypto/ccp/ccp_pmd_ops.c | 23 +++ drivers/crypto/ccp/ccp_pmd_private.h | 10 ++ 5 files changed, 316 insertions(+), 5 deletions(-)
config/common_base +1 -0
@@ -532,6 +532,7 @@ CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y # Compile PMD for AMD CCP crypto device # CONFIG_RTE_LIBRTE_PMD_CCP=n +CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=n # # Compile PMD for Marvell Crypto device
drivers/crypto/ccp/ccp_crypto.c +278 -4
467 lines not on this page · raw message
drivers/crypto/ccp/ccp_crypto.h +4 -1
@@ -94,6 +94,9 @@#define SHA512_BLOCK_SIZE 128#define SHA3_512_BLOCK_SIZE 72 +/* Maximum length for digest */ +#define DIGEST_LENGTH_MAX 64 +/* SHA LSB intialiazation values */ #define SHA1_H0 0x67452301UL
@@ -372,7 +375,7 @@ int ccp_compute_slot_count(struct ccp_session *session);* @param nb_ops No. of ops to be submitted * @return 0 on success otherwise -1 */ -int process_ops_to_enqueue(const struct ccp_qp *qp, +int process_ops_to_enqueue(struct ccp_qp *qp, struct rte_crypto_op **op, struct ccp_queue *cmd_q, uint16_t nb_ops,
drivers/crypto/ccp/ccp_pmd_ops.c +23 -0
@@ -39,6 +39,29 @@#include "ccp_crypto.h" static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = { +#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH + {/* MD5 HMAC */ + .op =RTE_CRYPTO_OP_TYPE_SYMMETRIC , + {.sym = { + .xform_type =RTE_CRYPTO_SYM_XFORM_AUTH , + {.auth = { + .algo =RTE_CRYPTO_AUTH_MD5_HMAC , + .block_size =64 , + .key_size = { + .min =1 , + .max =64 , + .increment =1 + }, + .digest_size = { + .min =16 , + .max =16 , + .increment =0 + }, + .aad_size = {0 } + }, } + }, } + }, +#endif {/* SHA1 */ .op =RTE_CRYPTO_OP_TYPE_SYMMETRIC , {.sym = {
drivers/crypto/ccp/ccp_pmd_private.h +10 -0
@@ -32,6 +32,7 @@#define _CCP_PMD_PRIVATE_H_#include <rte_cryptodev.h> +#include "ccp_crypto.h" #define CRYPTODEV_NAME_CCP_PMD crypto_ccp
@@ -87,6 +88,10 @@ struct ccp_batch_info {phys_addr_t lsb_buf_phys;/**< LSB intermediate buf for passthru */ int lsb_buf_idx; +#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH +uint16_t auth_ctr; +/**< auth only ops batch */ +#endif } __rte_cache_aligned;/**< CCP crypto queue pair */
@@ -107,6 +112,11 @@ struct ccp_qp {/**< Store ops pulled out of queue */ struct rte_cryptodev *dev;/**< rte crypto device to which this qp belongs */ +uint8_t temp_digest[DIGEST_LENGTH_MAX ]; +/**< Buffer used to store the digest generated +* by the driver when verifying a digest provided +* by the user (using authentication verify operation) +*/ } __rte_cache_aligned;
Signature · 1 line
2.7.4
PATCH v4 18/20 test/crypto: add test for AMD CCP crypto poll mode
In reply to Ravi Kumar--- test/test/test_cryptodev.c | 161 +++++++++++++++++++++++++++ test/test/test_cryptodev.h | 1 + test/test/test_cryptodev_aes_test_vectors.h | 93 ++++++++++------ test/test/test_cryptodev_blockcipher.c | 9 +- test/test/test_cryptodev_blockcipher.h | 1 + test/test/test_cryptodev_des_test_vectors.h | 42 ++++--- test/test/test_cryptodev_hash_test_vectors.h | 60 ++++++---- 7 files changed, 301 insertions(+), 66 deletions(-)
test/test/test_cryptodev.c +161 -0
@@ -338,6 +338,23 @@ testsuite_setup(void) } } +/* Create an CCP device if required */ +if (gbl_driver_id ==rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD ))) { + nb_devs =rte_cryptodev_device_count_by_driver ( +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD ))); +if (nb_devs <1 ) { + ret =rte_vdev_init ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD ), +NULL ); + +TEST_ASSERT (ret ==0 ,"Failed to create " +"instance of pmd : %s" , +RTE_STR (CRYPTODEV_NAME_CCP_PMD )); + } + } +#ifdef RTE_LIBRTE_PMD_CRYPTO_SCHEDULER if (gbl_driver_id ==rte_cryptodev_driver_id_get (RTE_STR (CRYPTODEV_NAME_SCHEDULER_PMD ))) {
@@ -1727,6 +1744,44 @@ test_AES_cipheronly_openssl_all(void) }static int +test_AES_chain_ccp_all (void ) +{ +struct crypto_testsuite_params *ts_params = &testsuite_params; +int status; + + status =test_blockcipher_all_tests (ts_params->mbuf_pool, + ts_params->op_mpool, + ts_params->session_mpool, + ts_params->valid_devs[0 ], +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )), +BLKCIPHER_AES_CHAIN_TYPE ); + +TEST_ASSERT_EQUAL (status,0 ,"Test failed" ); + +return TEST_SUCCESS ; +} + +static int +test_AES_cipheronly_ccp_all (void ) +{ +struct crypto_testsuite_params *ts_params = &testsuite_params; +int status; + + status =test_blockcipher_all_tests (ts_params->mbuf_pool, + ts_params->op_mpool, + ts_params->session_mpool, + ts_params->valid_devs[0 ], +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )), +BLKCIPHER_AES_CIPHERONLY_TYPE ); + +TEST_ASSERT_EQUAL (status,0 ,"Test failed" ); + +return TEST_SUCCESS ; +} + +static int test_AES_chain_qat_all (void ) {struct crypto_testsuite_params *ts_params = &testsuite_params;
@@ -1898,6 +1953,25 @@ test_authonly_openssl_all(void) }static int +test_authonly_ccp_all (void ) +{ +struct crypto_testsuite_params *ts_params = &testsuite_params; +int status; + + status =test_blockcipher_all_tests (ts_params->mbuf_pool, + ts_params->op_mpool, + ts_params->session_mpool, + ts_params->valid_devs[0 ], +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )), +BLKCIPHER_AUTHONLY_TYPE ); + +TEST_ASSERT_EQUAL (status,0 ,"Test failed" ); + +return TEST_SUCCESS ; +} + +static int test_AES_chain_armv8_all (void ) {struct crypto_testsuite_params *ts_params = &testsuite_params;
@@ -4973,6 +5047,44 @@ test_3DES_cipheronly_dpaa2_sec_all(void) }static int +test_3DES_chain_ccp_all (void ) +{ +struct crypto_testsuite_params *ts_params = &testsuite_params; +int status; + + status =test_blockcipher_all_tests (ts_params->mbuf_pool, + ts_params->op_mpool, + ts_params->session_mpool, + ts_params->valid_devs[0 ], +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )), +BLKCIPHER_3DES_CHAIN_TYPE ); + +TEST_ASSERT_EQUAL (status,0 ,"Test failed" ); + +return TEST_SUCCESS ; +} + +static int +test_3DES_cipheronly_ccp_all (void ) +{ +struct crypto_testsuite_params *ts_params = &testsuite_params; +int status; + + status =test_blockcipher_all_tests (ts_params->mbuf_pool, + ts_params->op_mpool, + ts_params->session_mpool, + ts_params->valid_devs[0 ], +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )), +BLKCIPHER_3DES_CIPHERONLY_TYPE ); + +TEST_ASSERT_EQUAL (status,0 ,"Test failed" ); + +return TEST_SUCCESS ; +} + +static int test_3DES_cipheronly_qat_all (void ) {struct crypto_testsuite_params *ts_params = &testsuite_params;
@@ -9646,6 +9758,38 @@ static struct unit_test_suite cryptodev_mrvl_testsuite = { } }; +static struct unit_test_suite cryptodev_ccp_testsuite = { + .suite_name ="Crypto Device CCP Unit Test Suite" , + .setup = testsuite_setup, + .teardown = testsuite_teardown, + .unit_test_cases = { +TEST_CASE_ST (ut_setup, ut_teardown, test_multi_session), +TEST_CASE_ST (ut_setup, ut_teardown, + test_multi_session_random_usage), +TEST_CASE_ST (ut_setup, ut_teardown, + test_AES_chain_ccp_all), +TEST_CASE_ST (ut_setup, ut_teardown, + test_AES_cipheronly_ccp_all), +TEST_CASE_ST (ut_setup, ut_teardown, + test_3DES_chain_ccp_all), +TEST_CASE_ST (ut_setup, ut_teardown, + test_3DES_cipheronly_ccp_all), +TEST_CASE_ST (ut_setup, ut_teardown, + test_authonly_ccp_all), + +/** Negative tests */ +TEST_CASE_ST (ut_setup, ut_teardown, + authentication_verify_HMAC_SHA1_fail_data_corrupt), +TEST_CASE_ST (ut_setup, ut_teardown, + authentication_verify_HMAC_SHA1_fail_tag_corrupt), +TEST_CASE_ST (ut_setup, ut_teardown, + auth_decryption_AES128CBC_HMAC_SHA1_fail_data_corrupt), +TEST_CASE_ST (ut_setup, ut_teardown, + auth_decryption_AES128CBC_HMAC_SHA1_fail_tag_corrupt), + +TEST_CASES_END ()/**< NULL terminate unit test array */ + } +};static int test_cryptodev_qat (void /*argv __rte_unused, int argc __rte_unused*/ )
@@ -9867,6 +10011,22 @@ test_cryptodev_dpaa_sec(void /*argv __rte_unused, int argc __rte_unused*/)return unit_test_suite_runner (&cryptodev_dpaa_sec_testsuite); } +static int +test_cryptodev_ccp (void ) +{ + gbl_driver_id =rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )); + +if (gbl_driver_id ==-1 ) { +RTE_LOG (ERR ,USER1 ,"CCP PMD must be loaded. Check if " +"CONFIG_RTE_LIBRTE_PMD_CCP is enabled " +"in config file to run this testsuite.\n" ); +return TEST_FAILED ; + } + +return unit_test_suite_runner (&cryptodev_ccp_testsuite); +} +REGISTER_TEST_COMMAND (cryptodev_qat_autotest, test_cryptodev_qat);REGISTER_TEST_COMMAND (cryptodev_aesni_mb_autotest, test_cryptodev_aesni_mb);REGISTER_TEST_COMMAND (cryptodev_openssl_autotest, test_cryptodev_openssl);
@@ -9879,3 +10039,4 @@ REGISTER_TEST_COMMAND(cryptodev_sw_armv8_autotest, test_cryptodev_armv8);REGISTER_TEST_COMMAND (cryptodev_sw_mrvl_autotest, test_cryptodev_mrvl);REGISTER_TEST_COMMAND (cryptodev_dpaa2_sec_autotest, test_cryptodev_dpaa2_sec);REGISTER_TEST_COMMAND (cryptodev_dpaa_sec_autotest, test_cryptodev_dpaa_sec); +REGISTER_TEST_COMMAND (cryptodev_ccp_autotest, test_cryptodev_ccp);
test/test/test_cryptodev.h +1 -0
@@ -61,6 +61,7 @@#define CRYPTODEV_NAME_DPAA2_SEC_PMD crypto_dpaa2_sec#define CRYPTODEV_NAME_SCHEDULER_PMD crypto_scheduler#define CRYPTODEV_NAME_MRVL_PMD crypto_mrvl +#define CRYPTODEV_NAME_CCP_PMD crypto_ccp/** * Write (spread) data from buffer to mbuf data
test/test/test_cryptodev_aes_test_vectors.h +62 -31
279 lines not on this page · raw message
test/test/test_cryptodev_blockcipher.c +8 -1
@@ -54,6 +54,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,int openssl_pmd =rte_cryptodev_driver_id_get (RTE_STR (CRYPTODEV_NAME_OPENSSL_PMD )); +int ccp_pmd =rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD ));int scheduler_pmd =rte_cryptodev_driver_id_get (RTE_STR (CRYPTODEV_NAME_SCHEDULER_PMD )); int armv8_pmd = rte_cryptodev_driver_id_get(
@@ -94,7 +96,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t, driver_id == qat_pmd || driver_id == openssl_pmd || driver_id == armv8_pmd || - driver_id == mrvl_pmd) { /* Fall through */ + driver_id == mrvl_pmd || + driver_id == ccp_pmd) { /* Fall through */ digest_len = tdata->digest.len; } else if (driver_id == aesni_mb_pmd || driver_id == scheduler_pmd) {
@@ -555,6 +558,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,int openssl_pmd =rte_cryptodev_driver_id_get (RTE_STR (CRYPTODEV_NAME_OPENSSL_PMD )); +int ccp_pmd =rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD ));int dpaa2_sec_pmd =rte_cryptodev_driver_id_get (RTE_STR (CRYPTODEV_NAME_DPAA2_SEC_PMD )); int dpaa_sec_pmd = rte_cryptodev_driver_id_get(
@@ -627,6 +632,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool, target_pmd_mask =BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER ; else if (driver_id == dpaa2_sec_pmd) target_pmd_mask =BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC ; + else if (driver_id == ccp_pmd) + target_pmd_mask =BLOCKCIPHER_TEST_TARGET_PMD_CCP ; else if (driver_id == dpaa_sec_pmd) target_pmd_mask =BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC ; else if (driver_id == mrvl_pmd)
test/test/test_cryptodev_blockcipher.h +1 -0
@@ -27,6 +27,7 @@#define BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC 0x0020/* DPAA2_SEC flag */ #define BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC 0x0040/* DPAA_SEC flag */ #define BLOCKCIPHER_TEST_TARGET_PMD_MRVL 0x0080/* Marvell flag */ +#define BLOCKCIPHER_TEST_TARGET_PMD_CCP 0x0040/* CCP flag */ #define BLOCKCIPHER_TEST_OP_CIPHER (BLOCKCIPHER_TEST_OP_ENCRYPT | \ BLOCKCIPHER_TEST_OP_DECRYPT)
test/test/test_cryptodev_des_test_vectors.h +28 -14
124 lines not on this page · raw message
test/test/test_cryptodev_hash_test_vectors.h +40 -20
172 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v4 19/20 doc: add document for AMD CCP crypto poll mode driver
In reply to Ravi Kumar--- doc/guides/cryptodevs/ccp.rst | 127 +++++++++++++++++++++++++++++ doc/guides/cryptodevs/features/ccp.ini | 57 +++++++++++++ doc/guides/cryptodevs/features/default.ini | 12 +++ doc/guides/cryptodevs/index.rst | 1 + 4 files changed, 197 insertions(+) create mode 100644 doc/guides/cryptodevs/ccp.rst create mode 100644 doc/guides/cryptodevs/features/ccp.ini
doc/guides/cryptodevs/ccp.rst new file +127 -0
@@ -0,0 +1,127 @@ +.. Copyright(c) 2017 Advanced Micro Devices, Inc. + All rights reserved. + + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions + are met: + + * Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + * Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + * Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +AMD CCP Poll Mode Driver +======================== + +This code provides the initial implementation of the ccp poll mode driver. +The CCP poll mode driver library (librte_pmd_ccp) implements support for +AMD’s cryptographic co-processor (CCP). The CCP PMD is a virtual crypto +poll mode driver which schedules crypto operations to one or more available +CCP hardware engines on the platform. The CCP PMD provides poll mode crypto +driver support for the following hardware accelerator devices:: + + AMD Cryptographic Co-processor (0x1456) + AMD Cryptographic Co-processor (0x1468) + +Features +-------- + +CCP crypto PMD has support for: + +Cipher algorithms: + +* ``RTE_CRYPTO_CIPHER_AES_CBC`` +* ``RTE_CRYPTO_CIPHER_AES_ECB`` +* ``RTE_CRYPTO_CIPHER_AES_CTR`` +* ``RTE_CRYPTO_CIPHER_3DES_CBC`` + +Hash algorithms: + +* ``RTE_CRYPTO_AUTH_SHA1`` +* ``RTE_CRYPTO_AUTH_SHA1_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA224`` +* ``RTE_CRYPTO_AUTH_SHA224_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA256`` +* ``RTE_CRYPTO_AUTH_SHA256_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA384`` +* ``RTE_CRYPTO_AUTH_SHA384_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA512`` +* ``RTE_CRYPTO_AUTH_SHA512_HMAC`` +* ``RTE_CRYPTO_AUTH_MD5_HMAC`` +* ``RTE_CRYPTO_AUTH_AES_CMAC`` +* ``RTE_CRYPTO_AUTH_SHA3_224`` +* ``RTE_CRYPTO_AUTH_SHA3_224_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA3_256`` +* ``RTE_CRYPTO_AUTH_SHA3_256_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA3_384`` +* ``RTE_CRYPTO_AUTH_SHA3_384_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA3_512`` +* ``RTE_CRYPTO_AUTH_SHA3_512_HMAC`` + +AEAD algorithms: + +* ``RTE_CRYPTO_AEAD_AES_GCM`` + +Installation +------------ + +To compile CCP PMD, it has to be enabled in the config/common_base file. +* ``CONFIG_RTE_LIBRTE_PMD_CCP=y`` + +The CCP PMD also supports computing authentication over CPU with cipher offloaded +to CCP. To enable this feature, enable following in the configuration. +* ``CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y`` + +This code was verified on Ubuntu 16.04. + +Initialization +-------------- + +Bind the CCP devices to DPDK UIO driver module before running the CCP PMD stack. +e.g. for the 0x1456 device:: + + cd to the top-level DPDK directory + modprobe uio + insmod ./build/kmod/igb_uio.ko + echo "1022 1456" > /sys/bus/pci/drivers/igb_uio/new_id + +Another way to bind the CCP devices to DPDK UIO driver is by using the ``dpdk-devbind.py`` script. +The following command assumes ``BFD`` of ``0000:09:00.2``:: + + cd to the top-level DPDK directory + ./usertools/dpdk-devbind.py -b igb_uio 0000:09:00.2 + +To verify real traffic l2fwd-crypto example can be used with following command: + +.. code-block:: console + + sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp" -- -p 0x1 + --chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo AES_CBC + --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f + --iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff + --auth_op GENERATE --auth_algo SHA1_HMAC + --auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + +Limitations +----------- + +* Chained mbufs are not supported +* MD5_HMAC is supported only if ``CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y`` is enabled in configuration
doc/guides/cryptodevs/features/ccp.ini new file +57 -0
57 lines not on this page · raw message
doc/guides/cryptodevs/features/default.ini +12 -0
@@ -28,6 +28,9 @@ NULL = AES CBC (128) = AES CBC (192) = AES CBC (256) = +AES ECB (128) = +AES ECB (192) = +AES ECB (256) = AES CTR (128) = AES CTR (192) = AES CTR (256) =
@@ -62,6 +65,15 @@ AES GMAC = SNOW3G UIA2 = KASUMI F9 = ZUC EIA3 = +AES CMAC = +SHA3_224 = +SHA3_224 HMAC = +SHA3_256 = +SHA3_256 HMAC = +SHA3_384 = +SHA3_384 HMAC = +SHA3_512 = +SHA3_512 HMAC = ; ; Supported AEAD algorithms of a default crypto driver.
doc/guides/cryptodevs/index.rst +1 -0
@@ -13,6 +13,7 @@ Crypto Device Drivers aesni_mb aesni_gcm armv8 + ccp dpaa2_sec dpaa_sec kasumi
Signature · 1 line
2.7.4
PATCH v4 20/20 crypto/ccp: moved license headers to SPDX format
In reply to Ravi Kumar--- doc/guides/cryptodevs/ccp.rst | 29 ++--------------------------- drivers/crypto/ccp/Makefile | 30 ++---------------------------- drivers/crypto/ccp/ccp_crypto.c | 29 ++--------------------------- drivers/crypto/ccp/ccp_crypto.h | 29 ++--------------------------- drivers/crypto/ccp/ccp_dev.c | 29 ++--------------------------- drivers/crypto/ccp/ccp_dev.h | 29 ++--------------------------- drivers/crypto/ccp/ccp_pci.c | 29 ++--------------------------- drivers/crypto/ccp/ccp_pci.h | 29 ++--------------------------- drivers/crypto/ccp/ccp_pmd_ops.c | 29 ++--------------------------- drivers/crypto/ccp/ccp_pmd_private.h | 29 ++--------------------------- drivers/crypto/ccp/rte_ccp_pmd.c | 29 ++--------------------------- 11 files changed, 22 insertions(+), 298 deletions(-)
doc/guides/cryptodevs/ccp.rst +2 -27
@@ -1,30 +1,5 @@ -.. Copyright(c) 2017 Advanced Micro Devices, Inc. - All rights reserved. - - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions - are met: - - * Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - * Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - * Neither the name of the copyright holder nor the names of its - contributors may be used to endorse or promote products derived from - this software without specific prior written permission. - - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +.. Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. + SPDX-License-Identifier: BSD-3-Clause AMD CCP Poll Mode Driver ========================
drivers/crypto/ccp/Makefile +2 -28
@@ -1,31 +1,5 @@ -# -# Copyright(c) 2018 Advanced Micro Devices, Inc. -# All rights reserved. -# -# Redistribution and use in source and binary forms, with or without -# modification, are permitted provided that the following conditions -# are met: -# -# * Redistributions of source code must retain the above copyright -# notice, this list of conditions and the following disclaimer. -# * Redistributions in binary form must reproduce the above copyright -# notice, this list of conditions and the following disclaimer in the -# documentation and/or other materials provided with the distribution. -# * Neither the name of the copyright holder nor the names of its -# contributors may be used to endorse or promote products derived from -# this software without specific prior written permission. -# -# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +# Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +# SPDX-License-Identifier: BSD-3-Clause include $(RTE_SDK)/mk/rte.vars.mk
drivers/crypto/ccp/ccp_crypto.c +2 -27
@@ -1,31 +1,6 @@/*- -* Copyright(c) 2018 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: BSD-3-Clause */ #include <dirent.h>
drivers/crypto/ccp/ccp_crypto.h +2 -27
@@ -1,31 +1,6 @@/*- -* Copyright(c) 2018 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: BSD-3-Clause */ #ifndef _CCP_CRYPTO_H_
drivers/crypto/ccp/ccp_dev.c +2 -27
@@ -1,31 +1,6 @@/*- -* Copyright(c) 2018 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: BSD-3-Clause */ #include <dirent.h>
drivers/crypto/ccp/ccp_dev.h +2 -27
@@ -1,31 +1,6 @@/*- -* Copyright(c) 2018 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: BSD-3-Clause */ #ifndef _CCP_DEV_H_
drivers/crypto/ccp/ccp_pci.c +2 -27
@@ -1,31 +1,6 @@/*- -* Copyright(c) 2018 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: BSD-3-Clause */ #include <dirent.h>
drivers/crypto/ccp/ccp_pci.h +2 -27
@@ -1,31 +1,6 @@/*- -* Copyright(c) 2018 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: BSD-3-Clause */ #ifndef _CCP_PCI_H_
drivers/crypto/ccp/ccp_pmd_ops.c +2 -27
@@ -1,31 +1,6 @@/*- -* Copyright(c) 2018 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: BSD-3-Clause */ #include <string.h>
drivers/crypto/ccp/ccp_pmd_private.h +2 -27
@@ -1,31 +1,6 @@/*- -* Copyright(c) 2018 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: BSD-3-Clause */ #ifndef _CCP_PMD_PRIVATE_H_
drivers/crypto/ccp/rte_ccp_pmd.c +2 -27
@@ -1,31 +1,6 @@/*- -* Copyright(c) 2018 Advanced Micro Devices, Inc. -* All rights reserved. -* -* Redistribution and use in source and binary forms, with or without -* modification, are permitted provided that the following conditions -* are met: -* -* * Redistributions of source code must retain the above copyright -* notice, this list of conditions and the following disclaimer. -* * Redistributions in binary form must reproduce the above copyright -* notice, this list of conditions and the following disclaimer in the -* documentation and/or other materials provided with the distribution. -* * Neither the name of the copyright holder nor the names of its -* contributors may be used to endorse or promote products derived from -* this software without specific prior written permission. -* -* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS -* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT -* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR -* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT -* HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, -* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT -* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, -* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY -* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +* SPDX-License-Identifier: BSD-3-Clause */ #include <rte_bus_pci.h>
Signature · 1 line
2.7.4
Re: [PATCH v4 20/20] crypto/ccp: moved license headers to SPDX format
Hi Ravi,
Quoted 7 lines
-----Original Message-----
From: Ravi Kumar [mailto:[email protected]]
Sent: Friday, March 9, 2018 8:35 AM
To: [email protected]
Cc: De Lara Guarch, Pablo <[email protected]>
Subject: [PATCH v4 20/20]crypto/ccp: moved license headers to SPDX format
As Ferruh suggested for "axgbe", could you use directly the SPDX license headers in the other patches and get rid of this one?
Thanks,
Pablo
Re: [PATCH v4 20/20] crypto/ccp: moved license headers to SPDX format
Quoted 18 lines
-----Original Message-----
From: De Lara Guarch, Pablo [mailto:[email protected]]
Sent: Monday, March 12, 2018 2:49 PM
To: Kumar, Ravi1 <[email protected]>; [email protected]
Subject: RE: [PATCH v4 20/20]crypto/ccp: moved license headers to SPDX formatHi Ravi,
Quoted 7 lines
-----Original Message-----
From: Ravi Kumar [mailto:[email protected]]
Sent: Friday, March 9, 2018 8:35 AM
To: [email protected]
Cc: De Lara Guarch, Pablo <[email protected]>
Subject: [PATCH v4 20/20]crypto/ccp: moved license headers to SPDX format
Quoted 5 lines
As Ferruh suggested for "axgbe", could you use directly the SPDX license headers in the other patches and get rid of this one?
Thanks,
Pablo
Hi Pablo,
Sure we will do that. Next version of the patches will take care of this.
Regards,
Ravi
Re: [PATCH v4 01/20] crypto/ccp: add AMD ccp skeleton PMD
In reply to Ravi KumarHi Ravi,
Since 18.02, DPDK community will prefer all new submission to use SPDX
licensing tags.
Regards,
Hemant
Quoted 2 lines · Ravi Kumar
Signed-off-by Ravi Kumar <[email protected]>---
<snip>..
Quoted 34 lines
drivers/crypto/ccp/Makefile new file +28
-0@@ -0,0 +1,55 @@ +# +# Copyright(c) 2018 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Re: [PATCH v4 01/20] crypto/ccp: add AMD ccp skeleton PMD
Please ignore my comment,
I just checked that you have added a patch to convert the license to SPDX.
However, it is not the best way. A new patchset should have this change in the individual patches itself.
Regards,
Hemant
Quoted 62 lines
-----Original Message-----
From: dev [mailto:[email protected]] On Behalf Of Hemant Agrawal
Sent: Friday, March 09, 2018 11:06 PM
To: Ravi Kumar <[email protected]>; [email protected]
Cc: [email protected]
Subject: Re: [dpdk-dev] [PATCH v4 01/20]crypto/ccp: add AMD ccp skeleton PMDHi Ravi,
Since 18.02, DPDK community will prefer all new submission to use SPDX
licensing tags.Regards,
HemantQuoted 2 lines · Ravi Kumar
Signed-off-by Ravi Kumar <[email protected]>---
<snip>..
Quoted 13 lines
drivers/crypto/ccp/Makefile new file +8
-0@@ -0,0 +1,55 @@ +# +# Copyright(c) 2018 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +#drivers/crypto/ccp/Makefile line 18
Quoted 10 lines
drivers/crypto/ccp/Makefile new file +10
-0+# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ANDCONTRIBUTORS
drivers/crypto/ccp/Makefile line 19
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUTNOT
drivers/crypto/ccp/Makefile line 20
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY ANDFITNESS FOR
drivers/crypto/ccp/Makefile line 21
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THECOPYRIGHT
drivers/crypto/ccp/Makefile line 22
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,INCIDENTAL,
drivers/crypto/ccp/Makefile line 23
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUTNOT
drivers/crypto/ccp/Makefile line 24
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSSOF USE,
drivers/crypto/ccp/Makefile line 25
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSEDAND ON ANY
drivers/crypto/ccp/Makefile line 26
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ORTORT
drivers/crypto/ccp/Makefile line 27
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OFTHE USE
drivers/crypto/ccp/Makefile line 28
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCHDAMAGE.
Re: [PATCH v4 01/20] crypto/ccp: add AMD ccp skeleton PMD
Quoted 9 lines
-----Original Message-----
From: Hemant Agrawal [mailto:[email protected]]
Sent: Friday, March 09, 2018 11:17 PM
To: Hemant Agrawal <[email protected]>; Kumar, Ravi1 <[email protected]>; [email protected]
Cc: [email protected]
Subject: RE: [dpdk-dev] [PATCH v4 01/20]crypto/ccp: add AMD ccp skeleton PMD
Quoted 8 lines
Please ignore my comment,
I just checked that you have added a patch to convert the license to SPDX.
However, it is not the best way. A new patchset should have this change in the individual patches itself.
Regards,
Hemant
Hi Hemant,
Thanks for reviewing. We will fix this in the next version of the patches.
Regards,
Ravi
Quoted 65 lines
Quoted 64 lines
-----Original Message-----
From: dev [mailto:[email protected]] On Behalf Of Hemant Agrawal
Sent: Friday, March 09, 2018 11:06 PM
To: Ravi Kumar <[email protected]>; [email protected]
Cc: [email protected]
Subject: Re: [dpdk-dev] [PATCH v4 01/20]crypto/ccp: add AMD ccp skeleton PMDHi Ravi,
Since 18.02, DPDK community will prefer all new submission to use
SPDX licensing tags.Regards,
HemantQuoted 2 lines · Ravi Kumar
Signed-off-by Ravi Kumar <[email protected]>---
<snip>..
Quoted 14 lines
(quoted diff) +0
-0b/drivers/crypto/ccp/Makefile new file mode 100644 index 0000000..51c5e5b
drivers/crypto/ccp/Makefile new file +8
-0@@ -0,0 +1,55 @@ +# +# Copyright(c) 2018 Advanced Micro Devices, Inc. +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +#drivers/crypto/ccp/Makefile line 18
Quoted 10 lines
drivers/crypto/ccp/Makefile new file +10
-0+# * Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# * Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution. +# * Neither the name of the copyright holder nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ANDCONTRIBUTORS
drivers/crypto/ccp/Makefile line 19
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUTNOT
drivers/crypto/ccp/Makefile line 20
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY ANDFITNESS FOR
drivers/crypto/ccp/Makefile line 21
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THECOPYRIGHT
drivers/crypto/ccp/Makefile line 22
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,INCIDENTAL,
drivers/crypto/ccp/Makefile line 23
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUTNOT
drivers/crypto/ccp/Makefile line 24
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSSOF USE,
drivers/crypto/ccp/Makefile line 25
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSEDAND ON ANY
drivers/crypto/ccp/Makefile line 26
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, ORTORT
drivers/crypto/ccp/Makefile line 27
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OFTHE USE
drivers/crypto/ccp/Makefile line 28
Quoted 1 line
drivers/crypto/ccp/Makefile new file +1
-0+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCHDAMAGE.
PATCH v5 1/19 crypto/ccp: add AMD ccp skeleton PMD
In reply to Ravi Kumar--- MAINTAINERS | 6 +++++ config/common_base | 5 +++++ doc/guides/rel_notes/release_18_05.rst | 5 +++++ drivers/crypto/Makefile | 1 + drivers/crypto/ccp/Makefile | 29 ++++++++++++++++++++++++ drivers/crypto/ccp/rte_ccp_pmd.c | 36 ++++++++++++++++++++++++++++++ drivers/crypto/ccp/rte_pmd_ccp_version.map | 4 ++++ mk/rte.app.mk | 2 ++ 8 files changed, 88 insertions(+) create mode 100644 drivers/crypto/ccp/Makefile create mode 100644 drivers/crypto/ccp/rte_ccp_pmd.c create mode 100644 drivers/crypto/ccp/rte_pmd_ccp_version.map
MAINTAINERS +6 -0
@@ -640,6 +640,12 @@ M: Pablo de Lara <[email protected]> T: git://dpdk.org/next/dpdk-next-crypto F: doc/guides/cryptodevs/features/default.ini +AMD CCP Crypto PMD +M: Ravi Kumar <[email protected]> +F: drivers/crypto/ccp/ +F: doc/guides/cryptodevs/ccp.rst +F: doc/guides/cryptodevs/features/ccp.ini + ARMv8 Crypto M: Jerin Jacob <[email protected]> F: drivers/crypto/armv8/
config/common_base +5 -0
@@ -529,6 +529,11 @@ CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y # +# Compile PMD for AMD CCP crypto device +# +CONFIG_RTE_LIBRTE_PMD_CCP=n + +# # Compile PMD for Marvell Crypto device # CONFIG_RTE_LIBRTE_PMD_MRVL_CRYPTO=n
doc/guides/rel_notes/release_18_05.rst +5 -0
@@ -41,6 +41,11 @@ New Features Also, make sure to start the actual text at the margin. ========================================================= +* **Added a new crypto poll mode driver for AMD CCP devices.** + + Added the new ``ccp`` crypto driver for AMD CCP devices. See the + :doc:`../cryptodevs/ccp` crypto driver guide for more details on + this new driver. API Changes -----------
drivers/crypto/Makefile +1 -0
@@ -20,5 +20,6 @@ endif ifeq ($(CONFIG_RTE_LIBRTE_DPAA_BUS),y) DIRS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_SEC) += dpaa_sec endif +DIRS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp include $(RTE_SDK)/mk/rte.subdir.mk
drivers/crypto/ccp/Makefile new file +29 -0
@@ -0,0 +1,29 @@ +# SPDX-License-Identifier: BSD-3-Clause +# Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. + +include $(RTE_SDK)/mk/rte.vars.mk + +# library name +LIB = librte_pmd_ccp.a + +# build flags +CFLAGS += -O3 +CFLAGS += -I$(SRCDIR) +CFLAGS += $(WERROR_FLAGS) + +# library version +LIBABIVER := 1 + +# external library include paths +LDLIBS += -lcrypto +LDLIBS += -lrte_eal -lrte_mbuf -lrte_mempool -lrte_ring +LDLIBS += -lrte_cryptodev +LDLIBS += -lrte_pci -lrte_bus_pci + +# versioning export map +EXPORT_MAP := rte_pmd_ccp_version.map + +# library source files +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += rte_ccp_pmd.c + +include $(RTE_SDK)/mk/rte.lib.mk
drivers/crypto/ccp/rte_ccp_pmd.c new file +36 -0
@@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: BSD-3-Clause +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +*/ + +#include <rte_bus_vdev.h> +#include <rte_cryptodev.h> +#include <rte_cryptodev_pmd.h> + +uint8_t ccp_cryptodev_driver_id; + +/** Remove ccp pmd */ +static int +cryptodev_ccp_remove(struct rte_vdev_device *dev __rte_unused) +{ +return 0 ; +} + +/** Probe ccp pmd */ +static int +cryptodev_ccp_probe(struct rte_vdev_device *vdev __rte_unused) +{ +return 0 ; +} + +static struct rte_vdev_driver cryptodev_ccp_pmd_drv = { + .probe = cryptodev_ccp_probe, + .remove = cryptodev_ccp_remove +}; + +static struct cryptodev_driver ccp_crypto_drv; + +RTE_PMD_REGISTER_VDEV (CRYPTODEV_NAME_CCP_PMD , cryptodev_ccp_pmd_drv); +RTE_PMD_REGISTER_PARAM_STRING (CRYPTODEV_NAME_CCP_PMD , +"max_nb_queue_pairs=<int> max_nb_sessions=<int> socket_id=<int>" ); +RTE_PMD_REGISTER_CRYPTO_DRIVER (ccp_crypto_drv, cryptodev_ccp_pmd_drv, + ccp_cryptodev_driver_id);
drivers/crypto/ccp/rte_pmd_ccp_version.map new file +4 -0
@@ -0,0 +1,4 @@ +DPDK_18.05 { + + local: *; +};
mk/rte.app.mk +2 -0
@@ -221,6 +221,8 @@ ifeq ($(CONFIG_RTE_LIBRTE_DPAA_BUS),y) _LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_DPAA_SEC) += -lrte_pmd_dpaa_sec endif # CONFIG_RTE_LIBRTE_DPAA_BUS +_LDLIBS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += -lrte_pmd_ccp -lcrypto + endif # CONFIG_RTE_LIBRTE_CRYPTODEV ifeq ($(CONFIG_RTE_LIBRTE_EVENTDEV),y)
Signature · 1 line
2.7.4
PATCH v5 2/19 crypto/ccp: support ccp device initialization and deintialization
--- drivers/crypto/ccp/Makefile | 3 + drivers/crypto/ccp/ccp_dev.c | 761 +++++++++++++++++++++++++++++++++++ drivers/crypto/ccp/ccp_dev.h | 284 +++++++++++++ drivers/crypto/ccp/ccp_pci.c | 236 +++++++++++ drivers/crypto/ccp/ccp_pci.h | 27 ++ drivers/crypto/ccp/ccp_pmd_ops.c | 29 ++ drivers/crypto/ccp/ccp_pmd_private.h | 56 +++ drivers/crypto/ccp/rte_ccp_pmd.c | 151 ++++++- 8 files changed, 1545 insertions(+), 2 deletions(-) create mode 100644 drivers/crypto/ccp/ccp_dev.c create mode 100644 drivers/crypto/ccp/ccp_dev.h create mode 100644 drivers/crypto/ccp/ccp_pci.c create mode 100644 drivers/crypto/ccp/ccp_pci.h create mode 100644 drivers/crypto/ccp/ccp_pmd_ops.c create mode 100644 drivers/crypto/ccp/ccp_pmd_private.h
drivers/crypto/ccp/Makefile +3 -0
@@ -25,5 +25,8 @@ EXPORT_MAP := rte_pmd_ccp_version.map # library source files SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += rte_ccp_pmd.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_pmd_ops.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_dev.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_pci.c include $(RTE_SDK)/mk/rte.lib.mk
drivers/crypto/ccp/ccp_dev.c new file +761 -0
761 lines not on this page · raw message
drivers/crypto/ccp/ccp_dev.h new file +284 -0
284 lines not on this page · raw message
drivers/crypto/ccp/ccp_pci.c new file +236 -0
236 lines not on this page · raw message
drivers/crypto/ccp/ccp_pci.h new file +27 -0
@@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: BSD-3-Clause +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +*/ + +#ifndef _CCP_PCI_H_ +#define _CCP_PCI_H_ + +#include <stdint.h> + +#include <rte_bus_pci.h> + +#define SYSFS_PCI_DEVICES "/sys/bus/pci/devices" +#define PROC_MODULES "/proc/modules" + +int ccp_check_pci_uio_module (void ); + +int ccp_parse_pci_addr_format (const char *buf,int bufsize,uint16_t *domain, +uint8_t *bus,uint8_t *devid,uint8_t *function); + +int ccp_pci_parse_sysfs_value (const char *filename,unsigned long *val); + +int ccp_pci_parse_sysfs_resource (const char *filename, +struct rte_pci_device *dev); + +int ccp_find_uio_devname (const char *dirname); + +#endif /* _CCP_PCI_H_ */
drivers/crypto/ccp/ccp_pmd_ops.c new file +29 -0
@@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: BSD-3-Clause +* Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. +*/ + +#include <rte_cryptodev_pmd.h> + +struct rte_cryptodev_ops ccp_ops = { + .dev_configure =NULL , + .dev_start =NULL , + .dev_stop =NULL , + .dev_close =NULL , + + .stats_get =NULL , + .stats_reset =NULL , + + .dev_infos_get =NULL , + + .queue_pair_setup =NULL , + .queue_pair_release =NULL , + .queue_pair_start =NULL , + .queue_pair_stop =NULL , + .queue_pair_count =NULL , + + .session_get_size =NULL , + .session_configure =NULL , + .session_clear =NULL , +}; + +struct rte_cryptodev_ops *ccp_pmd_ops = &ccp_ops;
drivers/crypto/ccp/ccp_pmd_private.h new file +56 -0
56 lines not on this page · raw message
drivers/crypto/ccp/rte_ccp_pmd.c +149 -2
172 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v5 3/19 crypto/ccp: support basic pmd ops
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_dev.c | 9 ++++++ drivers/crypto/ccp/ccp_dev.h | 9 ++++++ drivers/crypto/ccp/ccp_pmd_ops.c | 61 +++++++++++++++++++++++++++++++++--- drivers/crypto/ccp/ccp_pmd_private.h | 43 +++++++++++++++++++++++++ 4 files changed, 117 insertions(+), 5 deletions(-)
drivers/crypto/ccp/ccp_dev.c +9 -0
@@ -26,6 +26,15 @@struct ccp_list ccp_list =TAILQ_HEAD_INITIALIZER (ccp_list);static int ccp_dev_id; +int +ccp_dev_start (struct rte_cryptodev *dev) +{ +struct ccp_private *priv = dev->data->dev_private; + + priv->last_dev =TAILQ_FIRST (&ccp_list); +return 0 ; +} +static const struct rte_memzone * ccp_queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
drivers/crypto/ccp/ccp_dev.h +9 -0
@@ -78,6 +78,10 @@#define LSB_ITEM_SIZE 32#define SLSB_MAP_SIZE (MAX_LSB_CNT * LSB_SIZE) +/* General CCP Defines */ + +#define CCP_SB_BYTES 32 +/* bitmap */ enum {BITS_PER_WORD =sizeof (unsigned long ) *CHAR_BIT
@@ -273,6 +277,11 @@ high32_value(unsigned long addr)return ((uint64_t )addr >>32 ) &0x00000ffff ; } +/* +* Start CCP device +*/ +int ccp_dev_start (struct rte_cryptodev *dev); +/** * Detect ccp platform and initialize all ccp devices *
drivers/crypto/ccp/ccp_pmd_ops.c +56 -5
74 lines not on this page · raw message
drivers/crypto/ccp/ccp_pmd_private.h +43 -0
56 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v5 4/19 crypto/ccp: support session related crypto pmd ops
In reply to Ravi Kumar--- drivers/crypto/ccp/Makefile | 3 +- drivers/crypto/ccp/ccp_crypto.c | 203 +++++++++++++++++++++++++++++++++ drivers/crypto/ccp/ccp_crypto.h | 241 +++++++++++++++++++++++++++++++++++++++ drivers/crypto/ccp/ccp_dev.h | 129 +++++++++++++++++++++ drivers/crypto/ccp/ccp_pmd_ops.c | 61 +++++++++- 5 files changed, 633 insertions(+), 4 deletions(-) create mode 100644 drivers/crypto/ccp/ccp_crypto.c create mode 100644 drivers/crypto/ccp/ccp_crypto.h
drivers/crypto/ccp/Makefile +2 -1
@@ -25,8 +25,9 @@ EXPORT_MAP := rte_pmd_ccp_version.map # library source files SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += rte_ccp_pmd.c -SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_pmd_ops.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_crypto.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_dev.c SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_pci.c +SRCS-$(CONFIG_RTE_LIBRTE_PMD_CCP) += ccp_pmd_ops.c include $(RTE_SDK)/mk/rte.lib.mk
drivers/crypto/ccp/ccp_crypto.c new file +203 -0
203 lines not on this page · raw message
drivers/crypto/ccp/ccp_crypto.h new file +241 -0
241 lines not on this page · raw message
drivers/crypto/ccp/ccp_dev.h +129 -0
141 lines not on this page · raw message
drivers/crypto/ccp/ccp_pmd_ops.c +58 -3
79 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v5 5/19 crypto/ccp: support queue pair related pmd ops
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_pmd_ops.c | 149 +++++++++++++++++++++++++++++++++++++-- 1 file changed, 144 insertions(+), 5 deletions(-)
drivers/crypto/ccp/ccp_pmd_ops.c +144 -5
@@ -56,6 +56,145 @@ ccp_pmd_info_get(struct rte_cryptodev *dev, } } +static int +ccp_pmd_qp_release (struct rte_cryptodev *dev,uint16_t qp_id) +{ +struct ccp_qp *qp; + +if (dev->data->queue_pairs[qp_id] !=NULL ) { + qp = (struct ccp_qp *)dev->data->queue_pairs[qp_id]; +rte_ring_free (qp->processed_pkts); +rte_mempool_free (qp->batch_mp); +rte_free (qp); + dev->data->queue_pairs[qp_id] =NULL ; + } +return 0 ; +} + +static int +ccp_pmd_qp_set_unique_name (struct rte_cryptodev *dev, +struct ccp_qp *qp) +{ +unsigned int n =snprintf (qp->name,sizeof (qp->name), +"ccp_pmd_%u_qp_%u" , + dev->data->dev_id, qp->id); + +if (n >sizeof (qp->name)) +return -1 ; + +return 0 ; +} + +static struct rte_ring * +ccp_pmd_qp_create_batch_info_ring (struct ccp_qp *qp, +unsigned int ring_size,int socket_id) +{ +struct rte_ring *r; + + r =rte_ring_lookup (qp->name); +if (r) { +if (r->size >= ring_size) { +CCP_LOG_INFO ( +"Reusing ring %s for processed packets" , + qp->name); +return r; + } +CCP_LOG_INFO ( +"Unable to reuse ring %s for processed packets" , + qp->name); +return NULL ; + } + +return rte_ring_create (qp->name, ring_size, socket_id, +RING_F_SP_ENQ |RING_F_SC_DEQ ); +} + +static int +ccp_pmd_qp_setup (struct rte_cryptodev *dev,uint16_t qp_id, +const struct rte_cryptodev_qp_conf *qp_conf, +int socket_id,struct rte_mempool *session_pool) +{ +struct ccp_private *internals = dev->data->dev_private; +struct ccp_qp *qp; +int retval =0 ; + +if (qp_id >= internals->max_nb_qpairs) { +CCP_LOG_ERR ("Invalid qp_id %u, should be less than %u" , + qp_id, internals->max_nb_qpairs); +return (-EINVAL ); + } + +/* Free memory prior to re-allocation if needed. */ +if (dev->data->queue_pairs[qp_id] !=NULL ) +ccp_pmd_qp_release (dev, qp_id); + +/* Allocate the queue pair data structure. */ + qp =rte_zmalloc_socket ("CCP Crypto PMD Queue Pair" ,sizeof (*qp), +RTE_CACHE_LINE_SIZE , socket_id); +if (qp ==NULL ) { +CCP_LOG_ERR ("Failed to allocate queue pair memory" ); +return (-ENOMEM ); + } + + qp->dev = dev; + qp->id = qp_id; + dev->data->queue_pairs[qp_id] = qp; + + retval =ccp_pmd_qp_set_unique_name (dev, qp); +if (retval) { +CCP_LOG_ERR ("Failed to create unique name for ccp qp" ); + goto qp_setup_cleanup; + } + + qp->processed_pkts =ccp_pmd_qp_create_batch_info_ring (qp, + qp_conf->nb_descriptors, socket_id); +if (qp->processed_pkts ==NULL ) { +CCP_LOG_ERR ("Failed to create batch info ring" ); + goto qp_setup_cleanup; + } + + qp->sess_mp = session_pool; + +/* mempool for batch info */ + qp->batch_mp =rte_mempool_create ( + qp->name, + qp_conf->nb_descriptors, +sizeof (struct ccp_batch_info ), +RTE_CACHE_LINE_SIZE , +0 ,NULL ,NULL ,NULL ,NULL , +SOCKET_ID_ANY ,0 ); +if (qp->batch_mp ==NULL ) + goto qp_setup_cleanup; +memset (&qp->qp_stats,0 ,sizeof (qp->qp_stats)); +return 0 ; + +qp_setup_cleanup: + dev->data->queue_pairs[qp_id] =NULL ; +if (qp) +rte_free (qp); +return -1 ; +} + +static int +ccp_pmd_qp_start(struct rte_cryptodev *dev __rte_unused, + uint16_t queue_pair_id __rte_unused) +{ +return -ENOTSUP ; +} + +static int +ccp_pmd_qp_stop(struct rte_cryptodev *dev __rte_unused, + uint16_t queue_pair_id __rte_unused) +{ +return -ENOTSUP ; +} + +static uint32_t +ccp_pmd_qp_count (struct rte_cryptodev *dev) +{ +return dev->data->nb_queue_pairs; +} +static unsigned ccp_pmd_session_get_size(struct rte_cryptodev *dev __rte_unused) {
@@ -121,11 +260,11 @@ struct rte_cryptodev_ops ccp_ops = { .dev_infos_get = ccp_pmd_info_get, - .queue_pair_setup = NULL, - .queue_pair_release = NULL, - .queue_pair_start = NULL, - .queue_pair_stop = NULL, - .queue_pair_count = NULL, + .queue_pair_setup = ccp_pmd_qp_setup, + .queue_pair_release = ccp_pmd_qp_release, + .queue_pair_start = ccp_pmd_qp_start, + .queue_pair_stop = ccp_pmd_qp_stop, + .queue_pair_count = ccp_pmd_qp_count, .session_get_size = ccp_pmd_session_get_size, .session_configure = ccp_pmd_session_configure,
Signature · 1 line
2.7.4
PATCH v5 6/19 crypto/ccp: support crypto enqueue and dequeue burst api
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 360 +++++++++++++++++++++++++++++++++++++++ drivers/crypto/ccp/ccp_crypto.h | 35 ++++ drivers/crypto/ccp/ccp_dev.c | 27 +++ drivers/crypto/ccp/ccp_dev.h | 9 + drivers/crypto/ccp/rte_ccp_pmd.c | 64 ++++++- 5 files changed, 488 insertions(+), 7 deletions(-)
drivers/crypto/ccp/ccp_crypto.c +360 -0
@@ -201,3 +201,363 @@ ccp_set_session_parameters(struct ccp_session *sess, }return ret; } + +/* calculate CCP descriptors requirement */ +static inline int +ccp_cipher_slot (struct ccp_session *session) +{ +int count =0 ; + +switch (session->cipher.algo) { +default : +CCP_LOG_ERR ("Unsupported cipher algo %d" , + session->cipher.algo); + } +return count; +} + +static inline int +ccp_auth_slot (struct ccp_session *session) +{ +int count =0 ; + +switch (session->auth.algo) { +default : +CCP_LOG_ERR ("Unsupported auth algo %d" , + session->auth.algo); + } + +return count; +} + +static int +ccp_aead_slot (struct ccp_session *session) +{ +int count =0 ; + +switch (session->aead_algo) { +default : +CCP_LOG_ERR ("Unsupported aead algo %d" , + session->aead_algo); + } +return count; +} + +int +ccp_compute_slot_count (struct ccp_session *session) +{ +int count =0 ; + +switch (session->cmd_id) { +case CCP_CMD_CIPHER : + count =ccp_cipher_slot (session); +break ; +case CCP_CMD_AUTH : + count =ccp_auth_slot (session); +break ; +case CCP_CMD_CIPHER_HASH : +case CCP_CMD_HASH_CIPHER : + count =ccp_cipher_slot (session); + count +=ccp_auth_slot (session); +break ; +case CCP_CMD_COMBINED : + count =ccp_aead_slot (session); +break ; +default : +CCP_LOG_ERR ("Unsupported cmd_id" ); + + } + +return count; +} + +static inline int +ccp_crypto_cipher (struct rte_crypto_op *op, + struct ccp_queue *cmd_q __rte_unused, + struct ccp_batch_info *b_info __rte_unused) +{ +int result =0 ; +struct ccp_session *session; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + +switch (session->cipher.algo) { +default : +CCP_LOG_ERR ("Unsupported cipher algo %d" , + session->cipher.algo); +return -ENOTSUP ; + } +return result; +} + +static inline int +ccp_crypto_auth (struct rte_crypto_op *op, + struct ccp_queue *cmd_q __rte_unused, + struct ccp_batch_info *b_info __rte_unused) +{ + +int result =0 ; +struct ccp_session *session; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + +switch (session->auth.algo) { +default : +CCP_LOG_ERR ("Unsupported auth algo %d" , + session->auth.algo); +return -ENOTSUP ; + } + +return result; +} + +static inline int +ccp_crypto_aead (struct rte_crypto_op *op, + struct ccp_queue *cmd_q __rte_unused, + struct ccp_batch_info *b_info __rte_unused) +{ +int result =0 ; +struct ccp_session *session; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + +switch (session->aead_algo) { +default : +CCP_LOG_ERR ("Unsupported aead algo %d" , + session->aead_algo); +return -ENOTSUP ; + } +return result; +} + +int +process_ops_to_enqueue (const struct ccp_qp *qp, +struct rte_crypto_op **op, +struct ccp_queue *cmd_q, +uint16_t nb_ops, +int slots_req) +{ +int i, result =0 ; +struct ccp_batch_info *b_info; +struct ccp_session *session; + +if (rte_mempool_get (qp->batch_mp, (void **)&b_info)) { +CCP_LOG_ERR ("batch info allocation failed" ); +return 0 ; + } +/* populate batch info necessary for dequeue */ + b_info->op_idx =0 ; + b_info->lsb_buf_idx =0 ; + b_info->desccnt =0 ; + b_info->cmd_q = cmd_q; + b_info->lsb_buf_phys = + (phys_addr_t )rte_mem_virt2phy ((void *)b_info->lsb_buf); +rte_atomic64_sub (&b_info->cmd_q->free_slots, slots_req); + + b_info->head_offset = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx * +Q_DESC_SIZE ); +for (i =0 ; i < nb_ops; i++) { + session = (struct ccp_session *)get_session_private_data ( + op[i]->sym->session, + ccp_cryptodev_driver_id); +switch (session->cmd_id) { +case CCP_CMD_CIPHER : + result =ccp_crypto_cipher (op[i], cmd_q, b_info); +break ; +case CCP_CMD_AUTH : + result =ccp_crypto_auth (op[i], cmd_q, b_info); +break ; +case CCP_CMD_CIPHER_HASH : + result =ccp_crypto_cipher (op[i], cmd_q, b_info); +if (result) +break ; + result =ccp_crypto_auth (op[i], cmd_q, b_info); +break ; +case CCP_CMD_HASH_CIPHER : + result =ccp_crypto_auth (op[i], cmd_q, b_info); +if (result) +break ; + result =ccp_crypto_cipher (op[i], cmd_q, b_info); +break ; +case CCP_CMD_COMBINED : + result =ccp_crypto_aead (op[i], cmd_q, b_info); +break ; +default : +CCP_LOG_ERR ("Unsupported cmd_id" ); + result =-1 ; + } +if (unlikely (result <0 )) { +rte_atomic64_add (&b_info->cmd_q->free_slots, + (slots_req - b_info->desccnt)); +break ; + } + b_info->op[i] = op[i]; + } + + b_info->opcnt = i; + b_info->tail_offset = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx * +Q_DESC_SIZE ); + +rte_wmb (); +/* Write the new tail address back to the queue register */ +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , + b_info->tail_offset); +/* Turn the queue back on using our cached control register */ +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +rte_ring_enqueue (qp->processed_pkts, (void *)b_info); + +return i; +} + +static inline void ccp_auth_dq_prepare (struct rte_crypto_op *op) +{ +struct ccp_session *session; +uint8_t *digest_data, *addr; +struct rte_mbuf *m_last; +int offset, digest_offset; +uint8_t digest_le[64 ]; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + +if (session->cmd_id ==CCP_CMD_COMBINED ) { + digest_data = op->sym->aead.digest.data; + digest_offset = op->sym->aead.data.offset + + op->sym->aead.data.length; + }else { + digest_data = op->sym->auth.digest.data; + digest_offset = op->sym->auth.data.offset + + op->sym->auth.data.length; + } + m_last =rte_pktmbuf_lastseg (op->sym->m_src); + addr = (uint8_t *)((char *)m_last->buf_addr + m_last->data_off + + m_last->data_len - session->auth.ctx_len); + +rte_mb (); + offset = session->auth.offset; + +if (session->auth.engine ==CCP_ENGINE_SHA ) +if ((session->auth.ut.sha_type !=CCP_SHA_TYPE_1 ) && + (session->auth.ut.sha_type !=CCP_SHA_TYPE_224 ) && + (session->auth.ut.sha_type !=CCP_SHA_TYPE_256 )) { +/* All other algorithms require byte +* swap done by host +*/ +unsigned int i; + + offset = session->auth.ctx_len - + session->auth.offset -1 ; +for (i =0 ; i < session->auth.digest_length; i++) + digest_le[i] = addr[offset - i]; + offset =0 ; + addr = digest_le; + } + + op->status =RTE_CRYPTO_OP_STATUS_SUCCESS ; +if (session->auth.op ==CCP_AUTH_OP_VERIFY ) { +if (memcmp (addr + offset, digest_data, + session->auth.digest_length) !=0 ) + op->status =RTE_CRYPTO_OP_STATUS_AUTH_FAILED ; + + }else { +if (unlikely (digest_data ==0 )) + digest_data =rte_pktmbuf_mtod_offset ( + op->sym->m_dst, uint8_t *, + digest_offset); +rte_memcpy (digest_data, addr + offset, + session->auth.digest_length); + } +/* Trim area used for digest from mbuf. */ +rte_pktmbuf_trim (op->sym->m_src, + session->auth.ctx_len); +} + +static int +ccp_prepare_ops (struct rte_crypto_op **op_d, +struct ccp_batch_info *b_info, +uint16_t nb_ops) +{ +int i, min_ops; +struct ccp_session *session; + + min_ops =RTE_MIN (nb_ops, b_info->opcnt); + +for (i =0 ; i < min_ops; i++) { + op_d[i] = b_info->op[b_info->op_idx++]; + session = (struct ccp_session *)get_session_private_data ( + op_d[i]->sym->session, + ccp_cryptodev_driver_id); +switch (session->cmd_id) { +case CCP_CMD_CIPHER : + op_d[i]->status =RTE_CRYPTO_OP_STATUS_SUCCESS ; +break ; +case CCP_CMD_AUTH : +case CCP_CMD_CIPHER_HASH : +case CCP_CMD_HASH_CIPHER : +case CCP_CMD_COMBINED : +ccp_auth_dq_prepare (op_d[i]); +break ; +default : +CCP_LOG_ERR ("Unsupported cmd_id" ); + } + } + + b_info->opcnt -= min_ops; +return min_ops; +} + +int +process_ops_to_dequeue (struct ccp_qp *qp, +struct rte_crypto_op **op, +uint16_t nb_ops) +{ +struct ccp_batch_info *b_info; +uint32_t cur_head_offset; + +if (qp->b_info !=NULL ) { + b_info = qp->b_info; +if (unlikely (b_info->op_idx >0 )) + goto success; + }else if (rte_ring_dequeue (qp->processed_pkts, + (void **)&b_info)) +return 0 ; + cur_head_offset =CCP_READ_REG (b_info->cmd_q->reg_base, +CMD_Q_HEAD_LO_BASE ); + +if (b_info->head_offset < b_info->tail_offset) { +if ((cur_head_offset >= b_info->head_offset) && + (cur_head_offset < b_info->tail_offset)) { + qp->b_info = b_info; +return 0 ; + } + }else { +if ((cur_head_offset >= b_info->head_offset) || + (cur_head_offset < b_info->tail_offset)) { + qp->b_info = b_info; +return 0 ; + } + } + + +success: + nb_ops =ccp_prepare_ops (op, b_info, nb_ops); +rte_atomic64_add (&b_info->cmd_q->free_slots, b_info->desccnt); + b_info->desccnt =0 ; +if (b_info->opcnt >0 ) { + qp->b_info = b_info; + }else { +rte_mempool_put (qp->batch_mp, (void *)b_info); + qp->b_info =NULL ; + } + +return nb_ops; +}
drivers/crypto/ccp/ccp_crypto.h +35 -0
@@ -238,4 +238,39 @@ struct ccp_qp;int ccp_set_session_parameters (struct ccp_session *sess,const struct rte_crypto_sym_xform *xform); +/** +* Find count of slots +* +* @param session CCP private session +* @return count of free slots available +*/ +int ccp_compute_slot_count (struct ccp_session *session); + +/** +* process crypto ops to be enqueued +* +* @param qp CCP crypto queue-pair +* @param op crypto ops table +* @param cmd_q CCP cmd queue +* @param nb_ops No. of ops to be submitted +* @return 0 on success otherwise -1 +*/ +int process_ops_to_enqueue (const struct ccp_qp *qp, +struct rte_crypto_op **op, +struct ccp_queue *cmd_q, +uint16_t nb_ops, +int slots_req); + +/** +* process crypto ops to be dequeued +* +* @param qp CCP crypto queue-pair +* @param op crypto ops table +* @param nb_ops requested no. of ops +* @return 0 on success otherwise -1 +*/ +int process_ops_to_dequeue (struct ccp_qp *qp, +struct rte_crypto_op **op, +uint16_t nb_ops); +#endif /* _CCP_CRYPTO_H_ */
drivers/crypto/ccp/ccp_dev.c +27 -0
@@ -35,6 +35,33 @@ ccp_dev_start(struct rte_cryptodev *dev)return 0 ; } +struct ccp_queue * +ccp_allot_queue (struct rte_cryptodev *cdev,int slot_req) +{ +int i, ret =0 ; +struct ccp_device *dev; +struct ccp_private *priv = cdev->data->dev_private; + + dev =TAILQ_NEXT (priv->last_dev, next); +if (unlikely (dev ==NULL )) + dev =TAILQ_FIRST (&ccp_list); + priv->last_dev = dev; +if (dev->qidx >= dev->cmd_q_count) + dev->qidx =0 ; + ret =rte_atomic64_read (&dev->cmd_q[dev->qidx].free_slots); +if (ret >= slot_req) +return &dev->cmd_q[dev->qidx]; +for (i =0 ; i < dev->cmd_q_count; i++) { + dev->qidx++; +if (dev->qidx >= dev->cmd_q_count) + dev->qidx =0 ; + ret =rte_atomic64_read (&dev->cmd_q[dev->qidx].free_slots); +if (ret >= slot_req) +return &dev->cmd_q[dev->qidx]; + } +return NULL ; +} +static const struct rte_memzone * ccp_queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
drivers/crypto/ccp/ccp_dev.h +9 -0
@@ -419,4 +419,13 @@ int ccp_dev_start(struct rte_cryptodev *dev);*/ int ccp_probe_devices (const struct rte_pci_id *ccp_id); +/** +* allocate a ccp command queue +* +* @dev rte crypto device +* @param slot_req number of required +* @return allotted CCP queue on success otherwise NULL +*/ +struct ccp_queue *ccp_allot_queue (struct rte_cryptodev *dev,int slot_req); +#endif /* _CCP_DEV_H_ */
drivers/crypto/ccp/rte_ccp_pmd.c +57 -7
86 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v5 7/19 crypto/ccp: support sessionless operations
In reply to Ravi Kumar--- drivers/crypto/ccp/rte_ccp_pmd.c | 33 +++++++++++++++++++++++++++++++-- 1 file changed, 31 insertions(+), 2 deletions(-)
drivers/crypto/ccp/rte_ccp_pmd.c +31 -2
@@ -23,7 +23,7 @@ static unsigned int ccp_pmd_init_done;uint8_t ccp_cryptodev_driver_id;static struct ccp_session * -get_ccp_session(struct ccp_qp *qp __rte_unused, struct rte_crypto_op *op) +get_ccp_session (struct ccp_qp *qp,struct rte_crypto_op *op) {struct ccp_session *sess =NULL ;
@@ -35,6 +35,27 @@ get_ccp_session(struct ccp_qp *qp __rte_unused, struct rte_crypto_op *op)get_session_private_data ( op->sym->session, ccp_cryptodev_driver_id); + }else if (op->sess_type ==RTE_CRYPTO_OP_SESSIONLESS ) { +void *_sess; +void *_sess_private_data =NULL ; + +if (rte_mempool_get (qp->sess_mp, &_sess)) +return NULL ; +if (rte_mempool_get (qp->sess_mp, (void **)&_sess_private_data)) +return NULL ; + + sess = (struct ccp_session *)_sess_private_data; + +if (unlikely (ccp_set_session_parameters (sess, + op->sym->xform) !=0 )) { +rte_mempool_put (qp->sess_mp, _sess); +rte_mempool_put (qp->sess_mp, _sess_private_data); + sess =NULL ; + } + op->sym->session = (struct rte_cryptodev_sym_session *)_sess; +set_session_private_data (op->sym->session, + ccp_cryptodev_driver_id, + _sess_private_data); }return sess;
@@ -82,10 +103,18 @@ ccp_pmd_dequeue_burst(void *queue_pair, struct rte_crypto_op **ops, uint16_t nb_ops) {struct ccp_qp *qp = queue_pair; -uint16_t nb_dequeued =0 ; +uint16_t nb_dequeued =0 , i; nb_dequeued =process_ops_to_dequeue (qp, ops, nb_ops); +/* Free session if a session-less crypto op */ +for (i =0 ; i < nb_dequeued; i++) +if (unlikely (ops[i]->sess_type == +RTE_CRYPTO_OP_SESSIONLESS )) { +rte_mempool_put (qp->sess_mp, + ops[i]->sym->session); + ops[i]->sym->session =NULL ; + } qp->qp_stats.dequeued_count += nb_dequeued;return nb_dequeued;
Signature · 1 line
2.7.4
PATCH v5 8/19 crypto/ccp: support stats related crypto pmd ops
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_pmd_ops.c | 34 ++++++++++++++++++++++++++++++++-- 1 file changed, 32 insertions(+), 2 deletions(-)
drivers/crypto/ccp/ccp_pmd_ops.c +32 -2
@@ -42,6 +42,36 @@ ccp_pmd_close(struct rte_cryptodev *dev __rte_unused) }static void +ccp_pmd_stats_get (struct rte_cryptodev *dev, +struct rte_cryptodev_stats *stats) +{ +int qp_id; + +for (qp_id =0 ; qp_id < dev->data->nb_queue_pairs; qp_id++) { +struct ccp_qp *qp = dev->data->queue_pairs[qp_id]; + + stats->enqueued_count += qp->qp_stats.enqueued_count; + stats->dequeued_count += qp->qp_stats.dequeued_count; + + stats->enqueue_err_count += qp->qp_stats.enqueue_err_count; + stats->dequeue_err_count += qp->qp_stats.dequeue_err_count; + } + +} + +static void +ccp_pmd_stats_reset (struct rte_cryptodev *dev) +{ +int qp_id; + +for (qp_id =0 ; qp_id < dev->data->nb_queue_pairs; qp_id++) { +struct ccp_qp *qp = dev->data->queue_pairs[qp_id]; + +memset (&qp->qp_stats,0 ,sizeof (qp->qp_stats)); + } +} + +static void ccp_pmd_info_get (struct rte_cryptodev *dev,struct rte_cryptodev_info *dev_info) {
@@ -255,8 +285,8 @@ struct rte_cryptodev_ops ccp_ops = { .dev_stop = ccp_pmd_stop, .dev_close = ccp_pmd_close, - .stats_get = NULL, - .stats_reset = NULL, + .stats_get = ccp_pmd_stats_get, + .stats_reset = ccp_pmd_stats_reset, .dev_infos_get = ccp_pmd_info_get,
Signature · 1 line
2.7.4
PATCH v5 9/19 crypto/ccp: support ccp hwrng feature
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_dev.c | 20 ++++++++++++++++++++ drivers/crypto/ccp/ccp_dev.h | 11 +++++++++++ 2 files changed, 31 insertions(+)
drivers/crypto/ccp/ccp_dev.c +20 -0
@@ -62,6 +62,26 @@ ccp_allot_queue(struct rte_cryptodev *cdev, int slot_req)return NULL ; } +int +ccp_read_hwrng (uint32_t *value) +{ +struct ccp_device *dev; + + TAILQ_FOREACH(dev, &ccp_list, next) { +void *vaddr = (void *)(dev->pci.mem_resource[2 ].addr); + +while (dev->hwrng_retries++ <CCP_MAX_TRNG_RETRIES ) { + *value =CCP_READ_REG (vaddr,TRNG_OUT_REG ); +if (*value) { + dev->hwrng_retries =0 ; +return 0 ; + } + } + dev->hwrng_retries =0 ; + } +return -1 ; +} +static const struct rte_memzone * ccp_queue_dma_zone_reserve(const char *queue_name, uint32_t queue_size,
drivers/crypto/ccp/ccp_dev.h +11 -0
@@ -21,6 +21,7 @@/**< CCP sspecific */ #define MAX_HW_QUEUES 5 +#define CCP_MAX_TRNG_RETRIES 10/**< CCP Register Mappings */ #define Q_MASK_REG 0x000
@@ -197,6 +198,8 @@ struct ccp_device {/**< protection for shared lsb region allocation */ int qidx;/**< current queue index */ +int hwrng_retries; +/**< retry counter for CCP TRNG */ } __rte_cache_aligned;/**< CCP H/W engine related */
@@ -428,4 +431,12 @@ int ccp_probe_devices(const struct rte_pci_id *ccp_id);*/ struct ccp_queue *ccp_allot_queue (struct rte_cryptodev *dev,int slot_req); +/** +* read hwrng value +* +* @param trng_value data pointer to write RNG value +* @return 0 on success otherwise -1 +*/ +int ccp_read_hwrng (uint32_t *trng_value); +#endif /* _CCP_DEV_H_ */
Signature · 1 line
2.7.4
PATCH v5 10/19 crypto/ccp: support aes cipher algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 197 ++++++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_crypto.h | 13 +++ drivers/crypto/ccp/ccp_dev.h | 53 +++++++++++ drivers/crypto/ccp/ccp_pmd_ops.c | 60 ++++++++++++ 4 files changed, 321 insertions(+), 2 deletions(-)
drivers/crypto/ccp/ccp_crypto.c +195 -2
@@ -54,6 +54,7 @@ ccp_configure_session_cipher(struct ccp_session *sess, const struct rte_crypto_sym_xform *xform) {const struct rte_crypto_cipher_xform *cipher_xform =NULL ; +size_t i; cipher_xform = &xform->cipher;
@@ -73,6 +74,21 @@ ccp_configure_session_cipher(struct ccp_session *sess, sess->iv.length = cipher_xform->iv.length;switch (cipher_xform->algo) { +case RTE_CRYPTO_CIPHER_AES_CTR : + sess->cipher.algo =CCP_CIPHER_ALGO_AES_CTR ; + sess->cipher.um.aes_mode =CCP_AES_MODE_CTR ; + sess->cipher.engine =CCP_ENGINE_AES ; +break ; +case RTE_CRYPTO_CIPHER_AES_ECB : + sess->cipher.algo =CCP_CIPHER_ALGO_AES_CBC ; + sess->cipher.um.aes_mode =CCP_AES_MODE_ECB ; + sess->cipher.engine =CCP_ENGINE_AES ; +break ; +case RTE_CRYPTO_CIPHER_AES_CBC : + sess->cipher.algo =CCP_CIPHER_ALGO_AES_CBC ; + sess->cipher.um.aes_mode =CCP_AES_MODE_CBC ; + sess->cipher.engine =CCP_ENGINE_AES ; +break ;default :CCP_LOG_ERR ("Unsupported cipher algo" );return -1 ;
@@ -80,10 +96,27 @@ ccp_configure_session_cipher(struct ccp_session *sess,switch (sess->cipher.engine) { +case CCP_ENGINE_AES : +if (sess->cipher.key_length ==16 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_128 ; +else if (sess->cipher.key_length ==24 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_192 ; +else if (sess->cipher.key_length ==32 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_256 ; +else { +CCP_LOG_ERR ("Invalid cipher key length" ); +return -1 ; + } +for (i =0 ; i < sess->cipher.key_length ; i++) + sess->cipher.key_ccp[sess->cipher.key_length - i -1 ] = + sess->cipher.key[i]; +break ;default :CCP_LOG_ERR ("Invalid CCP Engine" );return -ENOTSUP ; } + sess->cipher.nonce_phys =rte_mem_virt2phy (sess->cipher.nonce); + sess->cipher.key_phys =rte_mem_virt2phy (sess->cipher.key_ccp);return 0 ; }
@@ -209,6 +242,18 @@ ccp_cipher_slot(struct ccp_session *session)int count =0 ;switch (session->cipher.algo) { +case CCP_CIPHER_ALGO_AES_CBC : + count =2 ; +/**< op + passthrough for iv */ +break ; +case CCP_CIPHER_ALGO_AES_ECB : + count =1 ; +/**<only op*/ +break ; +case CCP_CIPHER_ALGO_AES_CTR : + count =2 ; +/**< op + passthrough for iv */ +break ;default :CCP_LOG_ERR ("Unsupported cipher algo %d" , session->cipher.algo);
@@ -271,10 +316,146 @@ ccp_compute_slot_count(struct ccp_session *session)return count; } +static void +ccp_perform_passthru (struct ccp_passthru *pst, +struct ccp_queue *cmd_q) +{ +struct ccp_desc *desc; +union ccp_function function; + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_PASSTHRU ; + +CCP_CMD_SOC (desc) =0 ; +CCP_CMD_IOC (desc) =0 ; +CCP_CMD_INIT (desc) =0 ; +CCP_CMD_EOM (desc) =0 ; +CCP_CMD_PROT (desc) =0 ; + + function.raw =0 ; +CCP_PT_BYTESWAP (&function) = pst->byte_swap; +CCP_PT_BITWISE (&function) = pst->bit_mod; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = pst->len; + +if (pst->dir) { +CCP_CMD_SRC_LO (desc) = (uint32_t )(pst->src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (pst->src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = (uint32_t )(pst->dest_addr); +CCP_CMD_DST_HI (desc) =0 ; +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SB ; + +if (pst->bit_mod !=CCP_PASSTHRU_BITWISE_NOOP ) +CCP_CMD_LSB_ID (desc) = cmd_q->sb_key; + }else { + +CCP_CMD_SRC_LO (desc) = (uint32_t )(pst->src_addr); +CCP_CMD_SRC_HI (desc) =0 ; +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SB ; + +CCP_CMD_DST_LO (desc) = (uint32_t )(pst->dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (pst->dest_addr); +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + } + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; +} + +static int +ccp_perform_aes (struct rte_crypto_op *op, +struct ccp_queue *cmd_q, +struct ccp_batch_info *b_info) +{ +struct ccp_session *session; +union ccp_function function; +uint8_t *lsb_buf; +struct ccp_passthru pst = {0 }; +struct ccp_desc *desc; +phys_addr_t src_addr, dest_addr, key_addr; +uint8_t *iv; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + function.raw =0 ; + + iv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset); +if (session->cipher.um.aes_mode !=CCP_AES_MODE_ECB ) { +if (session->cipher.um.aes_mode ==CCP_AES_MODE_CTR ) { +rte_memcpy (session->cipher.nonce +AES_BLOCK_SIZE , + iv, session->iv.length); + pst.src_addr = (phys_addr_t )session->cipher.nonce_phys; +CCP_AES_SIZE (&function) =0x1F ; + }else { + lsb_buf = + &(b_info->lsb_buf[b_info->lsb_buf_idx*CCP_SB_BYTES ]); +rte_memcpy (lsb_buf + + (CCP_SB_BYTES - session->iv.length), + iv, session->iv.length); + pst.src_addr = b_info->lsb_buf_phys + + (b_info->lsb_buf_idx *CCP_SB_BYTES ); + b_info->lsb_buf_idx++; + } + + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + } + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->cipher.data.offset); +if (likely (op->sym->m_dst !=NULL )) + dest_addr =rte_pktmbuf_mtophys_offset (op->sym->m_dst, + op->sym->cipher.data.offset); +else + dest_addr = src_addr; + key_addr = session->cipher.key_phys; + +/* prepare desc for aes command */ +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; + +CCP_AES_ENCRYPT (&function) = session->cipher.dir; +CCP_AES_MODE (&function) = session->cipher.um.aes_mode; +CCP_AES_TYPE (&function) = session->cipher.ut.aes_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->cipher.data.length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = ((uint32_t )dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (dest_addr); +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +if (session->cipher.um.aes_mode !=CCP_AES_MODE_ECB ) +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} +static inline int ccp_crypto_cipher (struct rte_crypto_op *op, - struct ccp_queue *cmd_q __rte_unused, - struct ccp_batch_info *b_info __rte_unused) +struct ccp_queue *cmd_q, +struct ccp_batch_info *b_info) {int result =0 ;struct ccp_session *session;
@@ -284,6 +465,18 @@ ccp_crypto_cipher(struct rte_crypto_op *op, ccp_cryptodev_driver_id);switch (session->cipher.algo) { +case CCP_CIPHER_ALGO_AES_CBC : + result =ccp_perform_aes (op, cmd_q, b_info); + b_info->desccnt +=2 ; +break ; +case CCP_CIPHER_ALGO_AES_CTR : + result =ccp_perform_aes (op, cmd_q, b_info); + b_info->desccnt +=2 ; +break ; +case CCP_CIPHER_ALGO_AES_ECB : + result =ccp_perform_aes (op, cmd_q, b_info); + b_info->desccnt +=1 ; +break ;default :CCP_LOG_ERR ("Unsupported cipher algo %d" , session->cipher.algo);
drivers/crypto/ccp/ccp_crypto.h +13 -0
@@ -20,7 +20,20 @@#include "ccp_dev.h" +#define AES_BLOCK_SIZE 16 +#define CMAC_PAD_VALUE 0x80 +#define CTR_NONCE_SIZE 4 +#define CTR_IV_SIZE 8#define CCP_SHA3_CTX_SIZE 200 + +/**Macro helpers for CCP command creation*/ +#define CCP_AES_SIZE (p) ((p)->aes.size) +#define CCP_AES_ENCRYPT (p) ((p)->aes.encrypt) +#define CCP_AES_MODE (p) ((p)->aes.mode) +#define CCP_AES_TYPE (p) ((p)->aes.type) +#define CCP_PT_BYTESWAP (p) ((p)->pt.byteswap) +#define CCP_PT_BITWISE (p) ((p)->pt.bitwise) +/** * CCP supported AES modes */
drivers/crypto/ccp/ccp_dev.h +53 -0
75 lines not on this page · raw message
drivers/crypto/ccp/ccp_pmd_ops.c +60 -0
66 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v5 11/19 crypto/ccp: support 3des cipher algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 132 ++++++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_crypto.h | 3 + drivers/crypto/ccp/ccp_pmd_ops.c | 20 ++++++ 3 files changed, 154 insertions(+), 1 deletion(-)
drivers/crypto/ccp/ccp_crypto.c +131 -1
@@ -54,7 +54,7 @@ ccp_configure_session_cipher(struct ccp_session *sess, const struct rte_crypto_sym_xform *xform) {const struct rte_crypto_cipher_xform *cipher_xform =NULL ; -size_t i; +size_t i, j, x; cipher_xform = &xform->cipher;
@@ -89,6 +89,11 @@ ccp_configure_session_cipher(struct ccp_session *sess, sess->cipher.um.aes_mode =CCP_AES_MODE_CBC ; sess->cipher.engine =CCP_ENGINE_AES ;break ; +case RTE_CRYPTO_CIPHER_3DES_CBC : + sess->cipher.algo =CCP_CIPHER_ALGO_3DES_CBC ; + sess->cipher.um.des_mode =CCP_DES_MODE_CBC ; + sess->cipher.engine =CCP_ENGINE_3DES ; +break ;default :CCP_LOG_ERR ("Unsupported cipher algo" );return -1 ;
@@ -111,6 +116,20 @@ ccp_configure_session_cipher(struct ccp_session *sess, sess->cipher.key_ccp[sess->cipher.key_length - i -1 ] = sess->cipher.key[i];break ; +case CCP_ENGINE_3DES : +if (sess->cipher.key_length ==16 ) + sess->cipher.ut.des_type =CCP_DES_TYPE_128 ; +else if (sess->cipher.key_length ==24 ) + sess->cipher.ut.des_type =CCP_DES_TYPE_192 ; +else { +CCP_LOG_ERR ("Invalid cipher key length" ); +return -1 ; + } +for (j =0 , x =0 ; j < sess->cipher.key_length/8 ; j++, x +=8 ) +for (i =0 ; i <8 ; i++) + sess->cipher.key_ccp[(8 + x) - i -1 ] = + sess->cipher.key[i + x]; +break ;default :CCP_LOG_ERR ("Invalid CCP Engine" );return -ENOTSUP ;
@@ -254,6 +273,10 @@ ccp_cipher_slot(struct ccp_session *session) count =2 ;/**< op + passthrough for iv */ break ; +case CCP_CIPHER_ALGO_3DES_CBC : + count =2 ; +/**< op + passthrough for iv */ +break ;default :CCP_LOG_ERR ("Unsupported cipher algo %d" , session->cipher.algo);
@@ -452,6 +475,109 @@ ccp_perform_aes(struct rte_crypto_op *op,return 0 ; } +static int +ccp_perform_3des (struct rte_crypto_op *op, +struct ccp_queue *cmd_q, +struct ccp_batch_info *b_info) +{ +struct ccp_session *session; +union ccp_function function; +unsigned char *lsb_buf; +struct ccp_passthru pst; +struct ccp_desc *desc; +uint32_t tail; +uint8_t *iv; +phys_addr_t src_addr, dest_addr, key_addr; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + + iv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset); +switch (session->cipher.um.des_mode) { +case CCP_DES_MODE_CBC : + lsb_buf = &(b_info->lsb_buf[b_info->lsb_buf_idx*CCP_SB_BYTES ]); + b_info->lsb_buf_idx++; + +rte_memcpy (lsb_buf + (CCP_SB_BYTES - session->iv.length), + iv, session->iv.length); + + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *) lsb_buf); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); +break ; +case CCP_DES_MODE_CFB : +case CCP_DES_MODE_ECB : +CCP_LOG_ERR ("Unsupported DES cipher mode" ); +return -ENOTSUP ; + } + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->cipher.data.offset); +if (unlikely (op->sym->m_dst !=NULL )) + dest_addr = +rte_pktmbuf_mtophys_offset (op->sym->m_dst, + op->sym->cipher.data.offset); +else + dest_addr = src_addr; + + key_addr =rte_mem_virt2phy (session->cipher.key_ccp); + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; + +memset (desc,0 ,Q_DESC_SIZE ); + +/* prepare desc for des command */ +CCP_CMD_ENGINE (desc) =CCP_ENGINE_3DES ; + +CCP_CMD_SOC (desc) =0 ; +CCP_CMD_IOC (desc) =0 ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_PROT (desc) =0 ; + + function.raw =0 ; +CCP_DES_ENCRYPT (&function) = session->cipher.dir; +CCP_DES_MODE (&function) = session->cipher.um.des_mode; +CCP_DES_TYPE (&function) = session->cipher.ut.des_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->cipher.data.length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = ((uint32_t )dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (dest_addr); +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +if (session->cipher.um.des_mode) +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + +/* Write the new tail address back to the queue register */ + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +/* Turn the queue back on using our cached control register */ +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} + static inline int ccp_crypto_cipher(struct rte_crypto_op *op, struct ccp_queue *cmd_q,
@@ -477,6 +603,10 @@ ccp_crypto_cipher(struct rte_crypto_op *op, result =ccp_perform_aes (op, cmd_q, b_info); b_info->desccnt +=1 ;break ; +case CCP_CIPHER_ALGO_3DES_CBC : + result =ccp_perform_3des (op, cmd_q, b_info); + b_info->desccnt +=2 ; +break ;default :CCP_LOG_ERR ("Unsupported cipher algo %d" , session->cipher.algo);
drivers/crypto/ccp/ccp_crypto.h +3 -0
@@ -31,6 +31,9 @@#define CCP_AES_ENCRYPT (p) ((p)->aes.encrypt)#define CCP_AES_MODE (p) ((p)->aes.mode)#define CCP_AES_TYPE (p) ((p)->aes.type) +#define CCP_DES_ENCRYPT (p) ((p)->des.encrypt) +#define CCP_DES_MODE (p) ((p)->des.mode) +#define CCP_DES_TYPE (p) ((p)->des.type)#define CCP_PT_BYTESWAP (p) ((p)->pt.byteswap)#define CCP_PT_BITWISE (p) ((p)->pt.bitwise)
drivers/crypto/ccp/ccp_pmd_ops.c +20 -0
@@ -73,6 +73,26 @@ static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = { }, } }, } }, + {/* 3DES CBC */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type =RTE_CRYPTO_SYM_XFORM_CIPHER , + {.cipher = { + .algo =RTE_CRYPTO_CIPHER_3DES_CBC , + .block_size = 8, + .key_size = { + .min =16 , + .max = 24, + .increment = 8 + }, + .iv_size = { + .min =8 , + .max = 8, + .increment = 0 + } + }, } + }, } + },RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST () };
Signature · 1 line
2.7.4
PATCH v5 12/19 crypto/ccp: support aes-cmac auth algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 277 ++++++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_pmd_ops.c | 20 +++ 2 files changed, 295 insertions(+), 2 deletions(-)
drivers/crypto/ccp/ccp_crypto.c +275 -2
@@ -10,6 +10,8 @@#include <sys/queue.h> #include <sys/types.h> #include <unistd.h> +#include <openssl/cmac.h> /*sub key apis*/ +#include <openssl/evp.h> /*sub key apis*/ #include <rte_hexdump.h> #include <rte_memzone.h>
@@ -48,6 +50,84 @@ ccp_get_cmd_id(const struct rte_crypto_sym_xform *xform)return res; } +/* prepare temporary keys K1 and K2 */ +static void prepare_key (unsigned char *k,unsigned char *l,int bl) +{ +int i; +/* Shift block to left, including carry */ +for (i =0 ; i < bl; i++) { + k[i] = l[i] <<1 ; +if (i < bl -1 && l[i +1 ] &0x80 ) + k[i] |=1 ; + } +/* If MSB set fixup with R */ +if (l[0 ] &0x80 ) + k[bl -1 ] ^= bl ==16 ?0x87 :0x1b ; +} + +/* subkeys K1 and K2 generation for CMAC */ +static int +generate_cmac_subkeys (struct ccp_session *sess) +{ +const EVP_CIPHER *algo; +EVP_CIPHER_CTX *ctx; +unsigned char *ccp_ctx; +size_t i; +int dstlen, totlen; +unsigned char zero_iv[AES_BLOCK_SIZE ] = {0 }; +unsigned char dst[2 *AES_BLOCK_SIZE ] = {0 }; +unsigned char k1[AES_BLOCK_SIZE ] = {0 }; +unsigned char k2[AES_BLOCK_SIZE ] = {0 }; + +if (sess->auth.ut.aes_type ==CCP_AES_TYPE_128 ) + algo =EVP_aes_128_cbc (); +else if (sess->auth.ut.aes_type ==CCP_AES_TYPE_192 ) + algo =EVP_aes_192_cbc (); +else if (sess->auth.ut.aes_type ==CCP_AES_TYPE_256 ) + algo =EVP_aes_256_cbc (); +else { +CCP_LOG_ERR ("Invalid CMAC type length" ); +return -1 ; + } + + ctx =EVP_CIPHER_CTX_new (); +if (!ctx) { +CCP_LOG_ERR ("ctx creation failed" ); +return -1 ; + } +if (EVP_EncryptInit (ctx, algo, (unsigned char *)sess->auth.key, + (unsigned char *)zero_iv) <=0 ) + goto key_generate_err; +if (EVP_CIPHER_CTX_set_padding (ctx,0 ) <=0 ) + goto key_generate_err; +if (EVP_EncryptUpdate (ctx, dst, &dstlen, zero_iv, +AES_BLOCK_SIZE ) <=0 ) + goto key_generate_err; +if (EVP_EncryptFinal_ex (ctx, dst + dstlen, &totlen) <=0 ) + goto key_generate_err; + +memset (sess->auth.pre_compute,0 ,CCP_SB_BYTES *2 ); + + ccp_ctx = (unsigned char *)(sess->auth.pre_compute +CCP_SB_BYTES -1 ); +prepare_key (k1, dst,AES_BLOCK_SIZE ); +for (i =0 ; i <AES_BLOCK_SIZE ; i++, ccp_ctx--) + *ccp_ctx = k1[i]; + + ccp_ctx = (unsigned char *)(sess->auth.pre_compute + + (2 *CCP_SB_BYTES ) -1 ); +prepare_key (k2, k1,AES_BLOCK_SIZE ); +for (i =0 ; i <AES_BLOCK_SIZE ; i++, ccp_ctx--) + *ccp_ctx = k2[i]; + +EVP_CIPHER_CTX_free (ctx); + +return 0 ; + +key_generate_err: +CCP_LOG_ERR ("CMAC Init failed" ); +return -1 ; +} +/* configure session */ static int ccp_configure_session_cipher(struct ccp_session *sess,
@@ -144,6 +224,7 @@ ccp_configure_session_auth(struct ccp_session *sess, const struct rte_crypto_sym_xform *xform) {const struct rte_crypto_auth_xform *auth_xform =NULL ; +size_t i; auth_xform = &xform->auth;
@@ -153,6 +234,33 @@ ccp_configure_session_auth(struct ccp_session *sess,else sess->auth.op =CCP_AUTH_OP_VERIFY ;switch (auth_xform->algo) { +case RTE_CRYPTO_AUTH_AES_CMAC : + sess->auth.algo =CCP_AUTH_ALGO_AES_CMAC ; + sess->auth.engine =CCP_ENGINE_AES ; + sess->auth.um.aes_mode =CCP_AES_MODE_CMAC ; + sess->auth.key_length = auth_xform->key.length; +/**<padding and hash result*/ + sess->auth.ctx_len =CCP_SB_BYTES <<1 ; + sess->auth.offset =AES_BLOCK_SIZE ; + sess->auth.block_size =AES_BLOCK_SIZE ; +if (sess->auth.key_length ==16 ) + sess->auth.ut.aes_type =CCP_AES_TYPE_128 ; +else if (sess->auth.key_length ==24 ) + sess->auth.ut.aes_type =CCP_AES_TYPE_192 ; +else if (sess->auth.key_length ==32 ) + sess->auth.ut.aes_type =CCP_AES_TYPE_256 ; +else { +CCP_LOG_ERR ("Invalid CMAC key length" ); +return -1 ; + } +rte_memcpy (sess->auth.key, auth_xform->key.data, + sess->auth.key_length); +for (i =0 ; i < sess->auth.key_length; i++) + sess->auth.key_ccp[sess->auth.key_length - i -1 ] = + sess->auth.key[i]; +if (generate_cmac_subkeys (sess)) +return -1 ; +break ;default :CCP_LOG_ERR ("Unsupported hash algo" );return -ENOTSUP ;
@@ -290,6 +398,15 @@ ccp_auth_slot(struct ccp_session *session)int count =0 ;switch (session->auth.algo) { +case CCP_AUTH_ALGO_AES_CMAC : + count =4 ; +/** +* op +* extra descriptor in padding case +* (k1/k2(255:128) with iv(127:0)) +* Retrieve result +*/ +break ;default :CCP_LOG_ERR ("Unsupported auth algo %d" , session->auth.algo);
@@ -389,6 +506,158 @@ ccp_perform_passthru(struct ccp_passthru *pst, }static int +ccp_perform_aes_cmac (struct rte_crypto_op *op, +struct ccp_queue *cmd_q) +{ +struct ccp_session *session; +union ccp_function function; +struct ccp_passthru pst; +struct ccp_desc *desc; +uint32_t tail; +uint8_t *src_tb, *append_ptr, *ctx_addr; +phys_addr_t src_addr, dest_addr, key_addr; +int length, non_align_len; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + key_addr =rte_mem_virt2phy (session->auth.key_ccp); + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->auth.data.offset); + append_ptr = (uint8_t *)rte_pktmbuf_append (op->sym->m_src, + session->auth.ctx_len); + dest_addr = (phys_addr_t )rte_mem_virt2phy ((void *)append_ptr); + + function.raw =0 ; +CCP_AES_ENCRYPT (&function) =CCP_CIPHER_DIR_ENCRYPT ; +CCP_AES_MODE (&function) = session->auth.um.aes_mode; +CCP_AES_TYPE (&function) = session->auth.ut.aes_type; + +if (op->sym->auth.data.length % session->auth.block_size ==0 ) { + + ctx_addr = session->auth.pre_compute; +memset (ctx_addr,0 ,AES_BLOCK_SIZE ); + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *)ctx_addr); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +/* prepare desc for aes-cmac command */ +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->auth.data.length; +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + + tail = + (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + }else { + ctx_addr = session->auth.pre_compute +CCP_SB_BYTES ; +memset (ctx_addr,0 ,AES_BLOCK_SIZE ); + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *)ctx_addr); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + + length = (op->sym->auth.data.length /AES_BLOCK_SIZE ); + length *=AES_BLOCK_SIZE ; + non_align_len = op->sym->auth.data.length - length; +/* prepare desc for aes-cmac command */ +/*Command 1*/ + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = length; +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +/*Command 2*/ + append_ptr = append_ptr +CCP_SB_BYTES ; +memset (append_ptr,0 ,AES_BLOCK_SIZE ); + src_tb =rte_pktmbuf_mtod_offset (op->sym->m_src, + uint8_t *, + op->sym->auth.data.offset + + length); +rte_memcpy (append_ptr, src_tb, non_align_len); + append_ptr[non_align_len] =CMAC_PAD_VALUE ; + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_FUNCTION (desc) = function.raw; +CCP_CMD_LEN (desc) =AES_BLOCK_SIZE ; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )(dest_addr +CCP_SB_BYTES )); +CCP_CMD_SRC_HI (desc) =high32_value (dest_addr +CCP_SB_BYTES ); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + tail = + (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + } +/* Retrieve result */ + pst.dest_addr = dest_addr; + pst.src_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} + +static int ccp_perform_aes (struct rte_crypto_op *op,struct ccp_queue *cmd_q,struct ccp_batch_info *b_info)
@@ -617,8 +886,8 @@ ccp_crypto_cipher(struct rte_crypto_op *op,static inline int ccp_crypto_auth (struct rte_crypto_op *op, - struct ccp_queue *cmd_q __rte_unused, - struct ccp_batch_info *b_info __rte_unused) +struct ccp_queue *cmd_q, +struct ccp_batch_info *b_info) {int result =0 ;
@@ -629,6 +898,10 @@ ccp_crypto_auth(struct rte_crypto_op *op, ccp_cryptodev_driver_id);switch (session->auth.algo) { +case CCP_AUTH_ALGO_AES_CMAC : + result =ccp_perform_aes_cmac (op, cmd_q); + b_info->desccnt +=4 ; +break ;default :CCP_LOG_ERR ("Unsupported auth algo %d" , session->auth.algo);
drivers/crypto/ccp/ccp_pmd_ops.c +20 -0
@@ -13,6 +13,26 @@#include "ccp_crypto.h" static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = { + {/*AES-CMAC */ + .op =RTE_CRYPTO_OP_TYPE_SYMMETRIC , + {.sym = { + .xform_type =RTE_CRYPTO_SYM_XFORM_AUTH , + {.auth = { + .algo =RTE_CRYPTO_AUTH_AES_CMAC , + .block_size =16 , + .key_size = { + .min =16 , + .max =32 , + .increment =8 + }, + .digest_size = { + .min =16 , + .max =16 , + .increment =0 + }, + }, } + }, } + }, {/* AES ECB */ .op =RTE_CRYPTO_OP_TYPE_SYMMETRIC , {.sym = {
Signature · 1 line
2.7.4
PATCH v5 13/19 crypto/ccp: support aes-gcm aead algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 235 ++++++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_pmd_ops.c | 30 +++++ 2 files changed, 261 insertions(+), 4 deletions(-)
drivers/crypto/ccp/ccp_crypto.c +231 -4
@@ -273,6 +273,7 @@ ccp_configure_session_aead(struct ccp_session *sess, const struct rte_crypto_sym_xform *xform) {const struct rte_crypto_aead_xform *aead_xform =NULL ; +size_t i; aead_xform = &xform->aead;
@@ -287,6 +288,7 @@ ccp_configure_session_aead(struct ccp_session *sess, sess->cipher.dir =CCP_CIPHER_DIR_DECRYPT ; sess->auth.op =CCP_AUTH_OP_VERIFY ; } + sess->aead_algo = aead_xform->algo; sess->auth.aad_length = aead_xform->aad_length; sess->auth.digest_length = aead_xform->digest_length;
@@ -295,10 +297,37 @@ ccp_configure_session_aead(struct ccp_session *sess, sess->iv.length = aead_xform->iv.length;switch (aead_xform->algo) { +case RTE_CRYPTO_AEAD_AES_GCM : + sess->cipher.algo =CCP_CIPHER_ALGO_AES_GCM ; + sess->cipher.um.aes_mode =CCP_AES_MODE_GCTR ; + sess->cipher.engine =CCP_ENGINE_AES ; +if (sess->cipher.key_length ==16 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_128 ; +else if (sess->cipher.key_length ==24 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_192 ; +else if (sess->cipher.key_length ==32 ) + sess->cipher.ut.aes_type =CCP_AES_TYPE_256 ; +else { +CCP_LOG_ERR ("Invalid aead key length" ); +return -1 ; + } +for (i =0 ; i < sess->cipher.key_length; i++) + sess->cipher.key_ccp[sess->cipher.key_length - i -1 ] = + sess->cipher.key[i]; + sess->auth.algo =CCP_AUTH_ALGO_AES_GCM ; + sess->auth.engine =CCP_ENGINE_AES ; + sess->auth.um.aes_mode =CCP_AES_MODE_GHASH ; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =0 ; + sess->auth.block_size =AES_BLOCK_SIZE ; + sess->cmd_id =CCP_CMD_COMBINED ; +break ;default :CCP_LOG_ERR ("Unsupported aead algo" );return -ENOTSUP ; } + sess->cipher.nonce_phys =rte_mem_virt2phy (sess->cipher.nonce); + sess->cipher.key_phys =rte_mem_virt2phy (sess->cipher.key_ccp);return 0 ; }
@@ -421,10 +450,27 @@ ccp_aead_slot(struct ccp_session *session)int count =0 ;switch (session->aead_algo) { +case RTE_CRYPTO_AEAD_AES_GCM : +break ;default :CCP_LOG_ERR ("Unsupported aead algo %d" , session->aead_algo); } +switch (session->auth.algo) { +case CCP_AUTH_ALGO_AES_GCM : + count =5 ; +/** +* 1. Passthru iv +* 2. Hash AAD +* 3. GCTR +* 4. Reload passthru +* 5. Hash Final tag +*/ +break ; +default : +CCP_LOG_ERR ("Unsupported combined auth ALGO %d" , + session->auth.algo); + }return count; }
@@ -847,6 +893,179 @@ ccp_perform_3des(struct rte_crypto_op *op,return 0 ; } +static int +ccp_perform_aes_gcm (struct rte_crypto_op *op,struct ccp_queue *cmd_q) +{ +struct ccp_session *session; +union ccp_function function; +uint8_t *iv; +struct ccp_passthru pst; +struct ccp_desc *desc; +uint32_t tail; +uint64_t *temp; +phys_addr_t src_addr, dest_addr, key_addr, aad_addr; +phys_addr_t digest_dest_addr; +int length, non_align_len; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + iv = rte_crypto_op_ctod_offset(op, uint8_t *, session->iv.offset); + key_addr = session->cipher.key_phys; + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->aead.data.offset); +if (unlikely (op->sym->m_dst !=NULL )) + dest_addr =rte_pktmbuf_mtophys_offset (op->sym->m_dst, + op->sym->aead.data.offset); +else + dest_addr = src_addr; +rte_pktmbuf_append (op->sym->m_src, session->auth.ctx_len); + digest_dest_addr = op->sym->aead.digest.phys_addr; + temp = (uint64_t *)(op->sym->aead.digest.data +AES_BLOCK_SIZE ); + *temp++ =rte_bswap64 (session->auth.aad_length <<3 ); + *temp =rte_bswap64 (op->sym->aead.data.length <<3 ); + + non_align_len = op->sym->aead.data.length %AES_BLOCK_SIZE ; + length =CCP_ALIGN (op->sym->aead.data.length,AES_BLOCK_SIZE ); + + aad_addr = op->sym->aead.aad.phys_addr; + +/* CMD1 IV Passthru */ +rte_memcpy (session->cipher.nonce +AES_BLOCK_SIZE , iv, + session->iv.length); + pst.src_addr = session->cipher.nonce_phys; + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =CCP_SB_BYTES ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + +/* CMD2 GHASH-AAD */ + function.raw =0 ; +CCP_AES_ENCRYPT (&function) =CCP_AES_MODE_GHASH_AAD ; +CCP_AES_MODE (&function) =CCP_AES_MODE_GHASH ; +CCP_AES_TYPE (&function) = session->cipher.ut.aes_type; + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = session->auth.aad_length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )aad_addr); +CCP_CMD_SRC_HI (desc) =high32_value (aad_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* CMD3 : GCTR Plain text */ + function.raw =0 ; +CCP_AES_ENCRYPT (&function) = session->cipher.dir; +CCP_AES_MODE (&function) =CCP_AES_MODE_GCTR ; +CCP_AES_TYPE (&function) = session->cipher.ut.aes_type; +if (non_align_len ==0 ) +CCP_AES_SIZE (&function) = (AES_BLOCK_SIZE <<3 ) -1 ; +else +CCP_AES_SIZE (&function) = (non_align_len <<3 ) -1 ; + + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = ((uint32_t )dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (dest_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* CMD4 : PT to copy IV */ + pst.src_addr = session->cipher.nonce_phys; + pst.dest_addr = (phys_addr_t)(cmd_q->sb_iv *CCP_SB_BYTES ); + pst.len =AES_BLOCK_SIZE ; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + +/* CMD5 : GHASH-Final */ + function.raw =0 ; +CCP_AES_ENCRYPT (&function) =CCP_AES_MODE_GHASH_FINAL ; +CCP_AES_MODE (&function) =CCP_AES_MODE_GHASH ; +CCP_AES_TYPE (&function) = session->cipher.ut.aes_type; + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_AES ; +CCP_CMD_FUNCTION (desc) = function.raw; +/* Last block (AAD_len || PT_len)*/ +CCP_CMD_LEN (desc) =AES_BLOCK_SIZE ; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )digest_dest_addr +AES_BLOCK_SIZE ); +CCP_CMD_SRC_HI (desc) =high32_value (digest_dest_addr +AES_BLOCK_SIZE ); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = ((uint32_t )digest_dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (digest_dest_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )key_addr); +CCP_CMD_KEY_HI (desc) =high32_value (key_addr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_iv; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} + static inline int ccp_crypto_cipher(struct rte_crypto_op *op, struct ccp_queue *cmd_q,
@@ -913,17 +1132,25 @@ ccp_crypto_auth(struct rte_crypto_op *op,static inline int ccp_crypto_aead (struct rte_crypto_op *op, - struct ccp_queue *cmd_q __rte_unused, - struct ccp_batch_info *b_info __rte_unused) +struct ccp_queue *cmd_q, +struct ccp_batch_info *b_info) {int result =0 ;struct ccp_session *session; session = (struct ccp_session *)get_session_private_data ( - op->sym->session, + op->sym->session, ccp_cryptodev_driver_id); -switch (session->aead_algo) { +switch (session->auth.algo) { +case CCP_AUTH_ALGO_AES_GCM : +if (session->cipher.algo !=CCP_CIPHER_ALGO_AES_GCM ) { +CCP_LOG_ERR ("Incorrect chain order" ); +return -1 ; + } + result =ccp_perform_aes_gcm (op, cmd_q); + b_info->desccnt +=5 ; +break ;default :CCP_LOG_ERR ("Unsupported aead algo %d" , session->aead_algo);
drivers/crypto/ccp/ccp_pmd_ops.c +30 -0
@@ -113,6 +113,36 @@ static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = { }, } }, } }, + {/* AES GCM */ + .op = RTE_CRYPTO_OP_TYPE_SYMMETRIC, + {.sym = { + .xform_type =RTE_CRYPTO_SYM_XFORM_AEAD , + {.aead = { + .algo =RTE_CRYPTO_AEAD_AES_GCM , + .block_size = 16, + .key_size = { + .min =16 , + .max = 32, + .increment = 8 + }, + .digest_size = { + .min =16 , + .max = 16, + .increment = 0 + }, + .aad_size = { + .min =0 , + .max = 65535, + .increment = 1 + }, + .iv_size = { + .min =12 , + .max = 16, + .increment = 4 + }, + }, } + }, } + },RTE_CRYPTODEV_END_OF_CAPABILITIES_LIST () };
Signature · 1 line
2.7.4
PATCH v5 14/19 crypto/ccp: support sha1 authentication algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 367 +++++++++++++++++++++++++++++++++++++++ drivers/crypto/ccp/ccp_crypto.h | 23 +++ drivers/crypto/ccp/ccp_pmd_ops.c | 42 +++++ 3 files changed, 432 insertions(+)
drivers/crypto/ccp/ccp_crypto.c +367 -0
@@ -10,6 +10,7 @@#include <sys/queue.h> #include <sys/types.h> #include <unistd.h> +#include <openssl/sha.h> #include <openssl/cmac.h> /*sub key apis*/ #include <openssl/evp.h> /*sub key apis*/
@@ -26,6 +27,14 @@#include "ccp_pci.h" #include "ccp_pmd_private.h" +/* SHA initial context values */ +static uint32_t ccp_sha1_init[SHA_COMMON_DIGEST_SIZE /sizeof (uint32_t )] = { +SHA1_H4 ,SHA1_H3 , +SHA1_H2 ,SHA1_H1 , +SHA1_H0 ,0x0U , +0x0U ,0x0U , +}; +static enum ccp_cmd_order ccp_get_cmd_id (const struct rte_crypto_sym_xform *xform) {
@@ -50,6 +59,59 @@ ccp_get_cmd_id(const struct rte_crypto_sym_xform *xform)return res; } +/* partial hash using openssl */ +static int partial_hash_sha1 (uint8_t *data_in,uint8_t *data_out) +{ +SHA_CTX ctx; + +if (!SHA1_Init (&ctx)) +return -EFAULT ; +SHA1_Transform (&ctx, data_in); +rte_memcpy (data_out, &ctx,SHA_DIGEST_LENGTH ); +return 0 ; +} + +static int generate_partial_hash (struct ccp_session *sess) +{ + +uint8_t ipad[sess->auth.block_size]; +uint8_t opad[sess->auth.block_size]; +uint8_t *ipad_t, *opad_t; +uint32_t *hash_value_be32, hash_temp32[8 ]; +int i, count; + + opad_t = ipad_t = (uint8_t *)sess->auth.key; + + hash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute); + +/* considering key size is always equal to block size of algorithm */ +for (i =0 ; i < sess->auth.block_size; i++) { + ipad[i] = (ipad_t[i] ^HMAC_IPAD_VALUE ); + opad[i] = (opad_t[i] ^HMAC_OPAD_VALUE ); + } + +switch (sess->auth.algo) { +case CCP_AUTH_ALGO_SHA1_HMAC : + count =SHA1_DIGEST_SIZE >>2 ; + +if (partial_hash_sha1 (ipad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; + + hash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha1 (opad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; +return 0 ; +default : +CCP_LOG_ERR ("Invalid auth algo" ); +return -1 ; + } +} +/* prepare temporary keys K1 and K2 */ static void prepare_key (unsigned char *k,unsigned char *l,int bl) {
@@ -234,6 +296,31 @@ ccp_configure_session_auth(struct ccp_session *sess,else sess->auth.op =CCP_AUTH_OP_VERIFY ;switch (auth_xform->algo) { +case RTE_CRYPTO_AUTH_SHA1 : + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.algo =CCP_AUTH_ALGO_SHA1 ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_1 ; + sess->auth.ctx = (void *)ccp_sha1_init; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA1_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA1_HMAC : +if (auth_xform->key.length >SHA1_BLOCK_SIZE ) +return -1 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.algo =CCP_AUTH_ALGO_SHA1_HMAC ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_1 ; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA1_DIGEST_SIZE ; + sess->auth.block_size =SHA1_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 , sess->auth.ctx_len <<1 ); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ;case RTE_CRYPTO_AUTH_AES_CMAC : sess->auth.algo =CCP_AUTH_ALGO_AES_CMAC ; sess->auth.engine =CCP_ENGINE_AES ;
@@ -427,6 +514,13 @@ ccp_auth_slot(struct ccp_session *session)int count =0 ;switch (session->auth.algo) { +case CCP_AUTH_ALGO_SHA1 : + count =3 ; +/**< op + lsb passthrough cpy to/from*/ +break ; +case CCP_AUTH_ALGO_SHA1_HMAC : + count =6 ; +break ;case CCP_AUTH_ALGO_AES_CMAC : count =4 ;/**
@@ -552,6 +646,271 @@ ccp_perform_passthru(struct ccp_passthru *pst, }static int +ccp_perform_hmac (struct rte_crypto_op *op, +struct ccp_queue *cmd_q) +{ + +struct ccp_session *session; +union ccp_function function; +struct ccp_desc *desc; +uint32_t tail; +phys_addr_t src_addr, dest_addr, dest_addr_t; +struct ccp_passthru pst; +uint64_t auth_msg_bits; +void *append_ptr; +uint8_t *addr; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + addr = session->auth.pre_compute; + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->auth.data.offset); + append_ptr = (void *)rte_pktmbuf_append (op->sym->m_src, + session->auth.ctx_len); + dest_addr = (phys_addr_t )rte_mem_virt2phy (append_ptr); + dest_addr_t = dest_addr; + +/** Load PHash1 to LSB*/ + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *)addr); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.len = session->auth.ctx_len; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + +/**sha engine command descriptor for IntermediateHash*/ + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; + +CCP_CMD_SOC (desc) =0 ; +CCP_CMD_IOC (desc) =0 ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_PROT (desc) =0 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->auth.data.length; + auth_msg_bits = (op->sym->auth.data.length + + session->auth.block_size) *8 ; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_sha; +CCP_CMD_SHA_LO (desc) = ((uint32_t )auth_msg_bits); +CCP_CMD_SHA_HI (desc) =high32_value (auth_msg_bits); + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* Intermediate Hash value retrieve */ +if ((session->auth.ut.sha_type ==CCP_SHA_TYPE_384 ) || + (session->auth.ut.sha_type ==CCP_SHA_TYPE_512 )) { + + pst.src_addr = + (phys_addr_t)((cmd_q->sb_sha +1 ) *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t; + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t +CCP_SB_BYTES ; + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + }else { + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t; + pst.len = session->auth.ctx_len; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + } + +/** Load PHash2 to LSB*/ + addr += session->auth.ctx_len; + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *)addr); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.len = session->auth.ctx_len; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + +/**sha engine command descriptor for FinalHash*/ + dest_addr_t += session->auth.offset; + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; + +CCP_CMD_SOC (desc) =0 ; +CCP_CMD_IOC (desc) =0 ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_PROT (desc) =0 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = (session->auth.ctx_len - + session->auth.offset); + auth_msg_bits = (session->auth.block_size + + session->auth.ctx_len - + session->auth.offset) *8 ; + +CCP_CMD_SRC_LO (desc) = (uint32_t )(dest_addr_t); +CCP_CMD_SRC_HI (desc) =high32_value (dest_addr_t); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_sha; +CCP_CMD_SHA_LO (desc) = ((uint32_t )auth_msg_bits); +CCP_CMD_SHA_HI (desc) =high32_value (auth_msg_bits); + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* Retrieve hmac output */ + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr; + pst.len = session->auth.ctx_len; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; +if ((session->auth.ut.sha_type ==CCP_SHA_TYPE_384 ) || + (session->auth.ut.sha_type ==CCP_SHA_TYPE_512 )) + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +else + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; + +} + +static int +ccp_perform_sha (struct rte_crypto_op *op, +struct ccp_queue *cmd_q) +{ +struct ccp_session *session; +union ccp_function function; +struct ccp_desc *desc; +uint32_t tail; +phys_addr_t src_addr, dest_addr; +struct ccp_passthru pst; +void *append_ptr; +uint64_t auth_msg_bits; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->auth.data.offset); + + append_ptr = (void *)rte_pktmbuf_append (op->sym->m_src, + session->auth.ctx_len); + dest_addr = (phys_addr_t )rte_mem_virt2phy (append_ptr); + +/** Passthru sha context*/ + + pst.src_addr = (phys_addr_t )rte_mem_virt2phy ((void *) + session->auth.ctx); + pst.dest_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.len = session->auth.ctx_len; + pst.dir =1 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +ccp_perform_passthru (&pst, cmd_q); + +/**prepare sha command descriptor*/ + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; + +CCP_CMD_SOC (desc) =0 ; +CCP_CMD_IOC (desc) =0 ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; +CCP_CMD_PROT (desc) =0 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->auth.data.length; + auth_msg_bits = op->sym->auth.data.length *8 ; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_LSB_ID (desc) = cmd_q->sb_sha; +CCP_CMD_SHA_LO (desc) = ((uint32_t )auth_msg_bits); +CCP_CMD_SHA_HI (desc) =high32_value (auth_msg_bits); + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* Hash value retrieve */ + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr; + pst.len = session->auth.ctx_len; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; +if ((session->auth.ut.sha_type ==CCP_SHA_TYPE_384 ) || + (session->auth.ut.sha_type ==CCP_SHA_TYPE_512 )) + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_NOOP ; +else + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; + +} + +static int ccp_perform_aes_cmac (struct rte_crypto_op *op,struct ccp_queue *cmd_q) {
@@ -1117,6 +1476,14 @@ ccp_crypto_auth(struct rte_crypto_op *op, ccp_cryptodev_driver_id);switch (session->auth.algo) { +case CCP_AUTH_ALGO_SHA1 : + result =ccp_perform_sha (op, cmd_q); + b_info->desccnt +=3 ; +break ; +case CCP_AUTH_ALGO_SHA1_HMAC : + result =ccp_perform_hmac (op, cmd_q); + b_info->desccnt +=6 ; +break ;case CCP_AUTH_ALGO_AES_CMAC : result =ccp_perform_aes_cmac (op, cmd_q); b_info->desccnt +=4 ;
drivers/crypto/ccp/ccp_crypto.h +23 -0
@@ -34,9 +34,32 @@#define CCP_DES_ENCRYPT (p) ((p)->des.encrypt)#define CCP_DES_MODE (p) ((p)->des.mode)#define CCP_DES_TYPE (p) ((p)->des.type) +#define CCP_SHA_TYPE (p) ((p)->sha.type)#define CCP_PT_BYTESWAP (p) ((p)->pt.byteswap)#define CCP_PT_BITWISE (p) ((p)->pt.bitwise) +/* HMAC */ +#define HMAC_IPAD_VALUE 0x36 +#define HMAC_OPAD_VALUE 0x5c + +#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH +#define MD5_DIGEST_SIZE 16 +#define MD5_BLOCK_SIZE 64 +#endif + +/* SHA */ +#define SHA_COMMON_DIGEST_SIZE 32 +#define SHA1_DIGEST_SIZE 20 +#define SHA1_BLOCK_SIZE 64 + +/* SHA LSB intialiazation values */ + +#define SHA1_H0 0x67452301UL +#define SHA1_H1 0xefcdab89UL +#define SHA1_H2 0x98badcfeUL +#define SHA1_H3 0x10325476UL +#define SHA1_H4 0xc3d2e1f0UL +/** * CCP supported AES modes */
drivers/crypto/ccp/ccp_pmd_ops.c +42 -0
48 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v5 15/19 crypto/ccp: support sha2 family authentication algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 270 +++++++++++++++++++++++++++++++++++++++ drivers/crypto/ccp/ccp_crypto.h | 48 +++++++ drivers/crypto/ccp/ccp_pmd_ops.c | 168 ++++++++++++++++++++++++ 3 files changed, 486 insertions(+)
drivers/crypto/ccp/ccp_crypto.c +270 -0
@@ -35,6 +35,34 @@ static uint32_t ccp_sha1_init[SHA_COMMON_DIGEST_SIZE / sizeof(uint32_t)] = { 0x0U, 0x0U, }; +uint32_t ccp_sha224_init[SHA256_DIGEST_SIZE /sizeof (uint32_t )] = { +SHA224_H7 ,SHA224_H6 , +SHA224_H5 ,SHA224_H4 , +SHA224_H3 ,SHA224_H2 , +SHA224_H1 ,SHA224_H0 , +}; + +uint32_t ccp_sha256_init[SHA256_DIGEST_SIZE /sizeof (uint32_t )] = { +SHA256_H7 ,SHA256_H6 , +SHA256_H5 ,SHA256_H4 , +SHA256_H3 ,SHA256_H2 , +SHA256_H1 ,SHA256_H0 , +}; + +uint64_t ccp_sha384_init[SHA512_DIGEST_SIZE /sizeof (uint64_t )] = { +SHA384_H7 ,SHA384_H6 , +SHA384_H5 ,SHA384_H4 , +SHA384_H3 ,SHA384_H2 , +SHA384_H1 ,SHA384_H0 , +}; + +uint64_t ccp_sha512_init[SHA512_DIGEST_SIZE /sizeof (uint64_t )] = { +SHA512_H7 ,SHA512_H6 , +SHA512_H5 ,SHA512_H4 , +SHA512_H3 ,SHA512_H2 , +SHA512_H1 ,SHA512_H0 , +}; +static enum ccp_cmd_order ccp_get_cmd_id (const struct rte_crypto_sym_xform *xform) {
@@ -71,6 +99,54 @@ static int partial_hash_sha1(uint8_t *data_in, uint8_t *data_out)return 0 ; } +static int partial_hash_sha224 (uint8_t *data_in,uint8_t *data_out) +{ +SHA256_CTX ctx; + +if (!SHA224_Init (&ctx)) +return -EFAULT ; +SHA256_Transform (&ctx, data_in); +rte_memcpy (data_out, &ctx, +SHA256_DIGEST_LENGTH ); +return 0 ; +} + +static int partial_hash_sha256 (uint8_t *data_in,uint8_t *data_out) +{ +SHA256_CTX ctx; + +if (!SHA256_Init (&ctx)) +return -EFAULT ; +SHA256_Transform (&ctx, data_in); +rte_memcpy (data_out, &ctx, +SHA256_DIGEST_LENGTH ); +return 0 ; +} + +static int partial_hash_sha384 (uint8_t *data_in,uint8_t *data_out) +{ +SHA512_CTX ctx; + +if (!SHA384_Init (&ctx)) +return -EFAULT ; +SHA512_Transform (&ctx, data_in); +rte_memcpy (data_out, &ctx, +SHA512_DIGEST_LENGTH ); +return 0 ; +} + +static int partial_hash_sha512 (uint8_t *data_in,uint8_t *data_out) +{ +SHA512_CTX ctx; + +if (!SHA512_Init (&ctx)) +return -EFAULT ; +SHA512_Transform (&ctx, data_in); +rte_memcpy (data_out, &ctx, +SHA512_DIGEST_LENGTH ); +return 0 ; +} +static int generate_partial_hash (struct ccp_session *sess) {
@@ -78,11 +154,13 @@ static int generate_partial_hash(struct ccp_session *sess)uint8_t opad[sess->auth.block_size];uint8_t *ipad_t, *opad_t;uint32_t *hash_value_be32, hash_temp32[8 ]; +uint64_t *hash_value_be64, hash_temp64[8 ];int i, count; opad_t = ipad_t = (uint8_t *)sess->auth.key; hash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute); + hash_value_be64 = (uint64_t *)((uint8_t *)sess->auth.pre_compute);/* considering key size is always equal to block size of algorithm */ for (i =0 ; i < sess->auth.block_size; i++) {
@@ -106,6 +184,66 @@ static int generate_partial_hash(struct ccp_session *sess)for (i =0 ; i < count; i++, hash_value_be32++) *hash_value_be32 = hash_temp32[count -1 - i];return 0 ; +case CCP_AUTH_ALGO_SHA224_HMAC : + count =SHA256_DIGEST_SIZE >>2 ; + +if (partial_hash_sha224 (ipad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; + + hash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha224 (opad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; +return 0 ; +case CCP_AUTH_ALGO_SHA256_HMAC : + count =SHA256_DIGEST_SIZE >>2 ; + +if (partial_hash_sha256 (ipad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; + + hash_value_be32 = (uint32_t *)((uint8_t *)sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha256 (opad, (uint8_t *)hash_temp32)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be32++) + *hash_value_be32 = hash_temp32[count -1 - i]; +return 0 ; +case CCP_AUTH_ALGO_SHA384_HMAC : + count =SHA512_DIGEST_SIZE >>3 ; + +if (partial_hash_sha384 (ipad, (uint8_t *)hash_temp64)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be64++) + *hash_value_be64 = hash_temp64[count -1 - i]; + + hash_value_be64 = (uint64_t *)((uint8_t *)sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha384 (opad, (uint8_t *)hash_temp64)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be64++) + *hash_value_be64 = hash_temp64[count -1 - i]; +return 0 ; +case CCP_AUTH_ALGO_SHA512_HMAC : + count =SHA512_DIGEST_SIZE >>3 ; + +if (partial_hash_sha512 (ipad, (uint8_t *)hash_temp64)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be64++) + *hash_value_be64 = hash_temp64[count -1 - i]; + + hash_value_be64 = (uint64_t *)((uint8_t *)sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha512 (opad, (uint8_t *)hash_temp64)) +return -1 ; +for (i =0 ; i < count; i++, hash_value_be64++) + *hash_value_be64 = hash_temp64[count -1 - i]; +return 0 ;default :CCP_LOG_ERR ("Invalid auth algo" );return -1 ;
@@ -321,6 +459,107 @@ ccp_configure_session_auth(struct ccp_session *sess,if (generate_partial_hash (sess))return -1 ;break ; +case RTE_CRYPTO_AUTH_SHA224 : + sess->auth.algo =CCP_AUTH_ALGO_SHA224 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_224 ; + sess->auth.ctx = (void *)ccp_sha224_init; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA224_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA224_HMAC : +if (auth_xform->key.length >SHA224_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA224_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_224 ; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA224_DIGEST_SIZE ; + sess->auth.block_size =SHA224_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 , sess->auth.ctx_len <<1 ); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ; +case RTE_CRYPTO_AUTH_SHA256 : + sess->auth.algo =CCP_AUTH_ALGO_SHA256 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_256 ; + sess->auth.ctx = (void *)ccp_sha256_init; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA256_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA256_HMAC : +if (auth_xform->key.length >SHA256_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA256_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_256 ; + sess->auth.ctx_len =CCP_SB_BYTES ; + sess->auth.offset =CCP_SB_BYTES -SHA256_DIGEST_SIZE ; + sess->auth.block_size =SHA256_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 , sess->auth.ctx_len <<1 ); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ; +case RTE_CRYPTO_AUTH_SHA384 : + sess->auth.algo =CCP_AUTH_ALGO_SHA384 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_384 ; + sess->auth.ctx = (void *)ccp_sha384_init; + sess->auth.ctx_len =CCP_SB_BYTES <<1 ; + sess->auth.offset = (CCP_SB_BYTES <<1 ) -SHA384_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA384_HMAC : +if (auth_xform->key.length >SHA384_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA384_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_384 ; + sess->auth.ctx_len =CCP_SB_BYTES <<1 ; + sess->auth.offset = (CCP_SB_BYTES <<1 ) -SHA384_DIGEST_SIZE ; + sess->auth.block_size =SHA384_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 , sess->auth.ctx_len <<1 ); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ; +case RTE_CRYPTO_AUTH_SHA512 : + sess->auth.algo =CCP_AUTH_ALGO_SHA512 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_512 ; + sess->auth.ctx = (void *)ccp_sha512_init; + sess->auth.ctx_len =CCP_SB_BYTES <<1 ; + sess->auth.offset = (CCP_SB_BYTES <<1 ) -SHA512_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA512_HMAC : +if (auth_xform->key.length >SHA512_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA512_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA_TYPE_512 ; + sess->auth.ctx_len =CCP_SB_BYTES <<1 ; + sess->auth.offset = (CCP_SB_BYTES <<1 ) -SHA512_DIGEST_SIZE ; + sess->auth.block_size =SHA512_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 , sess->auth.ctx_len <<1 ); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ; +case RTE_CRYPTO_AUTH_AES_CMAC : sess->auth.algo =CCP_AUTH_ALGO_AES_CMAC ; sess->auth.engine =CCP_ENGINE_AES ;
@@ -515,12 +754,32 @@ ccp_auth_slot(struct ccp_session *session)switch (session->auth.algo) {case CCP_AUTH_ALGO_SHA1 : +case CCP_AUTH_ALGO_SHA224 : +case CCP_AUTH_ALGO_SHA256 : +case CCP_AUTH_ALGO_SHA384 : +case CCP_AUTH_ALGO_SHA512 : count =3 ;/**< op + lsb passthrough cpy to/from*/ break ;case CCP_AUTH_ALGO_SHA1_HMAC : +case CCP_AUTH_ALGO_SHA224_HMAC : +case CCP_AUTH_ALGO_SHA256_HMAC : count =6 ;break ; +case CCP_AUTH_ALGO_SHA384_HMAC : +case CCP_AUTH_ALGO_SHA512_HMAC : + count =7 ; +/** +* 1. Load PHash1 = H(k ^ ipad); to LSB +* 2. generate IHash = H(hash on meassage with PHash1 +* as init values); +* 3. Retrieve IHash 2 slots for 384/512 +* 4. Load Phash2 = H(k ^ opad); to LSB +* 5. generate FHash = H(hash on Ihash with Phash2 +* as init value); +* 6. Retrieve HMAC output from LSB to host memory +*/ +break ;case CCP_AUTH_ALGO_AES_CMAC : count =4 ;/**
@@ -1477,13 +1736,24 @@ ccp_crypto_auth(struct rte_crypto_op *op,switch (session->auth.algo) {case CCP_AUTH_ALGO_SHA1 : +case CCP_AUTH_ALGO_SHA224 : +case CCP_AUTH_ALGO_SHA256 : +case CCP_AUTH_ALGO_SHA384 : +case CCP_AUTH_ALGO_SHA512 : result =ccp_perform_sha (op, cmd_q); b_info->desccnt +=3 ;break ;case CCP_AUTH_ALGO_SHA1_HMAC : +case CCP_AUTH_ALGO_SHA224_HMAC : +case CCP_AUTH_ALGO_SHA256_HMAC : result =ccp_perform_hmac (op, cmd_q); b_info->desccnt +=6 ;break ; +case CCP_AUTH_ALGO_SHA384_HMAC : +case CCP_AUTH_ALGO_SHA512_HMAC : + result =ccp_perform_hmac (op, cmd_q); + b_info->desccnt +=7 ; +break ;case CCP_AUTH_ALGO_AES_CMAC : result =ccp_perform_aes_cmac (op, cmd_q); b_info->desccnt +=4 ;
drivers/crypto/ccp/ccp_crypto.h +48 -0
60 lines not on this page · raw message
drivers/crypto/ccp/ccp_pmd_ops.c +168 -0
174 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v5 16/19 crypto/ccp: support sha3 family authentication algo
In reply to Ravi Kumar--- drivers/crypto/ccp/ccp_crypto.c | 667 +++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_crypto.h | 22 ++ drivers/crypto/ccp/ccp_pmd_ops.c | 168 +++++++++ lib/librte_cryptodev/rte_crypto_sym.h | 17 + 4 files changed, 873 insertions(+), 1 deletion(-)
drivers/crypto/ccp/ccp_crypto.c +666 -1
@@ -63,6 +63,74 @@ uint64_t ccp_sha512_init[SHA512_DIGEST_SIZE / sizeof(uint64_t)] = { SHA512_H1, SHA512_H0, }; +#if defined(_MSC_VER) +#define SHA3_CONST (x) x +#else +#define SHA3_CONST (x) x##L +#endif + +/** 'Words' here refers to uint64_t */ +#define SHA3_KECCAK_SPONGE_WORDS \ + (((1600) / 8) / sizeof(uint64_t)) +typedef struct sha3_context_ { +uint64_t saved; +/** +* The portion of the input message that we +* didn't consume yet +*/ +union { +uint64_t s[SHA3_KECCAK_SPONGE_WORDS ]; +/* Keccak's state */ +uint8_t sb[SHA3_KECCAK_SPONGE_WORDS *8 ]; +/**total 200 ctx size**/ + }; +unsigned int byteIndex; +/** +* 0..7--the next byte after the set one +* (starts from 0; 0--none are buffered) +*/ +unsigned int wordIndex; +/** +* 0..24--the next word to integrate input +* (starts from 0) +*/ +unsigned int capacityWords; +/** +* the double size of the hash output in +* words (e.g. 16 for Keccak 512) +*/ +}sha3_context ; + +#ifndef SHA3_ROTL64 +#define SHA3_ROTL64 (x, y) \ + (((x) << (y)) | ((x) >> ((sizeof(uint64_t)*8) - (y)))) +#endif + +static const uint64_t keccakf_rndc[24 ] = { +SHA3_CONST (0x0000000000000001UL ),SHA3_CONST (0x0000000000008082UL ), +SHA3_CONST (0x800000000000808aUL ),SHA3_CONST (0x8000000080008000UL ), +SHA3_CONST (0x000000000000808bUL ),SHA3_CONST (0x0000000080000001UL ), +SHA3_CONST (0x8000000080008081UL ),SHA3_CONST (0x8000000000008009UL ), +SHA3_CONST (0x000000000000008aUL ),SHA3_CONST (0x0000000000000088UL ), +SHA3_CONST (0x0000000080008009UL ),SHA3_CONST (0x000000008000000aUL ), +SHA3_CONST (0x000000008000808bUL ),SHA3_CONST (0x800000000000008bUL ), +SHA3_CONST (0x8000000000008089UL ),SHA3_CONST (0x8000000000008003UL ), +SHA3_CONST (0x8000000000008002UL ),SHA3_CONST (0x8000000000000080UL ), +SHA3_CONST (0x000000000000800aUL ),SHA3_CONST (0x800000008000000aUL ), +SHA3_CONST (0x8000000080008081UL ),SHA3_CONST (0x8000000000008080UL ), +SHA3_CONST (0x0000000080000001UL ),SHA3_CONST (0x8000000080008008UL ) +}; + +static const unsigned int keccakf_rotc[24 ] = { +1 ,3 ,6 ,10 ,15 ,21 ,28 ,36 ,45 ,55 ,2 ,14 ,27 ,41 ,56 ,8 ,25 ,43 ,62 , +18 ,39 ,61 ,20 ,44 +}; + +static const unsigned int keccakf_piln[24 ] = { +10 ,7 ,11 ,17 ,18 ,3 ,5 ,16 ,8 ,21 ,24 ,4 ,15 ,23 ,19 ,13 ,12 ,2 ,20 , +14 ,22 ,9 ,6 ,1 +}; +static enum ccp_cmd_order ccp_get_cmd_id (const struct rte_crypto_sym_xform *xform) {
@@ -147,6 +215,223 @@ static int partial_hash_sha512(uint8_t *data_in, uint8_t *data_out)return 0 ; } +static void +keccakf (uint64_t s[25 ]) +{ +int i, j, round; +uint64_t t, bc[5 ]; +#define KECCAK_ROUNDS 24 + +for (round =0 ; round <KECCAK_ROUNDS ; round++) { + +/* Theta */ +for (i =0 ; i <5 ; i++) + bc[i] = s[i] ^ s[i +5 ] ^ s[i +10 ] ^ s[i +15 ] ^ + s[i +20 ]; + +for (i =0 ; i <5 ; i++) { + t = bc[(i +4 ) %5 ] ^SHA3_ROTL64 (bc[(i +1 ) %5 ],1 ); +for (j =0 ; j <25 ; j +=5 ) + s[j + i] ^= t; + } + +/* Rho Pi */ + t = s[1 ]; +for (i =0 ; i <24 ; i++) { + j = keccakf_piln[i]; + bc[0 ] = s[j]; + s[j] =SHA3_ROTL64 (t, keccakf_rotc[i]); + t = bc[0 ]; + } + +/* Chi */ +for (j =0 ; j <25 ; j +=5 ) { +for (i =0 ; i <5 ; i++) + bc[i] = s[j + i]; +for (i =0 ; i <5 ; i++) + s[j + i] ^= (~bc[(i +1 ) %5 ]) & + bc[(i +2 ) %5 ]; + } + +/* Iota */ + s[0 ] ^= keccakf_rndc[round]; + } +} + +static void +sha3_Init224 (void *priv) +{ +sha3_context *ctx = (sha3_context *) priv; + +memset (ctx,0 ,sizeof (*ctx)); + ctx->capacityWords =2 *224 / (8 *sizeof (uint64_t )); +} + +static void +sha3_Init256 (void *priv) +{ +sha3_context *ctx = (sha3_context *) priv; + +memset (ctx,0 ,sizeof (*ctx)); + ctx->capacityWords =2 *256 / (8 *sizeof (uint64_t )); +} + +static void +sha3_Init384 (void *priv) +{ +sha3_context *ctx = (sha3_context *) priv; + +memset (ctx,0 ,sizeof (*ctx)); + ctx->capacityWords =2 *384 / (8 *sizeof (uint64_t )); +} + +static void +sha3_Init512 (void *priv) +{ +sha3_context *ctx = (sha3_context *) priv; + +memset (ctx,0 ,sizeof (*ctx)); + ctx->capacityWords =2 *512 / (8 *sizeof (uint64_t )); +} + + +/* This is simply the 'update' with the padding block. +* The padding block is 0x01 || 0x00* || 0x80. First 0x01 and last 0x80 +* bytes are always present, but they can be the same byte. +*/ +static void +sha3_Update (void *priv,void const *bufIn,size_t len) +{ +sha3_context *ctx = (sha3_context *) priv; +unsigned int old_tail = (8 - ctx->byteIndex) &7 ; +size_t words; +unsigned int tail; +size_t i; +const uint8_t *buf = bufIn; + +if (len < old_tail) { +while (len--) + ctx->saved |= (uint64_t ) (*(buf++)) << + ((ctx->byteIndex++) *8 ); +return ; + } + +if (old_tail) { + len -= old_tail; +while (old_tail--) + ctx->saved |= (uint64_t ) (*(buf++)) << + ((ctx->byteIndex++) *8 ); + + ctx->s[ctx->wordIndex] ^= ctx->saved; + ctx->byteIndex =0 ; + ctx->saved =0 ; +if (++ctx->wordIndex == + (SHA3_KECCAK_SPONGE_WORDS - ctx->capacityWords)) { +keccakf (ctx->s); + ctx->wordIndex =0 ; + } + } + + words = len /sizeof (uint64_t ); + tail = len - words *sizeof (uint64_t ); + +for (i =0 ; i < words; i++, buf +=sizeof (uint64_t )) { +const uint64_t t = (uint64_t ) (buf[0 ]) | + ((uint64_t ) (buf[1 ]) <<8 *1 ) | + ((uint64_t ) (buf[2 ]) <<8 *2 ) | + ((uint64_t ) (buf[3 ]) <<8 *3 ) | + ((uint64_t ) (buf[4 ]) <<8 *4 ) | + ((uint64_t ) (buf[5 ]) <<8 *5 ) | + ((uint64_t ) (buf[6 ]) <<8 *6 ) | + ((uint64_t ) (buf[7 ]) <<8 *7 ); + ctx->s[ctx->wordIndex] ^= t; +if (++ctx->wordIndex == + (SHA3_KECCAK_SPONGE_WORDS - ctx->capacityWords)) { +keccakf (ctx->s); + ctx->wordIndex =0 ; + } + } + +while (tail--) + ctx->saved |= (uint64_t ) (*(buf++)) << ((ctx->byteIndex++) *8 ); +} + +int partial_hash_sha3_224 (uint8_t *data_in,uint8_t *data_out) +{ +sha3_context *ctx; +int i; + + ctx =rte_zmalloc ("sha3-ctx" ,sizeof (sha3_context),0 ); +if (!ctx) { +CCP_LOG_ERR ("sha3-ctx creation failed" ); +return -ENOMEM ; + } +sha3_Init224 (ctx); +sha3_Update (ctx, data_in,SHA3_224_BLOCK_SIZE ); +for (i =0 ; i <CCP_SHA3_CTX_SIZE ; i++, data_out++) + *data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i -1 ]; +rte_free (ctx); + +return 0 ; +} + +int partial_hash_sha3_256 (uint8_t *data_in,uint8_t *data_out) +{ +sha3_context *ctx; +int i; + + ctx =rte_zmalloc ("sha3-ctx" ,sizeof (sha3_context),0 ); +if (!ctx) { +CCP_LOG_ERR ("sha3-ctx creation failed" ); +return -ENOMEM ; + } +sha3_Init256 (ctx); +sha3_Update (ctx, data_in,SHA3_256_BLOCK_SIZE ); +for (i =0 ; i <CCP_SHA3_CTX_SIZE ; i++, data_out++) + *data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i -1 ]; +rte_free (ctx); + +return 0 ; +} + +int partial_hash_sha3_384 (uint8_t *data_in,uint8_t *data_out) +{ +sha3_context *ctx; +int i; + + ctx =rte_zmalloc ("sha3-ctx" ,sizeof (sha3_context),0 ); +if (!ctx) { +CCP_LOG_ERR ("sha3-ctx creation failed" ); +return -ENOMEM ; + } +sha3_Init384 (ctx); +sha3_Update (ctx, data_in,SHA3_384_BLOCK_SIZE ); +for (i =0 ; i <CCP_SHA3_CTX_SIZE ; i++, data_out++) + *data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i -1 ]; +rte_free (ctx); + +return 0 ; +} + +int partial_hash_sha3_512 (uint8_t *data_in,uint8_t *data_out) +{ +sha3_context *ctx; +int i; + + ctx =rte_zmalloc ("sha3-ctx" ,sizeof (sha3_context),0 ); +if (!ctx) { +CCP_LOG_ERR ("sha3-ctx creation failed" ); +return -ENOMEM ; + } +sha3_Init512 (ctx); +sha3_Update (ctx, data_in,SHA3_512_BLOCK_SIZE ); +for (i =0 ; i <CCP_SHA3_CTX_SIZE ; i++, data_out++) + *data_out = ctx->sb[CCP_SHA3_CTX_SIZE - i -1 ]; +rte_free (ctx); + +return 0 ; +} +static int generate_partial_hash (struct ccp_session *sess) {
@@ -156,6 +441,7 @@ static int generate_partial_hash(struct ccp_session *sess)uint32_t *hash_value_be32, hash_temp32[8 ];uint64_t *hash_value_be64, hash_temp64[8 ];int i, count; +uint8_t *hash_value_sha3; opad_t = ipad_t = (uint8_t *)sess->auth.key;
@@ -199,6 +485,16 @@ static int generate_partial_hash(struct ccp_session *sess)for (i =0 ; i < count; i++, hash_value_be32++) *hash_value_be32 = hash_temp32[count -1 - i];return 0 ; +case CCP_AUTH_ALGO_SHA3_224_HMAC : + hash_value_sha3 = sess->auth.pre_compute; +if (partial_hash_sha3_224 (ipad, hash_value_sha3)) +return -1 ; + + hash_value_sha3 = (uint8_t *)(sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha3_224 (opad, hash_value_sha3)) +return -1 ; +return 0 ;case CCP_AUTH_ALGO_SHA256_HMAC : count =SHA256_DIGEST_SIZE >>2 ;
@@ -214,6 +510,16 @@ static int generate_partial_hash(struct ccp_session *sess)for (i =0 ; i < count; i++, hash_value_be32++) *hash_value_be32 = hash_temp32[count -1 - i];return 0 ; +case CCP_AUTH_ALGO_SHA3_256_HMAC : + hash_value_sha3 = sess->auth.pre_compute; +if (partial_hash_sha3_256 (ipad, hash_value_sha3)) +return -1 ; + + hash_value_sha3 = (uint8_t *)(sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha3_256 (opad, hash_value_sha3)) +return -1 ; +return 0 ;case CCP_AUTH_ALGO_SHA384_HMAC : count =SHA512_DIGEST_SIZE >>3 ;
@@ -229,6 +535,16 @@ static int generate_partial_hash(struct ccp_session *sess)for (i =0 ; i < count; i++, hash_value_be64++) *hash_value_be64 = hash_temp64[count -1 - i];return 0 ; +case CCP_AUTH_ALGO_SHA3_384_HMAC : + hash_value_sha3 = sess->auth.pre_compute; +if (partial_hash_sha3_384 (ipad, hash_value_sha3)) +return -1 ; + + hash_value_sha3 = (uint8_t *)(sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha3_384 (opad, hash_value_sha3)) +return -1 ; +return 0 ;case CCP_AUTH_ALGO_SHA512_HMAC : count =SHA512_DIGEST_SIZE >>3 ;
@@ -244,6 +560,16 @@ static int generate_partial_hash(struct ccp_session *sess)for (i =0 ; i < count; i++, hash_value_be64++) *hash_value_be64 = hash_temp64[count -1 - i];return 0 ; +case CCP_AUTH_ALGO_SHA3_512_HMAC : + hash_value_sha3 = sess->auth.pre_compute; +if (partial_hash_sha3_512 (ipad, hash_value_sha3)) +return -1 ; + + hash_value_sha3 = (uint8_t *)(sess->auth.pre_compute + + sess->auth.ctx_len); +if (partial_hash_sha3_512 (opad, hash_value_sha3)) +return -1 ; +return 0 ;default :CCP_LOG_ERR ("Invalid auth algo" );return -1 ;
@@ -484,6 +810,30 @@ ccp_configure_session_auth(struct ccp_session *sess,if (generate_partial_hash (sess))return -1 ;break ; +case RTE_CRYPTO_AUTH_SHA3_224 : + sess->auth.algo =CCP_AUTH_ALGO_SHA3_224 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_224 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA224_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA3_224_HMAC : +if (auth_xform->key.length >SHA3_224_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA3_224_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_224 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA224_DIGEST_SIZE ; + sess->auth.block_size =SHA3_224_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 ,2 * sess->auth.ctx_len); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ;case RTE_CRYPTO_AUTH_SHA256 : sess->auth.algo =CCP_AUTH_ALGO_SHA256 ; sess->auth.engine =CCP_ENGINE_SHA ;
@@ -509,6 +859,30 @@ ccp_configure_session_auth(struct ccp_session *sess,if (generate_partial_hash (sess))return -1 ;break ; +case RTE_CRYPTO_AUTH_SHA3_256 : + sess->auth.algo =CCP_AUTH_ALGO_SHA3_256 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_256 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA256_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA3_256_HMAC : +if (auth_xform->key.length >SHA3_256_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA3_256_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_256 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA256_DIGEST_SIZE ; + sess->auth.block_size =SHA3_256_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 ,2 * sess->auth.ctx_len); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ;case RTE_CRYPTO_AUTH_SHA384 : sess->auth.algo =CCP_AUTH_ALGO_SHA384 ; sess->auth.engine =CCP_ENGINE_SHA ;
@@ -534,6 +908,30 @@ ccp_configure_session_auth(struct ccp_session *sess,if (generate_partial_hash (sess))return -1 ;break ; +case RTE_CRYPTO_AUTH_SHA3_384 : + sess->auth.algo =CCP_AUTH_ALGO_SHA3_384 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_384 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA384_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA3_384_HMAC : +if (auth_xform->key.length >SHA3_384_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA3_384_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_384 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA384_DIGEST_SIZE ; + sess->auth.block_size =SHA3_384_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 ,2 * sess->auth.ctx_len); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ;case RTE_CRYPTO_AUTH_SHA512 : sess->auth.algo =CCP_AUTH_ALGO_SHA512 ; sess->auth.engine =CCP_ENGINE_SHA ;
@@ -559,7 +957,30 @@ ccp_configure_session_auth(struct ccp_session *sess,if (generate_partial_hash (sess))return -1 ;break ; - +case RTE_CRYPTO_AUTH_SHA3_512 : + sess->auth.algo =CCP_AUTH_ALGO_SHA3_512 ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_512 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA512_DIGEST_SIZE ; +break ; +case RTE_CRYPTO_AUTH_SHA3_512_HMAC : +if (auth_xform->key.length >SHA3_512_BLOCK_SIZE ) +return -1 ; + sess->auth.algo =CCP_AUTH_ALGO_SHA3_512_HMAC ; + sess->auth.engine =CCP_ENGINE_SHA ; + sess->auth.ut.sha_type =CCP_SHA3_TYPE_512 ; + sess->auth.ctx_len =CCP_SHA3_CTX_SIZE ; + sess->auth.offset =CCP_SHA3_CTX_SIZE -SHA512_DIGEST_SIZE ; + sess->auth.block_size =SHA3_512_BLOCK_SIZE ; + sess->auth.key_length = auth_xform->key.length; +memset (sess->auth.key,0 , sess->auth.block_size); +memset (sess->auth.pre_compute,0 ,2 * sess->auth.ctx_len); +rte_memcpy (sess->auth.key, auth_xform->key.data, + auth_xform->key.length); +if (generate_partial_hash (sess)) +return -1 ; +break ;case RTE_CRYPTO_AUTH_AES_CMAC : sess->auth.algo =CCP_AUTH_ALGO_AES_CMAC ; sess->auth.engine =CCP_ENGINE_AES ;
@@ -780,6 +1201,26 @@ ccp_auth_slot(struct ccp_session *session)* 6. Retrieve HMAC output from LSB to host memory */ break ; +case CCP_AUTH_ALGO_SHA3_224 : +case CCP_AUTH_ALGO_SHA3_256 : +case CCP_AUTH_ALGO_SHA3_384 : +case CCP_AUTH_ALGO_SHA3_512 : + count =1 ; +/**< only op ctx and dst in host memory*/ +break ; +case CCP_AUTH_ALGO_SHA3_224_HMAC : +case CCP_AUTH_ALGO_SHA3_256_HMAC : + count =3 ; +break ; +case CCP_AUTH_ALGO_SHA3_384_HMAC : +case CCP_AUTH_ALGO_SHA3_512_HMAC : + count =4 ; +/** +* 1. Op to Perform Ihash +* 2. Retrieve result from LSB to host memory +* 3. Perform final hash +*/ +break ;case CCP_AUTH_ALGO_AES_CMAC : count =4 ;/**
@@ -1170,6 +1611,213 @@ ccp_perform_sha(struct rte_crypto_op *op, }static int +ccp_perform_sha3_hmac (struct rte_crypto_op *op, +struct ccp_queue *cmd_q) +{ +struct ccp_session *session; +struct ccp_passthru pst; +union ccp_function function; +struct ccp_desc *desc; +uint8_t *append_ptr; +uint32_t tail; +phys_addr_t src_addr, dest_addr, ctx_paddr, dest_addr_t; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->auth.data.offset); + append_ptr = (uint8_t *)rte_pktmbuf_append (op->sym->m_src, + session->auth.ctx_len); +if (!append_ptr) { +CCP_LOG_ERR ("CCP MBUF append failed\n" ); +return -1 ; + } + dest_addr = (phys_addr_t )rte_mem_virt2phy ((void *)append_ptr); + dest_addr_t = dest_addr + (session->auth.ctx_len /2 ); + ctx_paddr = (phys_addr_t )rte_mem_virt2phy ((void + *)session->auth.pre_compute); + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +/*desc1 for SHA3-Ihash operation */ +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; +CCP_CMD_LEN (desc) = op->sym->auth.data.length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = (cmd_q->sb_sha *CCP_SB_BYTES ); +CCP_CMD_DST_HI (desc) =0 ; +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SB ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )ctx_paddr); +CCP_CMD_KEY_HI (desc) =high32_value (ctx_paddr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + +/* Intermediate Hash value retrieve */ +if ((session->auth.ut.sha_type ==CCP_SHA3_TYPE_384 ) || + (session->auth.ut.sha_type ==CCP_SHA3_TYPE_512 )) { + + pst.src_addr = + (phys_addr_t)((cmd_q->sb_sha +1 ) *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t; + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t +CCP_SB_BYTES ; + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + + }else { + pst.src_addr = (phys_addr_t)(cmd_q->sb_sha *CCP_SB_BYTES ); + pst.dest_addr = dest_addr_t; + pst.len =CCP_SB_BYTES ; + pst.dir =0 ; + pst.bit_mod =CCP_PASSTHRU_BITWISE_NOOP ; + pst.byte_swap =CCP_PASSTHRU_BYTESWAP_256BIT ; +ccp_perform_passthru (&pst, cmd_q); + } + +/**sha engine command descriptor for FinalHash*/ + ctx_paddr +=CCP_SHA3_CTX_SIZE ; + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +if (session->auth.ut.sha_type ==CCP_SHA3_TYPE_224 ) { + dest_addr_t += (CCP_SB_BYTES -SHA224_DIGEST_SIZE ); +CCP_CMD_LEN (desc) =SHA224_DIGEST_SIZE ; + }else if (session->auth.ut.sha_type ==CCP_SHA3_TYPE_256 ) { +CCP_CMD_LEN (desc) =SHA256_DIGEST_SIZE ; + }else if (session->auth.ut.sha_type ==CCP_SHA3_TYPE_384 ) { + dest_addr_t += (2 *CCP_SB_BYTES -SHA384_DIGEST_SIZE ); +CCP_CMD_LEN (desc) =SHA384_DIGEST_SIZE ; + }else { +CCP_CMD_LEN (desc) =SHA512_DIGEST_SIZE ; + } + +CCP_CMD_SRC_LO (desc) = ((uint32_t )dest_addr_t); +CCP_CMD_SRC_HI (desc) =high32_value (dest_addr_t); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = (uint32_t )dest_addr; +CCP_CMD_DST_HI (desc) =high32_value (dest_addr); +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )ctx_paddr); +CCP_CMD_KEY_HI (desc) =high32_value (ctx_paddr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} + +static int +ccp_perform_sha3 (struct rte_crypto_op *op, +struct ccp_queue *cmd_q) +{ +struct ccp_session *session; +union ccp_function function; +struct ccp_desc *desc; +uint8_t *ctx_addr, *append_ptr; +uint32_t tail; +phys_addr_t src_addr, dest_addr, ctx_paddr; + + session = (struct ccp_session *)get_session_private_data ( + op->sym->session, + ccp_cryptodev_driver_id); + + src_addr =rte_pktmbuf_mtophys_offset (op->sym->m_src, + op->sym->auth.data.offset); + append_ptr = (uint8_t *)rte_pktmbuf_append (op->sym->m_src, + session->auth.ctx_len); +if (!append_ptr) { +CCP_LOG_ERR ("CCP MBUF append failed\n" ); +return -1 ; + } + dest_addr = (phys_addr_t )rte_mem_virt2phy ((void *)append_ptr); + ctx_addr = session->auth.sha3_ctx; + ctx_paddr = (phys_addr_t )rte_mem_virt2phy ((void *)ctx_addr); + + desc = &cmd_q->qbase_desc[cmd_q->qidx]; +memset (desc,0 ,Q_DESC_SIZE ); + +/* prepare desc for SHA3 operation */ +CCP_CMD_ENGINE (desc) =CCP_ENGINE_SHA ; +CCP_CMD_INIT (desc) =1 ; +CCP_CMD_EOM (desc) =1 ; + + function.raw =0 ; +CCP_SHA_TYPE (&function) = session->auth.ut.sha_type; +CCP_CMD_FUNCTION (desc) = function.raw; + +CCP_CMD_LEN (desc) = op->sym->auth.data.length; + +CCP_CMD_SRC_LO (desc) = ((uint32_t )src_addr); +CCP_CMD_SRC_HI (desc) =high32_value (src_addr); +CCP_CMD_SRC_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_DST_LO (desc) = ((uint32_t )dest_addr); +CCP_CMD_DST_HI (desc) =high32_value (dest_addr); +CCP_CMD_DST_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + +CCP_CMD_KEY_LO (desc) = ((uint32_t )ctx_paddr); +CCP_CMD_KEY_HI (desc) =high32_value (ctx_paddr); +CCP_CMD_KEY_MEM (desc) =CCP_MEMTYPE_SYSTEM ; + + cmd_q->qidx = (cmd_q->qidx +1 ) %COMMANDS_PER_QUEUE ; + +rte_wmb (); + + tail = (uint32_t )(cmd_q->qbase_phys_addr + cmd_q->qidx *Q_DESC_SIZE ); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_TAIL_LO_BASE , tail); +CCP_WRITE_REG (cmd_q->reg_base,CMD_Q_CONTROL_BASE , + cmd_q->qcontrol |CMD_Q_RUN ); + + op->status =RTE_CRYPTO_OP_STATUS_NOT_PROCESSED ; +return 0 ; +} + +static int ccp_perform_aes_cmac (struct rte_crypto_op *op,struct ccp_queue *cmd_q) {
@@ -1754,6 +2402,23 @@ ccp_crypto_auth(struct rte_crypto_op *op, result =ccp_perform_hmac (op, cmd_q); b_info->desccnt +=7 ;break ; +case CCP_AUTH_ALGO_SHA3_224 : +case CCP_AUTH_ALGO_SHA3_256 : +case CCP_AUTH_ALGO_SHA3_384 : +case CCP_AUTH_ALGO_SHA3_512 : + result =ccp_perform_sha3 (op, cmd_q); + b_info->desccnt +=1 ; +break ; +case CCP_AUTH_ALGO_SHA3_224_HMAC : +case CCP_AUTH_ALGO_SHA3_256_HMAC : + result =ccp_perform_sha3_hmac (op, cmd_q); + b_info->desccnt +=3 ; +break ; +case CCP_AUTH_ALGO_SHA3_384_HMAC : +case CCP_AUTH_ALGO_SHA3_512_HMAC : + result =ccp_perform_sha3_hmac (op, cmd_q); + b_info->desccnt +=4 ; +break ;case CCP_AUTH_ALGO_AES_CMAC : result =ccp_perform_aes_cmac (op, cmd_q); b_info->desccnt +=4 ;
drivers/crypto/ccp/ccp_crypto.h +22 -0
@@ -54,15 +54,19 @@#define SHA224_DIGEST_SIZE 28#define SHA224_BLOCK_SIZE 64 +#define SHA3_224_BLOCK_SIZE 144#define SHA256_DIGEST_SIZE 32#define SHA256_BLOCK_SIZE 64 +#define SHA3_256_BLOCK_SIZE 136#define SHA384_DIGEST_SIZE 48#define SHA384_BLOCK_SIZE 128 +#define SHA3_384_BLOCK_SIZE 104#define SHA512_DIGEST_SIZE 64#define SHA512_BLOCK_SIZE 128 +#define SHA3_512_BLOCK_SIZE 72/* SHA LSB intialiazation values */
@@ -360,4 +364,22 @@ int process_ops_to_dequeue(struct ccp_qp *qp,struct rte_crypto_op **op, uint16_t nb_ops); + +/** +* Apis for SHA3 partial hash generation +* @param data_in buffer pointer on which phash is applied +* @param data_out phash result in ccp be format is written +*/ +int partial_hash_sha3_224 (uint8_t *data_in, +uint8_t *data_out); + +int partial_hash_sha3_256 (uint8_t *data_in, +uint8_t *data_out); + +int partial_hash_sha3_384 (uint8_t *data_in, +uint8_t *data_out); + +int partial_hash_sha3_512 (uint8_t *data_in, +uint8_t *data_out); +#endif /* _CCP_CRYPTO_H_ */
drivers/crypto/ccp/ccp_pmd_ops.c +168 -0
192 lines not on this page · raw message
lib/librte_cryptodev/rte_crypto_sym.h +17 -0
@@ -245,6 +245,23 @@ enum rte_crypto_auth_algorithm {RTE_CRYPTO_AUTH_ZUC_EIA3 ,/**< ZUC algorithm in EIA3 mode */ +RTE_CRYPTO_AUTH_SHA3_224 , +/**< 224 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_224_HMAC , +/**< HMAC using 224 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_256 , +/**< 256 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_256_HMAC , +/**< HMAC using 256 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_384 , +/**< 384 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_384_HMAC , +/**< HMAC using 384 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_512 , +/**< 512 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_SHA3_512_HMAC , +/**< HMAC using 512 bit SHA3 algorithm. */ +RTE_CRYPTO_AUTH_LIST_END };
Signature · 1 line
2.7.4
PATCH v5 17/19 crypto/ccp: support cpu based md5 and sha2 family authentication algo
In reply to Ravi Kumar--- config/common_base | 1 + drivers/crypto/ccp/ccp_crypto.c | 282 ++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_crypto.h | 5 +- drivers/crypto/ccp/ccp_pmd_ops.c | 23 +++ drivers/crypto/ccp/ccp_pmd_private.h | 10 ++ 5 files changed, 316 insertions(+), 5 deletions(-)
config/common_base +1 -0
@@ -532,6 +532,7 @@ CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y # Compile PMD for AMD CCP crypto device # CONFIG_RTE_LIBRTE_PMD_CCP=n +CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=n # # Compile PMD for Marvell Crypto device
drivers/crypto/ccp/ccp_crypto.c +278 -4
467 lines not on this page · raw message
drivers/crypto/ccp/ccp_crypto.h +4 -1
@@ -68,6 +68,9 @@#define SHA512_BLOCK_SIZE 128#define SHA3_512_BLOCK_SIZE 72 +/* Maximum length for digest */ +#define DIGEST_LENGTH_MAX 64 +/* SHA LSB intialiazation values */ #define SHA1_H0 0x67452301UL
@@ -346,7 +349,7 @@ int ccp_compute_slot_count(struct ccp_session *session);* @param nb_ops No. of ops to be submitted * @return 0 on success otherwise -1 */ -int process_ops_to_enqueue(const struct ccp_qp *qp, +int process_ops_to_enqueue(struct ccp_qp *qp, struct rte_crypto_op **op, struct ccp_queue *cmd_q, uint16_t nb_ops,
drivers/crypto/ccp/ccp_pmd_ops.c +23 -0
@@ -13,6 +13,29 @@#include "ccp_crypto.h" static const struct rte_cryptodev_capabilities ccp_pmd_capabilities[] = { +#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH + {/* MD5 HMAC */ + .op =RTE_CRYPTO_OP_TYPE_SYMMETRIC , + {.sym = { + .xform_type =RTE_CRYPTO_SYM_XFORM_AUTH , + {.auth = { + .algo =RTE_CRYPTO_AUTH_MD5_HMAC , + .block_size =64 , + .key_size = { + .min =1 , + .max =64 , + .increment =1 + }, + .digest_size = { + .min =16 , + .max =16 , + .increment =0 + }, + .aad_size = {0 } + }, } + }, } + }, +#endif {/* SHA1 */ .op =RTE_CRYPTO_OP_TYPE_SYMMETRIC , {.sym = {
drivers/crypto/ccp/ccp_pmd_private.h +10 -0
@@ -6,6 +6,7 @@#define _CCP_PMD_PRIVATE_H_#include <rte_cryptodev.h> +#include "ccp_crypto.h" #define CRYPTODEV_NAME_CCP_PMD crypto_ccp
@@ -61,6 +62,10 @@ struct ccp_batch_info {phys_addr_t lsb_buf_phys;/**< LSB intermediate buf for passthru */ int lsb_buf_idx; +#ifdef RTE_LIBRTE_PMD_CCP_CPU_AUTH +uint16_t auth_ctr; +/**< auth only ops batch */ +#endif } __rte_cache_aligned;/**< CCP crypto queue pair */
@@ -81,6 +86,11 @@ struct ccp_qp {/**< Store ops pulled out of queue */ struct rte_cryptodev *dev;/**< rte crypto device to which this qp belongs */ +uint8_t temp_digest[DIGEST_LENGTH_MAX ]; +/**< Buffer used to store the digest generated +* by the driver when verifying a digest provided +* by the user (using authentication verify operation) +*/ } __rte_cache_aligned;
Signature · 1 line
2.7.4
Re: [PATCH v5 17/19] crypto/ccp: support cpu based md5 and sha2 family authentication algo
Hi,
I am doing some late comments because I have a quick look when trying to pull next-crypto in master branch.
Unfortunately, it doesn't met the basic quality criterias.
19/03/2018 13:23, Ravi Kumar:
Quoted 8 lines
Signed-off-by Ravi Kumar <[email protected]>--- config/common_base | 1 + drivers/crypto/ccp/ccp_crypto.c | 282 ++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_crypto.h | 5 +- drivers/crypto/ccp/ccp_pmd_ops.c | 23 +++ drivers/crypto/ccp/ccp_pmd_private.h | 10 ++ 5 files changed, 316 insertions(+), 5 deletions(-)
[...]
Quoted 1 line
+CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=n
Why introducing a compile-time option?
Can it be a run-time option of the device?
We must not add compile-time device option if not well justified.
Talking about justification, there is 0 explanation in the commit messages. But there are some in next-crypto tree. Where do they come from?
Re: [PATCH v5 17/19] crypto/ccp: support cpu based md5 and sha2 family authentication algo
Quoted 16 lines
Hi,
I am doing some late comments because I have a quick look when trying to pull next-crypto in master branch. Unfortunately, it doesn't met the basic quality criterias.
19/03/2018 13:23, Ravi Kumar:
Quoted 8 lines
Signed-off-by Ravi Kumar <[email protected]>--- config/common_base | 1 + drivers/crypto/ccp/ccp_crypto.c | 282 ++++++++++++++++++++++++++++++++++- drivers/crypto/ccp/ccp_crypto.h | 5 +- drivers/crypto/ccp/ccp_pmd_ops.c | 23 +++ drivers/crypto/ccp/ccp_pmd_private.h | 10 ++ 5 files changed, 316 insertions(+), 5 deletions(-)[...]
Quoted 9 lines
Quoted 1 line
+CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=n
Why introducing a compile-time option?
Can it be a run-time option of the device?
We must not add compile-time device option if not well justified.Talking about justification, there is 0 explanation in the commit messages. But there are some in next-crypto tree. Where do they come from?
Hi Thomas,
The detailed commit messages were missing from the earlier patches. Later after the patch were applied to dpdk-next-crypto, Pablo requested detailed commit messages for patches and just not to populate the mail-chain unnecessarily, the messages were later squashed in the commits offline.
Here is the explanation of the patch:
By default, all the crypto operations (cipher + auth) are offloaded to CCP engines. When user enables CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y, the auth operations are not offloaded to CCP and rather performed over CPU. We kept this feature as a compile time option in order to let user decide whether to run auth operations on CCP or CPU as some of the auth operations performs faster on CPU as compared to their performance on CCP.
Regards,
Ravi
Re: [PATCH v5 17/19] crypto/ccp: support cpu based md5 and sha2 family authentication algo
23/04/2018 08:41, Kumar, Ravi1:
Quoted 5 lines
Quoted 5 lines
Quoted 1 line
+CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=n
Why introducing a compile-time option?
Can it be a run-time option of the device?
We must not add compile-time device option if not well justified.
[...]
Quoted 1 line
By default, all the crypto operations (cipher + auth) are offloaded to CCP engines. When user enables
CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y, the auth operations are not offloaded to CCP and rather performed over CPU. We kept this feature as a compile time option in order to let user decide whether to run auth operations on CCP or CPU as some of the auth operations performs faster on CPU as compared to their performance on CCP.
No, you do not let the user decide.
The compilation options are for the packager to decide.
The user can rely on pre-compiled packages and use only runtime options. That's why we forbid compile-time options for such features.
Re: [PATCH v5 17/19] crypto/ccp: support cpu based md5 and sha2 family authentication algo
Hi Ravi,
Quoted 23 lines
-----Original Message-----
From: Thomas Monjalon [mailto:[email protected]]
Sent: Monday, April 23, 2018 9:06 AM
To: Kumar, Ravi1 <[email protected]>
Cc: De Lara Guarch, Pablo <[email protected]>; [email protected]; [email protected]
Subject: Re: [dpdk-dev] [PATCH v5 17/19]crypto/ccp: support cpu based md5 and sha2 family authentication algo23/04/2018 08:41, Kumar, Ravi1:
Quoted 5 lines
Quoted 5 lines
Quoted 1 line
+CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=n
Why introducing a compile-time option?
Can it be a run-time option of the device?
We must not add compile-time device option if not well justified.[...]
Quoted 1 line
By default, all the crypto operations (cipher + auth) are offloaded to CCP
engines. When user enables
CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y, the auth operations are not offloaded to CCP and rather performed over CPU. We kept this feature as a compile time option in order to let user decide whether to run auth operations on CCP or CPU as some of the auth operations performs faster on CPU as compared to their performance on CCP.
Quoted 5 lines
No, you do not let the user decide.
The compilation options are for the packager to decide.
The user can rely on pre-compiled packages and use only runtime options. That's why we forbid compile-time options for such features.
Could you send a patch to remove this compile-time option and pass it as an option for the vdev? Look at how the crypto scheduler accepts parameters from "rte_vdev_init" or --vdev, in scheduler_pmd.c.
Thanks!
Pablo
Re: [PATCH v5 17/19] crypto/ccp: support cpu based md5 and sha2 family authentication algo
Quoted 32 lines
Hi Ravi,
Quoted 24 lines
-----Original Message-----
From: Thomas Monjalon [mailto:[email protected]]
Sent: Monday, April 23, 2018 9:06 AM
To: Kumar, Ravi1 <[email protected]>
Cc: De Lara Guarch, Pablo <[email protected]>; [email protected]; [email protected]
Subject: Re: [dpdk-dev] [PATCH v5 17/19]crypto/ccp: support cpu based md5 and sha2 family authentication algo23/04/2018 08:41, Kumar, Ravi1:
Quoted 5 lines
Quoted 5 lines
Quoted 1 line
+CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=n
Why introducing a compile-time option?
Can it be a run-time option of the device?
We must not add compile-time device option if not well justified.[...]
Quoted 2 lines
By default, all the crypto operations (cipher + auth) are offloaded to CCP
engines. When user enables
CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y, the auth operations are not offloaded to CCP and rather performed over CPU. We kept this feature as a compile time option in order to let user decide whether to run auth operations on CCP or CPU as some of the auth operations performs faster on CPU as compared to their performance on CCP.Quoted 5 lines
No, you do not let the user decide.
The compilation options are for the packager to decide.
The user can rely on pre-compiled packages and use only runtime options. That's why we forbid compile-time options for such features.
Quoted 6 lines
Could you send a patch to remove this compile-time option and pass it as an option for the vdev? Look at how the crypto scheduler accepts parameters from "
rte_vdev_init" or --vdev, inscheduler_pmd.c.Thanks!
Pablo
Hi Pablo,
Yes, we are working on it.
Regards,
Ravi
Re: [PATCH v5 17/19] crypto/ccp: support cpu based md5 and sha2 family authentication algo
In reply to De Lara Guarch, PabloQuoted 32 lines
Hi Ravi,
Quoted 24 lines
-----Original Message-----
From: Thomas Monjalon [mailto:[email protected]]
Sent: Monday, April 23, 2018 9:06 AM
To: Kumar, Ravi1 <[email protected]>
Cc: De Lara Guarch, Pablo <[email protected]>; [email protected]; [email protected]
Subject: Re: [dpdk-dev] [PATCH v5 17/19]crypto/ccp: support cpu based md5 and sha2 family authentication algo23/04/2018 08:41, Kumar, Ravi1:
Quoted 5 lines
Quoted 5 lines
Quoted 1 line
+CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=n
Why introducing a compile-time option?
Can it be a run-time option of the device?
We must not add compile-time device option if not well justified.[...]
Quoted 2 lines
By default, all the crypto operations (cipher + auth) are offloaded to CCP
engines. When user enables
CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y, the auth operations are not offloaded to CCP and rather performed over CPU. We kept this feature as a compile time option in order to let user decide whether to run auth operations on CCP or CPU as some of the auth operations performs faster on CPU as compared to their performance on CCP.Quoted 5 lines
No, you do not let the user decide.
The compilation options are for the packager to decide.
The user can rely on pre-compiled packages and use only runtime options. That's why we forbid compile-time options for such features.
Quoted 6 lines
Could you send a patch to remove this compile-time option and pass it as an option for the vdev? Look at how the crypto scheduler accepts parameters from "
rte_vdev_init" or --vdev, inscheduler_pmd.c.Thanks!
Pablo
Hi Pablo,
I have uploaded 2 patches for this issue.
If needed, you could squash the patch-1 to our very initial patch (commit 0054d84f6ec8: crypto/ccp: add AMD ccp skeleton PMD).
Please let me know if you need any other information from our side.
Regards,
Ravi
Re: [PATCH v5 17/19] crypto/ccp: support cpu based md5 and sha2 family authentication algo
Quoted 54 lines
-----Original Message-----
From: Kumar, Ravi1 [mailto:[email protected]]
Sent: Thursday, May 3, 2018 7:02 AM
To: De Lara Guarch, Pablo <[email protected]>; Thomas Monjalon <[email protected]>
Cc: [email protected]; [email protected]
Subject: RE: [dpdk-dev] [PATCH v5 17/19]crypto/ccp: support cpu based md5 and sha2 family authentication algoQuoted 22 lines
Hi Ravi,
Quoted 20 lines
-----Original Message-----
From: Thomas Monjalon [mailto:[email protected]]
Sent: Monday, April 23, 2018 9:06 AM
To: Kumar, Ravi1 <[email protected]>
Cc: De Lara Guarch, Pablo <[email protected]>; [email protected]; [email protected]
Subject: Re: [dpdk-dev] [PATCH v5 17/19]crypto/ccp: support cpu based
md5 and sha2 family authentication algo23/04/2018 08:41, Kumar, Ravi1:
Quoted 5 lines
Quoted 5 lines
Quoted 1 line
+CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=n
Why introducing a compile-time option?
Can it be a run-time option of the device?
We must not add compile-time device option if not well justified.[...]
Quoted 2 lines
By default, all the crypto operations (cipher + auth) are offloaded to CCP
engines. When user enables
CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y,the
Quoted 4 lines
Quoted 4 lines
auth operations are not offloaded to CCP and rather performed over CPU. We kept this feature as a compile time option in order to let user decide whether to run auth operations on CCP or CPU as some of the auth operations performs faster on CPU as compared to their
performance on CCP.
Quoted 8 lines
Quoted 6 lines
No, you do not let the user decide.
The compilation options are for the packager to decide.
The user can rely on pre-compiled packages and use only runtime options. That's why we forbid compile-time options for such features.Could you send a patch to remove this compile-time option and pass it as an
option for the vdev?
Quoted 1 line
Look at how the crypto scheduler accepts parameters from "
rte_vdev_init" or --vdev, in
scheduler_pmd.c.Quoted 4 lines
Thanks!
Pablo
Quoted 8 lines
Hi Pablo,
I have uploaded 2 patches for this issue.
If needed, you could squash the patch-1 to our very initial patch (commit
0054d84f6ec8:crypto/ccp: add AMD ccp skeleton PMD).Please let me know if you need any other information from our side.
This cannot be squashed into the first patch as it has already been merged, so they would be applied as they are.
Pablo
Quoted 3 lines
Regards,
Ravi
PATCH v5 18/19 test/crypto: add test for AMD CCP crypto poll mode
In reply to Ravi Kumar--- test/test/test_cryptodev.c | 161 +++++++++++++++++++++++++++ test/test/test_cryptodev.h | 1 + test/test/test_cryptodev_aes_test_vectors.h | 93 ++++++++++------ test/test/test_cryptodev_blockcipher.c | 9 +- test/test/test_cryptodev_blockcipher.h | 1 + test/test/test_cryptodev_des_test_vectors.h | 42 ++++--- test/test/test_cryptodev_hash_test_vectors.h | 60 ++++++---- 7 files changed, 301 insertions(+), 66 deletions(-)
test/test/test_cryptodev.c +161 -0
@@ -338,6 +338,23 @@ testsuite_setup(void) } } +/* Create an CCP device if required */ +if (gbl_driver_id ==rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD ))) { + nb_devs =rte_cryptodev_device_count_by_driver ( +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD ))); +if (nb_devs <1 ) { + ret =rte_vdev_init ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD ), +NULL ); + +TEST_ASSERT (ret ==0 ,"Failed to create " +"instance of pmd : %s" , +RTE_STR (CRYPTODEV_NAME_CCP_PMD )); + } + } +#ifdef RTE_LIBRTE_PMD_CRYPTO_SCHEDULER if (gbl_driver_id ==rte_cryptodev_driver_id_get (RTE_STR (CRYPTODEV_NAME_SCHEDULER_PMD ))) {
@@ -1727,6 +1744,44 @@ test_AES_cipheronly_openssl_all(void) }static int +test_AES_chain_ccp_all (void ) +{ +struct crypto_testsuite_params *ts_params = &testsuite_params; +int status; + + status =test_blockcipher_all_tests (ts_params->mbuf_pool, + ts_params->op_mpool, + ts_params->session_mpool, + ts_params->valid_devs[0 ], +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )), +BLKCIPHER_AES_CHAIN_TYPE ); + +TEST_ASSERT_EQUAL (status,0 ,"Test failed" ); + +return TEST_SUCCESS ; +} + +static int +test_AES_cipheronly_ccp_all (void ) +{ +struct crypto_testsuite_params *ts_params = &testsuite_params; +int status; + + status =test_blockcipher_all_tests (ts_params->mbuf_pool, + ts_params->op_mpool, + ts_params->session_mpool, + ts_params->valid_devs[0 ], +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )), +BLKCIPHER_AES_CIPHERONLY_TYPE ); + +TEST_ASSERT_EQUAL (status,0 ,"Test failed" ); + +return TEST_SUCCESS ; +} + +static int test_AES_chain_qat_all (void ) {struct crypto_testsuite_params *ts_params = &testsuite_params;
@@ -1898,6 +1953,25 @@ test_authonly_openssl_all(void) }static int +test_authonly_ccp_all (void ) +{ +struct crypto_testsuite_params *ts_params = &testsuite_params; +int status; + + status =test_blockcipher_all_tests (ts_params->mbuf_pool, + ts_params->op_mpool, + ts_params->session_mpool, + ts_params->valid_devs[0 ], +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )), +BLKCIPHER_AUTHONLY_TYPE ); + +TEST_ASSERT_EQUAL (status,0 ,"Test failed" ); + +return TEST_SUCCESS ; +} + +static int test_AES_chain_armv8_all (void ) {struct crypto_testsuite_params *ts_params = &testsuite_params;
@@ -4973,6 +5047,44 @@ test_3DES_cipheronly_dpaa2_sec_all(void) }static int +test_3DES_chain_ccp_all (void ) +{ +struct crypto_testsuite_params *ts_params = &testsuite_params; +int status; + + status =test_blockcipher_all_tests (ts_params->mbuf_pool, + ts_params->op_mpool, + ts_params->session_mpool, + ts_params->valid_devs[0 ], +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )), +BLKCIPHER_3DES_CHAIN_TYPE ); + +TEST_ASSERT_EQUAL (status,0 ,"Test failed" ); + +return TEST_SUCCESS ; +} + +static int +test_3DES_cipheronly_ccp_all (void ) +{ +struct crypto_testsuite_params *ts_params = &testsuite_params; +int status; + + status =test_blockcipher_all_tests (ts_params->mbuf_pool, + ts_params->op_mpool, + ts_params->session_mpool, + ts_params->valid_devs[0 ], +rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )), +BLKCIPHER_3DES_CIPHERONLY_TYPE ); + +TEST_ASSERT_EQUAL (status,0 ,"Test failed" ); + +return TEST_SUCCESS ; +} + +static int test_3DES_cipheronly_qat_all (void ) {struct crypto_testsuite_params *ts_params = &testsuite_params;
@@ -9646,6 +9758,38 @@ static struct unit_test_suite cryptodev_mrvl_testsuite = { } }; +static struct unit_test_suite cryptodev_ccp_testsuite = { + .suite_name ="Crypto Device CCP Unit Test Suite" , + .setup = testsuite_setup, + .teardown = testsuite_teardown, + .unit_test_cases = { +TEST_CASE_ST (ut_setup, ut_teardown, test_multi_session), +TEST_CASE_ST (ut_setup, ut_teardown, + test_multi_session_random_usage), +TEST_CASE_ST (ut_setup, ut_teardown, + test_AES_chain_ccp_all), +TEST_CASE_ST (ut_setup, ut_teardown, + test_AES_cipheronly_ccp_all), +TEST_CASE_ST (ut_setup, ut_teardown, + test_3DES_chain_ccp_all), +TEST_CASE_ST (ut_setup, ut_teardown, + test_3DES_cipheronly_ccp_all), +TEST_CASE_ST (ut_setup, ut_teardown, + test_authonly_ccp_all), + +/** Negative tests */ +TEST_CASE_ST (ut_setup, ut_teardown, + authentication_verify_HMAC_SHA1_fail_data_corrupt), +TEST_CASE_ST (ut_setup, ut_teardown, + authentication_verify_HMAC_SHA1_fail_tag_corrupt), +TEST_CASE_ST (ut_setup, ut_teardown, + auth_decryption_AES128CBC_HMAC_SHA1_fail_data_corrupt), +TEST_CASE_ST (ut_setup, ut_teardown, + auth_decryption_AES128CBC_HMAC_SHA1_fail_tag_corrupt), + +TEST_CASES_END ()/**< NULL terminate unit test array */ + } +};static int test_cryptodev_qat (void /*argv __rte_unused, int argc __rte_unused*/ )
@@ -9867,6 +10011,22 @@ test_cryptodev_dpaa_sec(void /*argv __rte_unused, int argc __rte_unused*/)return unit_test_suite_runner (&cryptodev_dpaa_sec_testsuite); } +static int +test_cryptodev_ccp (void ) +{ + gbl_driver_id =rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD )); + +if (gbl_driver_id ==-1 ) { +RTE_LOG (ERR ,USER1 ,"CCP PMD must be loaded. Check if " +"CONFIG_RTE_LIBRTE_PMD_CCP is enabled " +"in config file to run this testsuite.\n" ); +return TEST_FAILED ; + } + +return unit_test_suite_runner (&cryptodev_ccp_testsuite); +} +REGISTER_TEST_COMMAND (cryptodev_qat_autotest, test_cryptodev_qat);REGISTER_TEST_COMMAND (cryptodev_aesni_mb_autotest, test_cryptodev_aesni_mb);REGISTER_TEST_COMMAND (cryptodev_openssl_autotest, test_cryptodev_openssl);
@@ -9879,3 +10039,4 @@ REGISTER_TEST_COMMAND(cryptodev_sw_armv8_autotest, test_cryptodev_armv8);REGISTER_TEST_COMMAND (cryptodev_sw_mrvl_autotest, test_cryptodev_mrvl);REGISTER_TEST_COMMAND (cryptodev_dpaa2_sec_autotest, test_cryptodev_dpaa2_sec);REGISTER_TEST_COMMAND (cryptodev_dpaa_sec_autotest, test_cryptodev_dpaa_sec); +REGISTER_TEST_COMMAND (cryptodev_ccp_autotest, test_cryptodev_ccp);
test/test/test_cryptodev.h +1 -0
@@ -61,6 +61,7 @@#define CRYPTODEV_NAME_DPAA2_SEC_PMD crypto_dpaa2_sec#define CRYPTODEV_NAME_SCHEDULER_PMD crypto_scheduler#define CRYPTODEV_NAME_MRVL_PMD crypto_mrvl +#define CRYPTODEV_NAME_CCP_PMD crypto_ccp/** * Write (spread) data from buffer to mbuf data
test/test/test_cryptodev_aes_test_vectors.h +62 -31
279 lines not on this page · raw message
test/test/test_cryptodev_blockcipher.c +8 -1
@@ -54,6 +54,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t,int openssl_pmd =rte_cryptodev_driver_id_get (RTE_STR (CRYPTODEV_NAME_OPENSSL_PMD )); +int ccp_pmd =rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD ));int scheduler_pmd =rte_cryptodev_driver_id_get (RTE_STR (CRYPTODEV_NAME_SCHEDULER_PMD )); int armv8_pmd = rte_cryptodev_driver_id_get(
@@ -94,7 +96,8 @@ test_blockcipher_one_case(const struct blockcipher_test_case *t, driver_id == qat_pmd || driver_id == openssl_pmd || driver_id == armv8_pmd || - driver_id == mrvl_pmd) { /* Fall through */ + driver_id == mrvl_pmd || + driver_id == ccp_pmd) { /* Fall through */ digest_len = tdata->digest.len; } else if (driver_id == aesni_mb_pmd || driver_id == scheduler_pmd) {
@@ -555,6 +558,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool,int openssl_pmd =rte_cryptodev_driver_id_get (RTE_STR (CRYPTODEV_NAME_OPENSSL_PMD )); +int ccp_pmd =rte_cryptodev_driver_id_get ( +RTE_STR (CRYPTODEV_NAME_CCP_PMD ));int dpaa2_sec_pmd =rte_cryptodev_driver_id_get (RTE_STR (CRYPTODEV_NAME_DPAA2_SEC_PMD )); int dpaa_sec_pmd = rte_cryptodev_driver_id_get(
@@ -627,6 +632,8 @@ test_blockcipher_all_tests(struct rte_mempool *mbuf_pool, target_pmd_mask =BLOCKCIPHER_TEST_TARGET_PMD_SCHEDULER ; else if (driver_id == dpaa2_sec_pmd) target_pmd_mask =BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC ; + else if (driver_id == ccp_pmd) + target_pmd_mask =BLOCKCIPHER_TEST_TARGET_PMD_CCP ; else if (driver_id == dpaa_sec_pmd) target_pmd_mask =BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC ; else if (driver_id == mrvl_pmd)
test/test/test_cryptodev_blockcipher.h +1 -0
@@ -27,6 +27,7 @@#define BLOCKCIPHER_TEST_TARGET_PMD_DPAA2_SEC 0x0020/* DPAA2_SEC flag */ #define BLOCKCIPHER_TEST_TARGET_PMD_DPAA_SEC 0x0040/* DPAA_SEC flag */ #define BLOCKCIPHER_TEST_TARGET_PMD_MRVL 0x0080/* Marvell flag */ +#define BLOCKCIPHER_TEST_TARGET_PMD_CCP 0x0040/* CCP flag */ #define BLOCKCIPHER_TEST_OP_CIPHER (BLOCKCIPHER_TEST_OP_ENCRYPT | \ BLOCKCIPHER_TEST_OP_DECRYPT)
test/test/test_cryptodev_des_test_vectors.h +28 -14
124 lines not on this page · raw message
test/test/test_cryptodev_hash_test_vectors.h +40 -20
172 lines not on this page · raw message
Signature · 1 line
2.7.4
PATCH v5 19/19 doc: add document for AMD CCP crypto poll mode driver
In reply to Ravi Kumar--- doc/guides/cryptodevs/ccp.rst | 102 +++++++++++++++++++++++++++++ doc/guides/cryptodevs/features/ccp.ini | 57 ++++++++++++++++ doc/guides/cryptodevs/features/default.ini | 12 ++++ doc/guides/cryptodevs/index.rst | 1 + 4 files changed, 172 insertions(+) create mode 100644 doc/guides/cryptodevs/ccp.rst create mode 100644 doc/guides/cryptodevs/features/ccp.ini
doc/guides/cryptodevs/ccp.rst new file +102 -0
@@ -0,0 +1,102 @@ +.. SPDX-License-Identifier: BSD-3-Clause + Copyright(c) 2018 Advanced Micro Devices, Inc. All rights reserved. + +AMD CCP Poll Mode Driver +======================== + +This code provides the initial implementation of the ccp poll mode driver. +The CCP poll mode driver library (librte_pmd_ccp) implements support for +AMD’s cryptographic co-processor (CCP). The CCP PMD is a virtual crypto +poll mode driver which schedules crypto operations to one or more available +CCP hardware engines on the platform. The CCP PMD provides poll mode crypto +driver support for the following hardware accelerator devices:: + + AMD Cryptographic Co-processor (0x1456) + AMD Cryptographic Co-processor (0x1468) + +Features +-------- + +CCP crypto PMD has support for: + +Cipher algorithms: + +* ``RTE_CRYPTO_CIPHER_AES_CBC`` +* ``RTE_CRYPTO_CIPHER_AES_ECB`` +* ``RTE_CRYPTO_CIPHER_AES_CTR`` +* ``RTE_CRYPTO_CIPHER_3DES_CBC`` + +Hash algorithms: + +* ``RTE_CRYPTO_AUTH_SHA1`` +* ``RTE_CRYPTO_AUTH_SHA1_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA224`` +* ``RTE_CRYPTO_AUTH_SHA224_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA256`` +* ``RTE_CRYPTO_AUTH_SHA256_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA384`` +* ``RTE_CRYPTO_AUTH_SHA384_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA512`` +* ``RTE_CRYPTO_AUTH_SHA512_HMAC`` +* ``RTE_CRYPTO_AUTH_MD5_HMAC`` +* ``RTE_CRYPTO_AUTH_AES_CMAC`` +* ``RTE_CRYPTO_AUTH_SHA3_224`` +* ``RTE_CRYPTO_AUTH_SHA3_224_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA3_256`` +* ``RTE_CRYPTO_AUTH_SHA3_256_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA3_384`` +* ``RTE_CRYPTO_AUTH_SHA3_384_HMAC`` +* ``RTE_CRYPTO_AUTH_SHA3_512`` +* ``RTE_CRYPTO_AUTH_SHA3_512_HMAC`` + +AEAD algorithms: + +* ``RTE_CRYPTO_AEAD_AES_GCM`` + +Installation +------------ + +To compile CCP PMD, it has to be enabled in the config/common_base file. +* ``CONFIG_RTE_LIBRTE_PMD_CCP=y`` + +The CCP PMD also supports computing authentication over CPU with cipher offloaded +to CCP. To enable this feature, enable following in the configuration. +* ``CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y`` + +This code was verified on Ubuntu 16.04. + +Initialization +-------------- + +Bind the CCP devices to DPDK UIO driver module before running the CCP PMD stack. +e.g. for the 0x1456 device:: + + cd to the top-level DPDK directory + modprobe uio + insmod ./build/kmod/igb_uio.ko + echo "1022 1456" > /sys/bus/pci/drivers/igb_uio/new_id + +Another way to bind the CCP devices to DPDK UIO driver is by using the ``dpdk-devbind.py`` script. +The following command assumes ``BFD`` of ``0000:09:00.2``:: + + cd to the top-level DPDK directory + ./usertools/dpdk-devbind.py -b igb_uio 0000:09:00.2 + +To verify real traffic l2fwd-crypto example can be used with following command: + +.. code-block:: console + + sudo ./build/l2fwd-crypto -l 1 -n 4 --vdev "crypto_ccp" -- -p 0x1 + --chain CIPHER_HASH --cipher_op ENCRYPT --cipher_algo AES_CBC + --cipher_key 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:0f + --iv 00:01:02:03:04:05:06:07:08:09:0a:0b:0c:0d:0e:ff + --auth_op GENERATE --auth_algo SHA1_HMAC + --auth_key 11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + :11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11:11 + +Limitations +----------- + +* Chained mbufs are not supported +* MD5_HMAC is supported only if ``CONFIG_RTE_LIBRTE_PMD_CCP_CPU_AUTH=y`` is enabled in configuration
doc/guides/cryptodevs/features/ccp.ini new file +57 -0
57 lines not on this page · raw message
doc/guides/cryptodevs/features/default.ini +12 -0
@@ -28,6 +28,9 @@ NULL = AES CBC (128) = AES CBC (192) = AES CBC (256) = +AES ECB (128) = +AES ECB (192) = +AES ECB (256) = AES CTR (128) = AES CTR (192) = AES CTR (256) =
@@ -62,6 +65,15 @@ AES GMAC = SNOW3G UIA2 = KASUMI F9 = ZUC EIA3 = +AES CMAC = +SHA3_224 = +SHA3_224 HMAC = +SHA3_256 = +SHA3_256 HMAC = +SHA3_384 = +SHA3_384 HMAC = +SHA3_512 = +SHA3_512 HMAC = ; ; Supported AEAD algorithms of a default crypto driver.
doc/guides/cryptodevs/index.rst +1 -0
@@ -13,6 +13,7 @@ Crypto Device Drivers aesni_mb aesni_gcm armv8 + ccp dpaa2_sec dpaa_sec kasumi
Signature · 1 line
2.7.4
Re: [PATCH v5 01/19] crypto/ccp: add AMD ccp skeleton PMD
In reply to Ravi KumarQuoted 11 lines
-----Original Message-----
From: Ravi Kumar [mailto:[email protected]]
Sent: Monday, March 19, 2018 12:24 PM
To: [email protected]
Cc: De Lara Guarch, Pablo <[email protected]>; [email protected]
Subject: [PATCH v5 01/19]crypto/ccp: add AMD ccp skeleton PMDSigned-off-by Ravi Kumar <[email protected]>
Patchset applied to dpdk-next-crypto, with same minor changes (title changes and driver registering modification due to an earlier patch).
Thanks for the work!
Pablo
Re: [PATCH v5 01/19] crypto/ccp: add AMD ccp skeleton PMD
Quoted 10 lines
Quoted 10 lines
-----Original Message-----
From: Ravi Kumar [mailto:[email protected]]
Sent: Monday, March 19, 2018 12:24 PM
To: [email protected]
Cc: De Lara Guarch, Pablo <[email protected]>; [email protected]
Subject: [PATCH v5 01/19]crypto/ccp: add AMD ccp skeleton PMD
Quoted 7 lines
Quoted 1 line
Signed-off-by Ravi Kumar <[email protected]>Patchset applied to dpdk-next-crypto, with same minor changes (title changes and driver registering modification due to an earlier patch).
Thanks for the work!
Pablo
Thanks a lot Pablo.
Regards,
Ravi
Re: [PATCH v5 01/19] crypto/ccp: add AMD ccp skeleton PMD
Hi Ravi,
Quoted 17 lines
-----Original Message-----
From: Kumar, Ravi1 [mailto:[email protected]]
Sent: Monday, April 2, 2018 6:50 AM
To: De Lara Guarch, Pablo <[email protected]>; [email protected]
Cc: [email protected]
Subject: RE: [PATCH v5 01/19]crypto/ccp: add AMD ccp skeleton PMDQuoted 10 lines
Quoted 10 lines
-----Original Message-----
From: Ravi Kumar [mailto:[email protected]]
Sent: Monday, March 19, 2018 12:24 PM
To: [email protected]
Cc: De Lara Guarch, Pablo <[email protected]>; [email protected]
Subject: [PATCH v5 01/19]crypto/ccp: add AMD ccp skeleton PMD
Quoted 8 lines
Quoted 3 lines
Quoted 1 line
Signed-off-by Ravi Kumar <[email protected]>Patchset applied to dpdk-next-crypto, with same minor changes (title changes
and driver registering modification due to an earlier patch).
Quoted 4 lines
Thanks for the work!
Pablo
There's been a memory rework applied in DPDK at the same time I applied your PMD in next-crypto, Which means that it is broken now. Could you submit a fix for it?
At least, compilation is broken now, but it may require more changes:
drivers/crypto/ccp/ccp_dev.c:98:7: error: implicit declaration of function 'rte_eal_get_physmem_layout' is invalid in C99
[-Werror,-Wimplicit-function-declaration]
ms = rte_eal_get_physmem_layout();This function does not exist anymore.
Commit 2d84772bf858 ("crypto/qat: use contiguous allocation for DMA memory") makes a similar required changed in QAT.
Take a look at it and see if it suits you.
Quoted 5 lines
Thanks a lot Pablo.
Regards,
Ravi
Re: [PATCH v5 01/19] crypto/ccp: add AMD ccp skeleton PMD
Quoted 33 lines
Hi Ravi,
Quoted 18 lines
-----Original Message-----
From: Kumar, Ravi1 [mailto:[email protected]]
Sent: Monday, April 2, 2018 6:50 AM
To: De Lara Guarch, Pablo <[email protected]>; [email protected]
Cc: [email protected]
Subject: RE: [PATCH v5 01/19]crypto/ccp: add AMD ccp skeleton PMDQuoted 10 lines
Quoted 10 lines
-----Original Message-----
From: Ravi Kumar [mailto:[email protected]]
Sent: Monday, March 19, 2018 12:24 PM
To: [email protected]
Cc: De Lara Guarch, Pablo <[email protected]>; [email protected]
Subject: [PATCH v5 01/19]crypto/ccp: add AMD ccp skeleton PMDQuoted 9 lines
Quoted 4 lines
Quoted 1 line
Signed-off-by Ravi Kumar <[email protected]>Patchset applied to dpdk-next-crypto, with same minor changes (title changes
and driver registering modification due to an earlier patch).
Quoted 4 lines
Thanks for the work!
PabloThere's been a memory rework applied in DPDK at the same time I applied your PMD in next-crypto, Which means that it is broken now. Could you submit a fix for it? At least, compilation is broken now, but it may require more changes:
Quoted 8 lines
drivers/crypto/ccp/ccp_dev.c:98:7: error: implicit declaration of function 'rte_eal_get_physmem_layout' is invalid in C99[-Werror,-Wimplicit-function-declaration] ms = rte_eal_get_physmem_layout();This function does not exist anymore.
Commit2d84772bf858("crypto/qat: use contiguous allocation for DMA memory") makes a similar required changed in QAT. Take a look at it and see if it suits you.
Hi Pablo,
Sure, we will send updated patch for this.
Regards,
Ravi
Quoted 6 lines
Quoted 5 lines
Thanks a lot Pablo.
Regards,
Ravi
Re: [PATCH v5 01/19] crypto/ccp: add AMD ccp skeleton PMD
In reply to Ravi KumarHi,
19/03/2018 13:23, Ravi Kumar:
config/common_base CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n · line 534
Quoted 9 lines
config/common_base +3
-0@@ -529,6 +529,11 @@ CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y # +# Compile PMD for AMD CCP crypto device +# +CONFIG_RTE_LIBRTE_PMD_CCP=n
Why is it disabled by default?
Re: [PATCH v5 01/19] crypto/ccp: add AMD ccp skeleton PMD
Quoted 8 lines
Hi,
19/03/2018 13:23, Ravi Kumar:
Quoted 5 lines
config/common_base +0
-0@@ -529,6 +529,11 @@ CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y
Quoted 5 lines
config/common_base CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n · line 532
Quoted 2 lines
config/common_base +1
-0# +# Compile PMD for AMD CCP crypto device # CONFIG_RTE_LIBRTE_PMD_CCP=nWhy is it disabled by default?
Hi Thomas,
The CCP HW crypto engines are available only on specific AMD platforms. That is why we let the user decide when to enable.
Regards,
Ravi
Re: [PATCH v5 01/19] crypto/ccp: add AMD ccp skeleton PMD
Hi,
Quoted 20 lines
-----Original Message-----
From: Kumar, Ravi1 [mailto:[email protected]]
Sent: Monday, April 23, 2018 7:37 AM
To: Thomas Monjalon <[email protected]>; De Lara Guarch, Pablo <[email protected]>
Cc: [email protected]; [email protected]
Subject: RE: [dpdk-dev] [PATCH v5 01/19]crypto/ccp: add AMD ccp skeleton PMDQuoted 6 lines
Hi,
19/03/2018 13:23, Ravi Kumar:
config/common_base
Quoted 3 lines
config/common_base +0
-0@@ -529,6 +529,11 @@
CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=nQuoted 4 lines
config/common_base CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n
Quoted 4 lines
config/common_base +1
-0CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=y # +# Compile PMD for AMD CCP crypto device #
Quoted 8 lines
CONFIG_RTE_LIBRTE_PMD_CCP=nQuoted 3 lines
Why is it disabled by default?
Hi Thomas,
The CCP HW crypto engines are available only on specific AMD platforms. That is why we let the user decide when to enable.
Actually, I thought this was disabled because this PMD has an external dependency with libcrypto.
Quoted 3 lines
Regards,
Ravi
Re: [PATCH v5 01/19] crypto/ccp: add AMD ccp skeleton PMD
In reply to Kumar, Ravi123/04/2018 08:37, Kumar, Ravi1:
Quoted 13 lines
Quoted 8 lines
Hi,
19/03/2018 13:23, Ravi Kumar:
Quoted 5 lines
config/common_base +0
-0@@ -529,6 +529,11 @@ CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n CONFIG_RTE_LIBRTE_PMD_NULL_CRYPTO=yQuoted 5 lines
config/common_base CONFIG_RTE_LIBRTE_PMD_CRYPTO_SCHEDULER_DEBUG=n · line 532
Quoted 2 lines
config/common_base +1
-0# +# Compile PMD for AMD CCP crypto device # CONFIG_RTE_LIBRTE_PMD_CCP=nWhy is it disabled by default?
Quoted 4 lines
Hi Thomas,
The CCP HW crypto engines are available only on specific AMD platforms. That is why we let the user decide when to enable.
Most of the devices are not always available,
but they are enabled by default.
Can we enable this one from the first patch?