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mips: bmips: add BCM3380 SoC support

PATCH New Álvaro Fernández Rojas 3 participants 12 messages May 15, 2017 – May 20, 2017

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Álvaro Fernández Rojas

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#0 lore raw

cover mips: bmips: add BCM3380 SoC support

BCM3380 is a dual core BCM33xx SoC, which means that it's pretty similar to the BCM63xx, but it's meant for HFC instead of xDSL.
The pll_conf register seems to be bugged, because it just stalls the SoC instead of performing a reboot, so the watchdog needs to be used as sysreset.

Álvaro Fernández Rojas (3):
dm: cpu: bmips: add BCM3380 support
MIPS: add support for Broadcom MIPS BCM3380 SoC family
MIPS: add BMIPS Netgear CG3100D board

 arch/mips/dts/Makefile                    |   1 +
 arch/mips/dts/brcm,bcm3380.dtsi           | 154 ++++++++++++++++++++++++++++++
 arch/mips/dts/netgear,cg3100d.dts         |  96 +++++++++++++++++++
 arch/mips/mach-bmips/Kconfig              |  18 ++++
 board/netgear/cg3100d/Kconfig             |  12 +++
 board/netgear/cg3100d/MAINTAINERS         |   6 ++
 board/netgear/cg3100d/Makefile            |   5 +
 board/netgear/cg3100d/cg3100d.c           |   7 ++
 configs/netgear_cg3100d_ram_defconfig     |  56 +++++++++++
 drivers/cpu/bmips_cpu.c                   |  14 +++
 include/configs/bmips_bcm3380.h           |  25 +++++
 include/configs/netgear_cg3100d.h         |  15 +++
 include/dt-bindings/clock/bcm3380-clock.h |  23 +++++
 include/dt-bindings/reset/bcm3380-reset.h |  16 ++++
 14 files changed, 448 insertions(+)
 create mode 100644 arch/mips/dts/brcm,bcm3380.dtsi
 create mode 100644 arch/mips/dts/netgear,cg3100d.dts
 create mode 100644 board/netgear/cg3100d/Kconfig
 create mode 100644 board/netgear/cg3100d/MAINTAINERS
 create mode 100644 board/netgear/cg3100d/Makefile
 create mode 100644 board/netgear/cg3100d/cg3100d.c
 create mode 100644 configs/netgear_cg3100d_ram_defconfig
 create mode 100644 include/configs/bmips_bcm3380.h
 create mode 100644 include/configs/netgear_cg3100d.h
 create mode 100644 include/dt-bindings/clock/bcm3380-clock.h
 create mode 100644 include/dt-bindings/reset/bcm3380-reset.h
Signature · 1 line
2.1.4
author
#1 lore raw

PATCH 1/3 dm: cpu: bmips: add BCM3380 support

As far as I know BCM3380 has a fixed CPU frequency since I couldn't find its PLL registers in any documentation.

Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 drivers/cpu/bmips_cpu.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
drivers/cpu/bmips_cpu.c +14 -0
index 2381081..4f412fa 100644
@@ -96,6 +96,11 @@ static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 	return 0;
 }
 
+static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+	return 333000000;
+}
+
 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 {
 	unsigned int mips_pll_fcvo;

@@ -190,6 +195,12 @@ static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 	return 2;
 }
 
+static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
+	.get_cpu_desc = bmips_short_cpu_desc,
+	.get_cpu_freq = bcm3380_get_cpu_freq,
+	.get_cpu_count = bcm6358_get_cpu_count,
+};
+
 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
 	.get_cpu_desc = bmips_long_cpu_desc,
 	.get_cpu_freq = bcm6328_get_cpu_freq,

@@ -290,6 +301,9 @@ int bmips_cpu_probe(struct udevice *dev)
 
 static const struct udevice_id bmips_cpu_ids[] = {
 	{
+		.compatible = "brcm,bcm3380-cpu",
+		.data = (ulong)&bmips_cpu_bcm3380,
+	}, {
 		.compatible = "brcm,bcm6328-cpu",
 		.data = (ulong)&bmips_cpu_bcm6328,
 	}, {
Signature · 1 line
2.1.4
author
#2 lore raw

PATCH 2/3 MIPS: add support for Broadcom MIPS BCM3380 SoC family

In reply to Álvaro Fernández Rojas
Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 arch/mips/dts/brcm,bcm3380.dtsi           | 154 ++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig              |  12 +++
 include/configs/bmips_bcm3380.h           |  25 +++++
 include/dt-bindings/clock/bcm3380-clock.h |  23 +++++
 include/dt-bindings/reset/bcm3380-reset.h |  16 ++++
 5 files changed, 230 insertions(+)
 create mode 100644 arch/mips/dts/brcm,bcm3380.dtsi
 create mode 100644 include/configs/bmips_bcm3380.h
 create mode 100644 include/dt-bindings/clock/bcm3380-clock.h
 create mode 100644 include/dt-bindings/reset/bcm3380-reset.h
arch/mips/dts/brcm,bcm3380.dtsi new file +154 -0
new file mode 100644
index 0000000..e351d58
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm3380-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm3380-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm3380";
+
+	cpus {
+		reg = <0x14e00000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu at 0 {
+			compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu at 1 {
+			compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <1>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_clk0: periph-clk at 14e00004 {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0x14e00004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		periph_clk1: periph-clk at 14e00008 {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0x14e00008 0x4>;
+			#clock-cells = <1>;
+		};
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		memory-controller at 12000000 {
+			compatible = "brcm,bcm6328-mc";
+			reg = <0x12000000 0x1000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_rst0: reset-controller at 14e0008c {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x14e0008c 0x4>;
+			#reset-cells = <1>;
+		};
+
+		periph_rst1: reset-controller at 14e00090 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x14e00090 0x4>;
+			#reset-cells = <1>;
+		};
+
+		pll_cntl: syscon at 14e00094 {
+			compatible = "syscon";
+			reg = <0x14e00094 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		wdt: watchdog at 14e000dc {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x14e000dc 0xc>;
+
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
+		gpio0: gpio-controller at 14e00100 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			status = "disabled";
+		};
+
+		gpio1: gpio-controller at 14e00104 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <3>;
+
+			status = "disabled";
+		};
+
+		uart0: serial at 14e00200 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x14e00200 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		uart1: serial at 14e00220 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x14e00220 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		leds: led-controller at 14e00f00 {
+			compatible = "brcm,bcm6328-leds";
+			reg = <0x14e00f00 0x1c>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+	};
+};
arch/mips/mach-bmips/Kconfig +12 -0
index c2b0f89..9755bc0 100644
@@ -2,6 +2,7 @@ menu "Broadcom MIPS platforms"
 	depends on ARCH_BMIPS
 
 config SYS_SOC
+	default "bcm3380" if SOC_BMIPS_BCM3380
 	default "bcm6328" if SOC_BMIPS_BCM6328
 	default "bcm6348" if SOC_BMIPS_BCM6348
 	default "bcm6358" if SOC_BMIPS_BCM6358

@@ -10,6 +11,17 @@ config SYS_SOC
 choice
 	prompt "Broadcom MIPS SoC select"
 
+config SOC_BMIPS_BCM3380
+	bool "BMIPS BCM3380 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_WATCHDOG
+	help
+	  This supports BMIPS BCM3380 family.
+
 config SOC_BMIPS_BCM6328
 	bool "BMIPS BCM6328 family"
 	select SUPPORTS_BIG_ENDIAN
include/configs/bmips_bcm3380.h new file +25 -0
new file mode 100644
index 0000000..0c3f7f5
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM3380_H
+#define __CONFIG_BMIPS_BCM3380_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	166500000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM3380_H */
include/dt-bindings/clock/bcm3380-clock.h new file +23 -0
new file mode 100644
index 0000000..00add2f
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * Derived from Broadcom GPL Source Code:
+ *	Copyright (C) Broadcom Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM3380_H
+#define __DT_BINDINGS_CLOCK_BCM3380_H
+
+#define BCM3380_CLK0_DDR	0
+#define BCM3380_CLK0_FPM	1
+#define BCM3380_CLK0_CRYPTO	2
+#define BCM3380_CLK0_EPHY	3
+#define BCM3380_CLK0_PCIE	16
+#define BCM3380_CLK0_SPI	17
+#define BCM3380_CLK0_ENET0	18
+#define BCM3380_CLK0_ENET1	19
+#define BCM3380_CLK0_PCM	27
+
+#endif /* __DT_BINDINGS_CLOCK_BCM3380_H */
include/dt-bindings/reset/bcm3380-reset.h new file +16 -0
new file mode 100644
index 0000000..ddc575d
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * Derived from Broadcom GPL Source Code:
+ *	Copyright (C) Broadcom Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM3380_H
+#define __DT_BINDINGS_RESET_BCM3380_H
+
+#define BCM3380_RST0_SPI	0
+#define BCM3380_RST0_PCM	13
+
+#endif /* __DT_BINDINGS_RESET_BCM3380_H */
Signature · 1 line
2.1.4
author
#3 lore raw

PATCH 3/3 MIPS: add BMIPS Netgear CG3100D board

In reply to Álvaro Fernández Rojas
Signed-off-by Álvaro Fernández Rojas <[email protected]>
---
 arch/mips/dts/Makefile                |  1 +
 arch/mips/dts/netgear,cg3100d.dts     | 96 +++++++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig          |  6 +++
 board/netgear/cg3100d/Kconfig         | 12 +++++
 board/netgear/cg3100d/MAINTAINERS     |  6 +++
 board/netgear/cg3100d/Makefile        |  5 ++
 board/netgear/cg3100d/cg3100d.c       |  7 +++
 configs/netgear_cg3100d_ram_defconfig | 56 ++++++++++++++++++++
 include/configs/netgear_cg3100d.h     | 15 ++++++
 9 files changed, 204 insertions(+)
 create mode 100644 arch/mips/dts/netgear,cg3100d.dts
 create mode 100644 board/netgear/cg3100d/Kconfig
 create mode 100644 board/netgear/cg3100d/MAINTAINERS
 create mode 100644 board/netgear/cg3100d/Makefile
 create mode 100644 board/netgear/cg3100d/cg3100d.c
 create mode 100644 configs/netgear_cg3100d_ram_defconfig
 create mode 100644 include/configs/netgear_cg3100d.h
arch/mips/dts/Makefile +1 -0
index 9bab744..fdce645 100644
@@ -12,6 +12,7 @@ dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
 dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
 dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
 dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
+dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 
 targets += $(dtb-y)
arch/mips/dts/netgear,cg3100d.dts new file +96 -0

96 lines not on this page · raw message

arch/mips/mach-bmips/Kconfig +6 -0
index 9755bc0..a843fda 100644
@@ -92,6 +92,11 @@ config BOARD_HUAWEI_HG556A
 	depends on SOC_BMIPS_BCM6358
 	select BMIPS_SUPPORTS_BOOT_RAM
 
+config BOARD_NETGEAR_CG3100D
+	bool "Netgear CG3100D"
+	depends on SOC_BMIPS_BCM3380
+	select BMIPS_SUPPORTS_BOOT_RAM
+
 config BOARD_SFR_NB4_SER
 	bool "SFR NeufBox 4 (Sercomm)"
 	depends on SOC_BMIPS_BCM6358

@@ -119,6 +124,7 @@ source "board/comtrend/ar5387un/Kconfig"
 source "board/comtrend/ct5361/Kconfig"
 source "board/comtrend/vr3032u/Kconfig"
 source "board/huawei/hg556a/Kconfig"
+source "board/netgear/cg3100d/Kconfig"
 source "board/sfr/nb4_ser/Kconfig"
 
 endmenu
board/netgear/cg3100d/Kconfig new file +12 -0
new file mode 100644
index 0000000..632c22d
@@ -0,0 +1,12 @@
+if BOARD_NETGEAR_CG3100D
+
+config SYS_BOARD
+	default "cg3100d"
+
+config SYS_VENDOR
+	default "netgear"
+
+config SYS_CONFIG_NAME
+	default "netgear_cg3100d"
+
+endif
board/netgear/cg3100d/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..f1dcb1f
@@ -0,0 +1,6 @@
+NETGEAR CG3100D BOARD
+M:	Álvaro Fernández Rojas <[email protected]>
+S:	Maintained
+F:	board/netgear/cg3100d/
+F:	include/configs/netgear_cg3100d.h
+F:	configs/netgear_cg3100d_ram_defconfig
board/netgear/cg3100d/Makefile new file +5 -0
new file mode 100644
index 0000000..b82e59e
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cg3100d.o
board/netgear/cg3100d/cg3100d.c new file +7 -0
new file mode 100644
index 0000000..d181ca6
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
configs/netgear_cg3100d_ram_defconfig new file +56 -0

56 lines not on this page · raw message

include/configs/netgear_cg3100d.h new file +15 -0
new file mode 100644
index 0000000..c97d4e5
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm3380.h>
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
Signature · 1 line
2.1.4
author
#4 lore raw

v2 cover mips: bmips: add BCM3380 SoC support

In reply to Álvaro Fernández Rojas

BCM3380 is a dual core BCM33xx SoC, which means that it's pretty similar to the BCM63xx, but it's meant for HFC instead of xDSL.
The pll_conf register seems to be bugged, because it just stalls the SoC instead of performing a reboot, so the watchdog needs to be used as sysreset.

v2: Introduce changes requested by Simon Glass.

Álvaro Fernández Rojas (3):
dm: cpu: bmips: add BCM3380 support
MIPS: add support for Broadcom MIPS BCM3380 SoC family
MIPS: add BMIPS Netgear CG3100D board

 arch/mips/dts/Makefile                    |   1 +
 arch/mips/dts/brcm,bcm3380.dtsi           | 154 ++++++++++++++++++++++++++++++
 arch/mips/dts/netgear,cg3100d.dts         |  96 +++++++++++++++++++
 arch/mips/mach-bmips/Kconfig              |  24 +++++
 board/netgear/cg3100d/Kconfig             |  12 +++
 board/netgear/cg3100d/MAINTAINERS         |   6 ++
 board/netgear/cg3100d/Makefile            |   5 +
 board/netgear/cg3100d/cg3100d.c           |   7 ++
 configs/netgear_cg3100d_ram_defconfig     |  56 +++++++++++
 drivers/cpu/bmips_cpu.c                   |  14 +++
 include/configs/bmips_bcm3380.h           |  25 +++++
 include/configs/netgear_cg3100d.h         |  15 +++
 include/dt-bindings/clock/bcm3380-clock.h |  23 +++++
 include/dt-bindings/reset/bcm3380-reset.h |  16 ++++
 14 files changed, 454 insertions(+)
 create mode 100644 arch/mips/dts/brcm,bcm3380.dtsi
 create mode 100644 arch/mips/dts/netgear,cg3100d.dts
 create mode 100644 board/netgear/cg3100d/Kconfig
 create mode 100644 board/netgear/cg3100d/MAINTAINERS
 create mode 100644 board/netgear/cg3100d/Makefile
 create mode 100644 board/netgear/cg3100d/cg3100d.c
 create mode 100644 configs/netgear_cg3100d_ram_defconfig
 create mode 100644 include/configs/bmips_bcm3380.h
 create mode 100644 include/configs/netgear_cg3100d.h
 create mode 100644 include/dt-bindings/clock/bcm3380-clock.h
 create mode 100644 include/dt-bindings/reset/bcm3380-reset.h
Signature · 1 line
2.1.4
author
#5 lore raw

PATCH v2 1/3 dm: cpu: bmips: add BCM3380 support

As far as I know BCM3380 has a fixed CPU frequency since I couldn't find its PLL registers in any documentation.

Signed-off-by Álvaro Fernández Rojas <[email protected]>

---
v2: no changes.

 drivers/cpu/bmips_cpu.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
drivers/cpu/bmips_cpu.c +14 -0
index 2381081..4f412fa 100644
@@ -96,6 +96,11 @@ static int bmips_long_cpu_desc(struct bmips_cpu_priv *priv, char *buf,
 	return 0;
 }
 
+static ulong bcm3380_get_cpu_freq(struct bmips_cpu_priv *priv)
+{
+	return 333000000;
+}
+
 static ulong bcm6328_get_cpu_freq(struct bmips_cpu_priv *priv)
 {
 	unsigned int mips_pll_fcvo;

@@ -190,6 +195,12 @@ static int bcm6358_get_cpu_count(struct bmips_cpu_priv *priv)
 	return 2;
 }
 
+static const struct bmips_cpu_hw bmips_cpu_bcm3380 = {
+	.get_cpu_desc = bmips_short_cpu_desc,
+	.get_cpu_freq = bcm3380_get_cpu_freq,
+	.get_cpu_count = bcm6358_get_cpu_count,
+};
+
 static const struct bmips_cpu_hw bmips_cpu_bcm6328 = {
 	.get_cpu_desc = bmips_long_cpu_desc,
 	.get_cpu_freq = bcm6328_get_cpu_freq,

@@ -290,6 +301,9 @@ int bmips_cpu_probe(struct udevice *dev)
 
 static const struct udevice_id bmips_cpu_ids[] = {
 	{
+		.compatible = "brcm,bcm3380-cpu",
+		.data = (ulong)&bmips_cpu_bcm3380,
+	}, {
 		.compatible = "brcm,bcm6328-cpu",
 		.data = (ulong)&bmips_cpu_bcm6328,
 	}, {
Signature · 1 line
2.1.4
author
#7 lore raw

PATCH v2 2/3 MIPS: add support for Broadcom MIPS BCM3380 SoC family

In reply to Álvaro Fernández Rojas
Signed-off-by Álvaro Fernández Rojas <[email protected]>

---
v2: no changes.

 arch/mips/dts/brcm,bcm3380.dtsi           | 154 ++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig              |  12 +++
 include/configs/bmips_bcm3380.h           |  25 +++++
 include/dt-bindings/clock/bcm3380-clock.h |  23 +++++
 include/dt-bindings/reset/bcm3380-reset.h |  16 ++++
 5 files changed, 230 insertions(+)
 create mode 100644 arch/mips/dts/brcm,bcm3380.dtsi
 create mode 100644 include/configs/bmips_bcm3380.h
 create mode 100644 include/dt-bindings/clock/bcm3380-clock.h
 create mode 100644 include/dt-bindings/reset/bcm3380-reset.h
arch/mips/dts/brcm,bcm3380.dtsi new file +154 -0
new file mode 100644
index 0000000..e351d58
@@ -0,0 +1,154 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <dt-bindings/clock/bcm3380-clock.h>
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/reset/bcm3380-reset.h>
+#include "skeleton.dtsi"
+
+/ {
+	compatible = "brcm,bcm3380";
+
+	cpus {
+		reg = <0x14e00000 0x4>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		u-boot,dm-pre-reloc;
+
+		cpu at 0 {
+			compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <0>;
+			u-boot,dm-pre-reloc;
+		};
+
+		cpu at 1 {
+			compatible = "brcm,bcm3380-cpu", "mips,mips4Kc";
+			device_type = "cpu";
+			reg = <1>;
+			u-boot,dm-pre-reloc;
+		};
+	};
+
+	clocks {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		periph_osc: periph-osc {
+			compatible = "fixed-clock";
+			#clock-cells = <0>;
+			clock-frequency = <50000000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_clk0: periph-clk at 14e00004 {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0x14e00004 0x4>;
+			#clock-cells = <1>;
+		};
+
+		periph_clk1: periph-clk at 14e00008 {
+			compatible = "brcm,bcm6345-clk";
+			reg = <0x14e00008 0x4>;
+			#clock-cells = <1>;
+		};
+	};
+
+	ubus {
+		compatible = "simple-bus";
+		#address-cells = <1>;
+		#size-cells = <1>;
+		u-boot,dm-pre-reloc;
+
+		memory-controller at 12000000 {
+			compatible = "brcm,bcm6328-mc";
+			reg = <0x12000000 0x1000>;
+			u-boot,dm-pre-reloc;
+		};
+
+		periph_rst0: reset-controller at 14e0008c {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x14e0008c 0x4>;
+			#reset-cells = <1>;
+		};
+
+		periph_rst1: reset-controller at 14e00090 {
+			compatible = "brcm,bcm6345-reset";
+			reg = <0x14e00090 0x4>;
+			#reset-cells = <1>;
+		};
+
+		pll_cntl: syscon at 14e00094 {
+			compatible = "syscon";
+			reg = <0x14e00094 0x4>;
+		};
+
+		syscon-reboot {
+			compatible = "syscon-reboot";
+			regmap = <&pll_cntl>;
+			offset = <0x0>;
+			mask = <0x1>;
+		};
+
+		wdt: watchdog at 14e000dc {
+			compatible = "brcm,bcm6345-wdt";
+			reg = <0x14e000dc 0xc>;
+
+			clocks = <&periph_osc>;
+		};
+
+		wdt-reboot {
+			compatible = "wdt-reboot";
+			wdt = <&wdt>;
+		};
+
+		gpio0: gpio-controller at 14e00100 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x14e00100 0x4>, <0x14e00108 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+
+			status = "disabled";
+		};
+
+		gpio1: gpio-controller at 14e00104 {
+			compatible = "brcm,bcm6345-gpio";
+			reg = <0x14e00104 0x4>, <0x14e0010c 0x4>;
+			gpio-controller;
+			#gpio-cells = <2>;
+			ngpios = <3>;
+
+			status = "disabled";
+		};
+
+		uart0: serial at 14e00200 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x14e00200 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		uart1: serial at 14e00220 {
+			compatible = "brcm,bcm6345-uart";
+			reg = <0x14e00220 0x18>;
+			clocks = <&periph_osc>;
+
+			status = "disabled";
+		};
+
+		leds: led-controller at 14e00f00 {
+			compatible = "brcm,bcm6328-leds";
+			reg = <0x14e00f00 0x1c>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			status = "disabled";
+		};
+	};
+};
arch/mips/mach-bmips/Kconfig +12 -0
index b980587..9cf8e5c 100644
@@ -2,6 +2,7 @@ menu "Broadcom MIPS platforms"
 	depends on ARCH_BMIPS
 
 config SYS_SOC
+	default "bcm3380" if SOC_BMIPS_BCM3380
 	default "bcm6328" if SOC_BMIPS_BCM6328
 	default "bcm6348" if SOC_BMIPS_BCM6348
 	default "bcm6358" if SOC_BMIPS_BCM6358

@@ -10,6 +11,17 @@ config SYS_SOC
 choice
 	prompt "Broadcom MIPS SoC select"
 
+config SOC_BMIPS_BCM3380
+	bool "BMIPS BCM3380 family"
+	select SUPPORTS_BIG_ENDIAN
+	select SUPPORTS_CPU_MIPS32_R1
+	select MIPS_TUNE_4KC
+	select MIPS_L1_CACHE_SHIFT_4
+	select SWAP_IO_SPACE
+	select SYSRESET_WATCHDOG
+	help
+	  This supports BMIPS BCM3380 family.
+
 config SOC_BMIPS_BCM6328
 	bool "BMIPS BCM6328 family"
 	select SUPPORTS_BIG_ENDIAN
include/configs/bmips_bcm3380.h new file +25 -0
new file mode 100644
index 0000000..0c3f7f5
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __CONFIG_BMIPS_BCM3380_H
+#define __CONFIG_BMIPS_BCM3380_H
+
+/* CPU */
+#define CONFIG_SYS_MIPS_TIMER_FREQ	166500000
+
+/* RAM */
+#define CONFIG_NR_DRAM_BANKS		1
+#define CONFIG_SYS_SDRAM_BASE		0x80000000
+
+/* U-Boot */
+#define CONFIG_SYS_LOAD_ADDR		CONFIG_SYS_SDRAM_BASE + 0x100000
+
+#if defined(CONFIG_BMIPS_BOOT_RAM)
+#define CONFIG_SKIP_LOWLEVEL_INIT
+#define CONFIG_SYS_INIT_SP_OFFSET	0x2000
+#endif
+
+#endif /* __CONFIG_BMIPS_BCM3380_H */
include/dt-bindings/clock/bcm3380-clock.h new file +23 -0
new file mode 100644
index 0000000..00add2f
@@ -0,0 +1,23 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * Derived from Broadcom GPL Source Code:
+ *	Copyright (C) Broadcom Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_BCM3380_H
+#define __DT_BINDINGS_CLOCK_BCM3380_H
+
+#define BCM3380_CLK0_DDR	0
+#define BCM3380_CLK0_FPM	1
+#define BCM3380_CLK0_CRYPTO	2
+#define BCM3380_CLK0_EPHY	3
+#define BCM3380_CLK0_PCIE	16
+#define BCM3380_CLK0_SPI	17
+#define BCM3380_CLK0_ENET0	18
+#define BCM3380_CLK0_ENET1	19
+#define BCM3380_CLK0_PCM	27
+
+#endif /* __DT_BINDINGS_CLOCK_BCM3380_H */
include/dt-bindings/reset/bcm3380-reset.h new file +16 -0
new file mode 100644
index 0000000..ddc575d
@@ -0,0 +1,16 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * Derived from Broadcom GPL Source Code:
+ *	Copyright (C) Broadcom Corporation
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#ifndef __DT_BINDINGS_RESET_BCM3380_H
+#define __DT_BINDINGS_RESET_BCM3380_H
+
+#define BCM3380_RST0_SPI	0
+#define BCM3380_RST0_PCM	13
+
+#endif /* __DT_BINDINGS_RESET_BCM3380_H */
Signature · 1 line
2.1.4
#8 lore raw

PATCH v2 2/3 MIPS: add support for Broadcom MIPS BCM3380 SoC family

Quoted 4 lines · Álvaro Fernández Rojas
Signed-off-by Álvaro Fernández Rojas <[email protected]>

---
v2: no changes.

Quoted 11 lines
 arch/mips/dts/brcm,bcm3380.dtsi           | 154 ++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig              |  12 +++
 include/configs/bmips_bcm3380.h           |  25 +++++
 include/dt-bindings/clock/bcm3380-clock.h |  23 +++++
 include/dt-bindings/reset/bcm3380-reset.h |  16 ++++
 5 files changed, 230 insertions(+)
 create mode 100644 arch/mips/dts/brcm,bcm3380.dtsi
 create mode 100644 include/configs/bmips_bcm3380.h
 create mode 100644 include/dt-bindings/clock/bcm3380-clock.h
 create mode 100644 include/dt-bindings/reset/bcm3380-reset.h
Reviewed-by Simon Glass <[email protected]>
author
#9 lore raw

PATCH v2 3/3 MIPS: add BMIPS Netgear CG3100D board

In reply to Álvaro Fernández Rojas
Signed-off-by Álvaro Fernández Rojas <[email protected]>

---
v2: introduce changes requested by Simon Glass:
- Add board description.

 arch/mips/dts/Makefile                |  1 +
 arch/mips/dts/netgear,cg3100d.dts     | 96 +++++++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig          | 12 +++++
 board/netgear/cg3100d/Kconfig         | 12 +++++
 board/netgear/cg3100d/MAINTAINERS     |  6 +++
 board/netgear/cg3100d/Makefile        |  5 ++
 board/netgear/cg3100d/cg3100d.c       |  7 +++
 configs/netgear_cg3100d_ram_defconfig | 56 ++++++++++++++++++++
 include/configs/netgear_cg3100d.h     | 15 ++++++
 9 files changed, 210 insertions(+)
 create mode 100644 arch/mips/dts/netgear,cg3100d.dts
 create mode 100644 board/netgear/cg3100d/Kconfig
 create mode 100644 board/netgear/cg3100d/MAINTAINERS
 create mode 100644 board/netgear/cg3100d/Makefile
 create mode 100644 board/netgear/cg3100d/cg3100d.c
 create mode 100644 configs/netgear_cg3100d_ram_defconfig
 create mode 100644 include/configs/netgear_cg3100d.h
arch/mips/dts/Makefile +1 -0
index 9bab744..fdce645 100644
@@ -12,6 +12,7 @@ dtb-$(CONFIG_BOARD_COMTREND_AR5387UN) += comtrend,ar-5387un.dtb
 dtb-$(CONFIG_BOARD_COMTREND_CT5361) += comtrend,ct-5361.dtb
 dtb-$(CONFIG_BOARD_COMTREND_VR3032U) += comtrend,vr-3032u.dtb
 dtb-$(CONFIG_BOARD_HUAWEI_HG556A) += huawei,hg556a.dtb
+dtb-$(CONFIG_BOARD_NETGEAR_CG3100D) += netgear,cg3100d.dtb
 dtb-$(CONFIG_BOARD_TPLINK_WDR4300) += tplink_wdr4300.dtb
 
 targets += $(dtb-y)
arch/mips/dts/netgear,cg3100d.dts new file +96 -0

96 lines not on this page · raw message

arch/mips/mach-bmips/Kconfig +12 -0
index 9cf8e5c..e849438 100644
@@ -98,6 +98,17 @@ config BOARD_HUAWEI_HG556A
 	depends on SOC_BMIPS_BCM6358
 	select BMIPS_SUPPORTS_BOOT_RAM
 
+config BOARD_NETGEAR_CG3100D
+	bool "Netgear CG3100D"
+	depends on SOC_BMIPS_BCM3380
+	select BMIPS_SUPPORTS_BOOT_RAM
+	help
+	  Netgear CG3100D boards have a BCM3380 SoC with 64 MB of RAM and 8 MB
+	  of flash (SPI).
+	  Between its different peripherals there's a BCM53115 switch with 4
+	  ethernet ports, 1 UART, GPIO buttons and LEDs, and a BCM43225
+	  (miniPCIe).
+
 config BOARD_SFR_NB4_SER
 	bool "SFR NeufBox 4 (Sercomm)"
 	depends on SOC_BMIPS_BCM6358

@@ -125,6 +136,7 @@ source "board/comtrend/ar5387un/Kconfig"
 source "board/comtrend/ct5361/Kconfig"
 source "board/comtrend/vr3032u/Kconfig"
 source "board/huawei/hg556a/Kconfig"
+source "board/netgear/cg3100d/Kconfig"
 source "board/sfr/nb4_ser/Kconfig"
 
 endmenu
board/netgear/cg3100d/Kconfig new file +12 -0
new file mode 100644
index 0000000..632c22d
@@ -0,0 +1,12 @@
+if BOARD_NETGEAR_CG3100D
+
+config SYS_BOARD
+	default "cg3100d"
+
+config SYS_VENDOR
+	default "netgear"
+
+config SYS_CONFIG_NAME
+	default "netgear_cg3100d"
+
+endif
board/netgear/cg3100d/MAINTAINERS new file +6 -0
new file mode 100644
index 0000000..f1dcb1f
@@ -0,0 +1,6 @@
+NETGEAR CG3100D BOARD
+M:	Álvaro Fernández Rojas <[email protected]>
+S:	Maintained
+F:	board/netgear/cg3100d/
+F:	include/configs/netgear_cg3100d.h
+F:	configs/netgear_cg3100d_ram_defconfig
board/netgear/cg3100d/Makefile new file +5 -0
new file mode 100644
index 0000000..b82e59e
@@ -0,0 +1,5 @@
+#
+# SPDX-License-Identifier:	GPL-2.0+
+#
+
+obj-y += cg3100d.o
board/netgear/cg3100d/cg3100d.c new file +7 -0
new file mode 100644
index 0000000..d181ca6
@@ -0,0 +1,7 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <common.h>
configs/netgear_cg3100d_ram_defconfig new file +56 -0

56 lines not on this page · raw message

include/configs/netgear_cg3100d.h new file +15 -0
new file mode 100644
index 0000000..c97d4e5
@@ -0,0 +1,15 @@
+/*
+ * Copyright (C) 2017 Álvaro Fernández Rojas <[email protected]>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#include <configs/bmips_common.h>
+#include <configs/bmips_bcm3380.h>
+
+#define CONFIG_ENV_IS_NOWHERE
+#define CONFIG_ENV_SIZE			(8 * 1024)
+
+#define CONFIG_AUTO_COMPLETE
+#define CONFIG_CMDLINE_EDITING
+#define CONFIG_SYS_LONGHELP
Signature · 1 line
2.1.4
#10 lore raw

PATCH v2 3/3 MIPS: add BMIPS Netgear CG3100D board

Quoted 14 lines · Álvaro Fernández Rojas
Signed-off-by Álvaro Fernández Rojas <[email protected]>

---
v2: introduce changes requested by Simon Glass:
- Add board description.

 arch/mips/dts/Makefile                |  1 +
 arch/mips/dts/netgear,cg3100d.dts     | 96 +++++++++++++++++++++++++++++++++++
 arch/mips/mach-bmips/Kconfig          | 12 +++++
 board/netgear/cg3100d/Kconfig         | 12 +++++
 board/netgear/cg3100d/MAINTAINERS     |  6 +++
 board/netgear/cg3100d/Makefile        |  5 ++
 board/netgear/cg3100d/cg3100d.c       |  7 +++
 configs/netgear_cg3100d_ram_defconfig | 56 ++++++++++++++++++++
 include/configs/netgear_cg3100d.h     | 15 ++++++
Quoted 8 lines
 9 files changed, 210 insertions(+)
 create mode 100644 arch/mips/dts/netgear,cg3100d.dts
 create mode 100644 board/netgear/cg3100d/Kconfig
 create mode 100644 board/netgear/cg3100d/MAINTAINERS
 create mode 100644 board/netgear/cg3100d/Makefile
 create mode 100644 board/netgear/cg3100d/cg3100d.c
 create mode 100644 configs/netgear_cg3100d_ram_defconfig
 create mode 100644 include/configs/netgear_cg3100d.h
Reviewed-by Simon Glass <[email protected]>
#11 lore raw

v2 cover mips: bmips: add BCM3380 SoC support

In reply to Álvaro Fernández Rojas

Am 16.05.2017 um 18:42 schrieb Álvaro Fernández Rojas:

Quoted 30 lines

BCM3380 is a dual core BCM33xx SoC, which means that it's pretty similar to the BCM63xx, but it's meant for HFC instead of xDSL.
The pll_conf register seems to be bugged, because it just stalls the SoC instead of performing a reboot, so the watchdog needs to be used as sysreset.

v2: Introduce changes requested by Simon Glass.

Álvaro Fernández Rojas (3):
dm: cpu: bmips: add BCM3380 support
MIPS: add support for Broadcom MIPS BCM3380 SoC family
MIPS: add BMIPS Netgear CG3100D board

 arch/mips/dts/Makefile                    |   1 +
 arch/mips/dts/brcm,bcm3380.dtsi           | 154 ++++++++++++++++++++++++++++++
 arch/mips/dts/netgear,cg3100d.dts         |  96 +++++++++++++++++++
 arch/mips/mach-bmips/Kconfig              |  24 +++++
 board/netgear/cg3100d/Kconfig             |  12 +++
 board/netgear/cg3100d/MAINTAINERS         |   6 ++
 board/netgear/cg3100d/Makefile            |   5 +
 board/netgear/cg3100d/cg3100d.c           |   7 ++
 configs/netgear_cg3100d_ram_defconfig     |  56 +++++++++++
 drivers/cpu/bmips_cpu.c                   |  14 +++
 include/configs/bmips_bcm3380.h           |  25 +++++
 include/configs/netgear_cg3100d.h         |  15 +++
 include/dt-bindings/clock/bcm3380-clock.h |  23 +++++
 include/dt-bindings/reset/bcm3380-reset.h |  16 ++++
 14 files changed, 454 insertions(+)
 create mode 100644 arch/mips/dts/brcm,bcm3380.dtsi
 create mode 100644 arch/mips/dts/netgear,cg3100d.dts
 create mode 100644 board/netgear/cg3100d/Kconfig
Quoted 9 lines
 create mode 100644 board/netgear/cg3100d/MAINTAINERS
 create mode 100644 board/netgear/cg3100d/Makefile
 create mode 100644 board/netgear/cg3100d/cg3100d.c
 create mode 100644 configs/netgear_cg3100d_ram_defconfig
 create mode 100644 include/configs/bmips_bcm3380.h
 create mode 100644 include/configs/netgear_cg3100d.h
 create mode 100644 include/dt-bindings/clock/bcm3380-clock.h
 create mode 100644 include/dt-bindings/reset/bcm3380-reset.h

series applied to u-boot-mips, thanks.

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