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Support ARMv7 architecture

PATCH Applied Jan Viktorin 6 participants 26 messages Nov 2, 2015 – Nov 18, 2015

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#0 lore raw

v6 cover Support ARMv7 architecture

Hello DPDK community,

ARMv7 again, changes:

* removed unnecessary code in the #ifndef RTE_FORCE_INTRINSICS .. #endif (atomic, spinlock, byteorder)
* more splitting of headers to have 32/64 bit variants (atomic, cpuflags)
* fixed cpuflags AT_PLATFORM

Other details in the individual commits as usual.

---

You can pull the changes from

https://github.com/RehiveTech/dpdk.git arm-support-v6

since commit 82fb702077f67585d64a07de0080e5cb6a924a72:

ixgbe: support new flow director modes for X550 (2015-10-29 00:06:01 +0100)

up to 9d686e4bd972dea2f9baef0a419a57a1c037d26e:

maintainers: claim responsibility for ARMv7 (2015-11-02 23:34:14 +0100)

---

Jan Viktorin (7):
eal/arm: implement rdtsc by PMU or clock_gettime eal/arm: use vector memcpy only when NEON is enabled eal/arm: detect arm architecture in cpu flags eal/arm: rwlock support for ARM
eal/arm: add very incomplete rte_vect gcc/arm: avoid alignment errors to break build
maintainers: claim responsibility for ARMv7

Vlastimil Kosar (8):
eal/arm: atomic operations for ARM eal/arm: byte order operations for ARM eal/arm: cpu cycle operations for ARM eal/arm: prefetch operations for ARM eal/arm: spinlock operations for ARM (without HTM) eal/arm: vector memcpy for ARM
eal/arm: cpu flag checks for ARM
mk: Introduce ARMv7 architecture

 MAINTAINERS                                        |   4 +
 app/test/test_cpuflags.c                           |   5 +
 config/defconfig_arm-armv7a-linuxapp-gcc           |  76 +++++
 doc/guides/rel_notes/release_2_2.rst               |   5 +
 .../common/include/arch/arm/rte_atomic.h           |  38 +++
 .../common/include/arch/arm/rte_atomic_32.h        |  74 +++++
 .../common/include/arch/arm/rte_byteorder.h        | 107 +++++++
 .../common/include/arch/arm/rte_cpuflags.h         |  38 +++
 .../common/include/arch/arm/rte_cpuflags_32.h      | 189 ++++++++++++
 .../common/include/arch/arm/rte_cycles.h           |  38 +++
 .../common/include/arch/arm/rte_cycles_32.h        | 121 ++++++++
 .../common/include/arch/arm/rte_memcpy.h           |  38 +++
 .../common/include/arch/arm/rte_memcpy_32.h        | 334 +++++++++++++++++++++
 .../common/include/arch/arm/rte_prefetch.h         |  38 +++
 .../common/include/arch/arm/rte_prefetch_32.h      |  61 ++++
 .../common/include/arch/arm/rte_rwlock.h           |  40 +++
 .../common/include/arch/arm/rte_spinlock.h         |  92 ++++++
 lib/librte_eal/common/include/arch/arm/rte_vect.h  |  84 ++++++
 mk/arch/arm/rte.vars.mk                            |  39 +++
 mk/machine/armv7-a/rte.vars.mk                     |  67 +++++
 mk/rte.cpuflags.mk                                 |   6 +
 mk/toolchain/gcc/rte.vars.mk                       |   6 +
 22 files changed, 1500 insertions(+)
 create mode 100644 config/defconfig_arm-armv7a-linuxapp-gcc
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_byteorder.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch_32.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_rwlock.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_spinlock.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_vect.h
 create mode 100644 mk/arch/arm/rte.vars.mk
 create mode 100644 mk/machine/armv7-a/rte.vars.mk
Signature · 1 line
2.6.2
#1 lore raw

PATCH v6 1/15 eal/arm: atomic operations for ARM

From: Vlastimil Kosar <[email protected]>

This patch adds architecture specific atomic operation file for ARM architecture. The RTE_FORCE_INTRINSICS=y is required.

---
v1 -> v2:
* improve rte_wmb()
* use __atomic_* or __sync_*? (may affect the required GCC version)

v4:
* checkpatch complaints about volatile keyword (but seems to be OK to me)
* checkpatch complaints about do { ... } while (0) for single statement with asm volatile (but I didn't find a way how to write it without the checkpatch complaints)
* checkpatch is now happy with whitespaces

v6:
* separate for 32/64 architectures
* drop the atomic implementation and require to use RTE_FORCE_INTRINSICS

---
 .../common/include/arch/arm/rte_atomic.h           | 38 +++++++++++
 .../common/include/arch/arm/rte_atomic_32.h        | 74 ++++++++++++++++++++++
 2 files changed, 112 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
lib/librte_eal/common/include/arch/arm/rte_atomic.h new file +38 -0
new file mode 100644
index 0000000..f4f5783
@@ -0,0 +1,38 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of RehiveTech nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_ATOMIC_ARM_H_
+#define _RTE_ATOMIC_ARM_H_
+
+#include <rte_atomic_32.h>
+
+#endif /* _RTE_ATOMIC_ARM_H_ */
lib/librte_eal/common/include/arch/arm/rte_atomic_32.h new file +74 -0

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Signature · 1 line
2.6.2
#2 lore raw

PATCH v6 2/15 eal/arm: byte order operations for ARM

In reply to Jan Viktorin

From: Vlastimil Kosar <[email protected]>

This patch adds architecture specific byte order operations for ARM. The architecture supports both big and little endian. It requires RTE_FORCE_INTRINSICS=y.

---
v4: fix passing params to asm volatile for checkpatch

v6: disable intrinsics, however, fix the bswap16 in older GCC

---
 .../common/include/arch/arm/rte_byteorder.h        | 107 +++++++++++++++++++++
 1 file changed, 107 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_byteorder.h
lib/librte_eal/common/include/arch/arm/rte_byteorder.h new file +107 -0
new file mode 100644
index 0000000..3f2dd1f
@@ -0,0 +1,107 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of RehiveTech nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_BYTEORDER_ARM_H_
+#define _RTE_BYTEORDER_ARM_H_
+
+#ifndef RTE_FORCE_INTRINSICS
+#  error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_byteorder.h"
+
+/* fix missing __builtin_bswap16 for gcc older then 4.8 */
+#if !(__GNUC__ > 4 || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8))
+
+static inline uint16_t rte_arch_bswap16(uint16_t _x)
+{
+	register uint16_t x = _x;
+
+	asm volatile ("rev16 %0,%1"
+		      : "=r" (x)
+		      : "r" (x)
+		      );
+	return x;
+}
+
+#define rte_bswap16(x) ((uint16_t)(__builtin_constant_p(x) ? \
+				   rte_constant_bswap16(x) : \
+				   rte_arch_bswap16(x)))
+#endif
+
+/* ARM architecture is bi-endian (both big and little). */
+#if RTE_BYTE_ORDER == RTE_LITTLE_ENDIAN
+
+#define rte_cpu_to_le_16(x) (x)
+#define rte_cpu_to_le_32(x) (x)
+#define rte_cpu_to_le_64(x) (x)
+
+#define rte_cpu_to_be_16(x) rte_bswap16(x)
+#define rte_cpu_to_be_32(x) rte_bswap32(x)
+#define rte_cpu_to_be_64(x) rte_bswap64(x)
+
+#define rte_le_to_cpu_16(x) (x)
+#define rte_le_to_cpu_32(x) (x)
+#define rte_le_to_cpu_64(x) (x)
+
+#define rte_be_to_cpu_16(x) rte_bswap16(x)
+#define rte_be_to_cpu_32(x) rte_bswap32(x)
+#define rte_be_to_cpu_64(x) rte_bswap64(x)
+
+#else /* RTE_BIG_ENDIAN */
+
+#define rte_cpu_to_le_16(x) rte_bswap16(x)
+#define rte_cpu_to_le_32(x) rte_bswap32(x)
+#define rte_cpu_to_le_64(x) rte_bswap64(x)
+
+#define rte_cpu_to_be_16(x) (x)
+#define rte_cpu_to_be_32(x) (x)
+#define rte_cpu_to_be_64(x) (x)
+
+#define rte_le_to_cpu_16(x) rte_bswap16(x)
+#define rte_le_to_cpu_32(x) rte_bswap32(x)
+#define rte_le_to_cpu_64(x) rte_bswap64(x)
+
+#define rte_be_to_cpu_16(x) (x)
+#define rte_be_to_cpu_32(x) (x)
+#define rte_be_to_cpu_64(x) (x)
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_BYTEORDER_ARM_H_ */
Signature · 1 line
2.6.2
#3 lore raw

PATCH v6 3/15 eal/arm: cpu cycle operations for ARM

In reply to Jan Viktorin

From: Vlastimil Kosar <[email protected]>

ARM architecture doesn't have a suitable source of CPU cycles. This patch uses clock_gettime instead. The implementation should be improved in the future.

---
v5: prepare for applying ARMv8

---
 .../common/include/arch/arm/rte_cycles.h           | 38 ++++++++++
 .../common/include/arch/arm/rte_cycles_32.h        | 85 ++++++++++++++++++++++
 2 files changed, 123 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
lib/librte_eal/common/include/arch/arm/rte_cycles.h new file +38 -0
new file mode 100644
index 0000000..b2372fa
@@ -0,0 +1,38 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of RehiveTech nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_CYCLES_ARM_H_
+#define _RTE_CYCLES_ARM_H_
+
+#include <rte_cycles_32.h>
+
+#endif /* _RTE_CYCLES_ARM_H_ */
lib/librte_eal/common/include/arch/arm/rte_cycles_32.h new file +85 -0

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Signature · 1 line
2.6.2
#4 lore raw

PATCH v6 4/15 eal/arm: implement rdtsc by PMU or clock_gettime

In reply to Jan Viktorin

Enable to choose a preferred way to read timer based on the configuration entry CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU. It requires a kernel module that is not included to work.

Based on the patch by David Hunt and Armuta Zende:

lib: added support for armv7 architecture

---
 .../common/include/arch/arm/rte_cycles_32.h        | 38 +++++++++++++++++++++-
 1 file changed, 37 insertions(+), 1 deletion(-)
lib/librte_eal/common/include/arch/arm/rte_cycles_32.h +37 -1
index 755cc4a..6c6098e 100644
@@ -54,8 +54,14 @@ extern "C" {
  * @return
  *   The time base for this lcore.
  */
+#ifndef CONFIG_RTE_ARM_EAL_RDTSC_USE_PMU
+
+/**
+ * This call is easily portable to any ARM architecture, however,
+ * it may be damn slow and inprecise for some tasks.
+ */
 static inline uint64_t
-rte_rdtsc(void)
+__rte_rdtsc_syscall(void)
 {
 	struct timespec val;
 	uint64_t v;
@@ -67,6 +73,36 @@ rte_rdtsc(void)
 	v += (uint64_t) val.tv_nsec;
 	return v;
 }
+#define rte_rdtsc __rte_rdtsc_syscall
+
+#else
+
+/**
+ * This function requires to configure the PMCCNTR and enable
+ * userspace access to it:
+ *
+ *      asm volatile("mcr p15, 0, %0, c9, c14, 0" : : "r"(1));
+ *      asm volatile("mcr p15, 0, %0, c9, c12, 0" : : "r"(29));
+ *      asm volatile("mcr p15, 0, %0, c9, c12, 1" : : "r"(0x8000000f));
+ *
+ * which is possible only from the priviledged mode (kernel space).
+ */
+static inline uint64_t
+__rte_rdtsc_pmccntr(void)
+{
+	unsigned tsc;
+	uint64_t final_tsc;
+
+	/* Read PMCCNTR */
+	asm volatile("mrc p15, 0, %0, c9, c13, 0" : "=r"(tsc));
+	/* 1 tick = 64 clocks */
+	final_tsc = ((uint64_t)tsc) << 6;
+
+	return (uint64_t)final_tsc;
+}
+#define rte_rdtsc __rte_rdtsc_pmccntr
+
+#endif /* RTE_ARM_EAL_RDTSC_USE_PMU */
 
 static inline uint64_t
 rte_rdtsc_precise(void)
Signature · 1 line
2.6.2
#5 lore raw

PATCH v6 5/15 eal/arm: prefetch operations for ARM

In reply to Jan Viktorin

From: Vlastimil Kosar <[email protected]>

This patch adds architecture specific prefetch operations for ARM architecture. It utilizes the pld instruction that starts filling the appropriate cache line without blocking.

---
v4:
* checkpatch does not like the syntax of naming params to asm volatile; switched to %0, %1 syntax
* checkpatch complatins about volatile (seems to be OK for me)

v5: prepare for applying ARMv8

---
 .../common/include/arch/arm/rte_prefetch.h         | 38 ++++++++++++++
 .../common/include/arch/arm/rte_prefetch_32.h      | 61 ++++++++++++++++++++++
 2 files changed, 99 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch_32.h
lib/librte_eal/common/include/arch/arm/rte_prefetch.h new file +38 -0
new file mode 100644
index 0000000..1f46697
@@ -0,0 +1,38 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of RehiveTech nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_PREFETCH_ARM_H_
+#define _RTE_PREFETCH_ARM_H_
+
+#include <rte_prefetch_32.h>
+
+#endif /* _RTE_PREFETCH_ARM_H_ */
lib/librte_eal/common/include/arch/arm/rte_prefetch_32.h new file +61 -0

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Signature · 1 line
2.6.2
#6 lore raw

PATCH v6 6/15 eal/arm: spinlock operations for ARM (without HTM)

In reply to Jan Viktorin

From: Vlastimil Kosar <[email protected]>

This patch adds spinlock operations for ARM architecture. We do not support HTM in spinlocks on ARM. Setting of the RTE_FORCE_INTRINSICS=y is required.

---
v6: use builtin intrinsics implementation

---
 .../common/include/arch/arm/rte_spinlock.h         | 92 ++++++++++++++++++++++
 1 file changed, 92 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_spinlock.h
lib/librte_eal/common/include/arch/arm/rte_spinlock.h new file +92 -0
new file mode 100644
index 0000000..396a42e
@@ -0,0 +1,92 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of RehiveTech nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_SPINLOCK_ARM_H_
+#define _RTE_SPINLOCK_ARM_H_
+
+#ifndef RTE_FORCE_INTRINSICS
+#  error Platform must be built with CONFIG_RTE_FORCE_INTRINSICS
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <rte_common.h>
+#include "generic/rte_spinlock.h"
+
+static inline int rte_tm_supported(void)
+{
+	return 0;
+}
+
+static inline void
+rte_spinlock_lock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_lock(sl); /* fall-back */
+}
+
+static inline int
+rte_spinlock_trylock_tm(rte_spinlock_t *sl)
+{
+	return rte_spinlock_trylock(sl);
+}
+
+static inline void
+rte_spinlock_unlock_tm(rte_spinlock_t *sl)
+{
+	rte_spinlock_unlock(sl);
+}
+
+static inline void
+rte_spinlock_recursive_lock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_lock(slr); /* fall-back */
+}
+
+static inline void
+rte_spinlock_recursive_unlock_tm(rte_spinlock_recursive_t *slr)
+{
+	rte_spinlock_recursive_unlock(slr);
+}
+
+static inline int
+rte_spinlock_recursive_trylock_tm(rte_spinlock_recursive_t *slr)
+{
+	return rte_spinlock_recursive_trylock(slr);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_SPINLOCK_ARM_H_ */
Signature · 1 line
2.6.2
#7 lore raw

PATCH v6 7/15 eal/arm: vector memcpy for ARM

In reply to Jan Viktorin

From: Vlastimil Kosar <[email protected]>

The SSE based memory copy in DPDK only support x86. This patch adds ARM NEON based memory copy functions for ARM architecture.

The implementation improves memory copy of short or well aligned data buffers. The following measurements show improvements over the libc memcpy on Cortex CPUs.

by X % faster
Length (B) a15 a7 a9

   1         4.9  15.2    3.2
   7        56.9  48.2   40.3
   8        37.3  39.8   29.6
   9        69.3  38.7   33.9
  15        60.8  35.3   23.7
  16        50.6  35.9   35.0
  17        57.7  35.7   31.1
  31        16.0  23.3    9.0
  32        65.9  13.5   21.4
  33         3.9  10.3   -3.7
  63         2.0  12.9   -2.0
  64        66.5   0.0   16.5
  65         2.7   7.6  -35.6
 127         0.1   4.5  -18.9
 128        66.2   1.5  -51.4
 129        -0.8   3.2  -35.8
 255        -3.1  -0.9  -69.1
 256        67.9   1.2    7.2
 257        -3.6  -1.9  -36.9
 320        67.7   1.4    0.0
 384        66.8   1.4  -14.2
 511       -44.9  -2.3  -41.9
 512        67.3   1.4   -6.8
 513       -41.7  -3.0  -36.2
1023       -82.4  -2.8  -41.2
1024        68.3   1.4  -11.6
1025       -80.1  -3.3  -38.1
1518       -47.3  -5.0  -38.3
1522       -48.3  -6.0  -37.9
1600        65.4   1.3  -27.3
2048        59.5   1.5  -10.9
3072        52.3   1.5  -12.2
4096        45.3   1.4  -12.5
5120        40.6   1.5  -14.5
6144        35.4   1.4  -13.4
7168        32.9   1.4  -13.9
8192        28.2   1.4  -15.1

---
v4:
* fix whitespace issues reported by checkpatch
* fix passing params to asm volatile for checkpatch

v5: prepare for applying ARMv8

---
 .../common/include/arch/arm/rte_memcpy.h           |  38 +++
 .../common/include/arch/arm/rte_memcpy_32.h        | 279 +++++++++++++++++++++
 2 files changed, 317 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h
lib/librte_eal/common/include/arch/arm/rte_memcpy.h new file +38 -0
new file mode 100644
index 0000000..d9f5bf1
@@ -0,0 +1,38 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of RehiveTech nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_MEMCPY_ARM_H_
+#define _RTE_MEMCPY_ARM_H_
+
+#include <rte_memcpy_32.h>
+
+#endif /* _RTE_MEMCPY_ARM_H_ */
lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h new file +279 -0

279 lines not on this page · raw message

Signature · 1 line
2.6.2
#8 lore raw

PATCH v6 8/15 eal/arm: use vector memcpy only when NEON is enabled

In reply to Jan Viktorin

The GCC can be configured to avoid using NEON extensions. For that purpose, we provide just the memcpy implementation of the rte_memcpy.

Based on the patch by David Hunt and Armuta Zende:

lib: added support for armv7 architecture

---
v5: prepare for applying ARMv8

---
 .../common/include/arch/arm/rte_memcpy_32.h        | 59 +++++++++++++++++++++-
 1 file changed, 57 insertions(+), 2 deletions(-)
lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h +57 -2
index 11f8241..df47c0d 100644
@@ -35,8 +35,6 @@
 
 #include <stdint.h>
 #include <string.h>
-/* ARM NEON Intrinsics are used to copy data */
-#include <arm_neon.h>
 
 #ifdef __cplusplus
 extern "C" {
@@ -44,6 +42,11 @@ extern "C" {
 
 #include "generic/rte_memcpy.h"
 
+#ifdef __ARM_NEON_FP
+
+/* ARM NEON Intrinsics are used to copy data */
+#include <arm_neon.h>
+
 static inline void
 rte_mov16(uint8_t *dst, const uint8_t *src)
 {
@@ -272,6 +275,58 @@ rte_memcpy_func(void *dst, const void *src, size_t n)
 	return ret;
 }
 
+#else
+
+static inline void
+rte_mov16(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 16);
+}
+
+static inline void
+rte_mov32(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 32);
+}
+
+static inline void
+rte_mov48(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 48);
+}
+
+static inline void
+rte_mov64(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 64);
+}
+
+static inline void
+rte_mov128(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 128);
+}
+
+static inline void
+rte_mov256(uint8_t *dst, const uint8_t *src)
+{
+	memcpy(dst, src, 256);
+}
+
+static inline void *
+rte_memcpy(void *dst, const void *src, size_t n)
+{
+	return memcpy(dst, src, n);
+}
+
+static inline void *
+rte_memcpy_func(void *dst, const void *src, size_t n)
+{
+	return memcpy(dst, src, n);
+}
+
+#endif /* __ARM_NEON_FP */
+
 #ifdef __cplusplus
 }
 #endif
Signature · 1 line
2.6.2
#9 lore raw

PATCH v6 9/15 eal/arm: cpu flag checks for ARM

In reply to Jan Viktorin

From: Vlastimil Kosar <[email protected]>

This implementation is based on IBM POWER version of rte_cpuflags. We use software emulation of HW capability registers, because those are usually not directly accessible from userspace on ARM.

---
v6: separate 32/64 architectures

---
 app/test/test_cpuflags.c                           |   5 +
 .../common/include/arch/arm/rte_cpuflags.h         |  38 +++++
 .../common/include/arch/arm/rte_cpuflags_32.h      | 177 +++++++++++++++++++++
 mk/rte.cpuflags.mk                                 |   6 +
 4 files changed, 226 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h
app/test/test_cpuflags.c +5 -0
index 5b92061..557458f 100644
@@ -115,6 +115,11 @@ test_cpuflags(void)
 	CHECK_FOR_FLAG(RTE_CPUFLAG_ICACHE_SNOOP);
 #endif
 
+#if defined(RTE_ARCH_ARM)
+	printf("Check for NEON:\t\t");
+	CHECK_FOR_FLAG(RTE_CPUFLAG_NEON);
+#endif
+
 #if defined(RTE_ARCH_X86_64) || defined(RTE_ARCH_I686)
 	printf("Check for SSE:\t\t");
 	CHECK_FOR_FLAG(RTE_CPUFLAG_SSE);
lib/librte_eal/common/include/arch/arm/rte_cpuflags.h new file +38 -0
new file mode 100644
index 0000000..8de78d2
@@ -0,0 +1,38 @@
+/*
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of RehiveTech nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_CPUFLAGS_ARM_H_
+#define _RTE_CPUFLAGS_ARM_H_
+
+#include <rte_cpuflags_32.h>
+
+#endif /* _RTE_CPUFLAGS_ARM_H_ */
lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h new file +177 -0

177 lines not on this page · raw message

mk/rte.cpuflags.mk +6 -0
index f595cd0..bec7bdd 100644
@@ -106,6 +106,12 @@ ifneq ($(filter $(AUTO_CPUFLAGS),__builtin_vsx_xvnmaddadp),)
 CPUFLAGS += VSX
 endif
 
+# ARM flags
+ifneq ($(filter $(AUTO_CPUFLAGS),__ARM_NEON_FP),)
+CPUFLAGS += NEON
+endif
+
+
 MACHINE_CFLAGS += $(addprefix -DRTE_MACHINE_CPUFLAG_,$(CPUFLAGS))
 
 # To strip whitespace
Signature · 1 line
2.6.2
#10 lore raw

PATCH v6 10/15 eal/arm: detect arm architecture in cpu flags

In reply to Jan Viktorin

Based on the patch by David Hunt and Armuta Zende:

lib: added support for armv7 architecture

---
v2 -> v3: fixed forgotten include of string.h
v4: checkpatch reports few characters over 80 for checking aarch64
v6: drop checking of "aarch32/64" (invalid for armv7),
check for "v7l" string instead

---
 lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)
lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h +12 -0
index 3280817..2106c41 100644
@@ -41,6 +41,7 @@ extern "C" {
 #include <fcntl.h>
 #include <assert.h>
 #include <unistd.h>
+#include <string.h>
 
 #include "generic/rte_cpuflags.h"
 
@@ -52,10 +53,15 @@ extern "C" {
 #define AT_HWCAP2 26
 #endif
 
+#ifndef AT_PLATFORM
+#define AT_PLATFORM 15
+#endif
+
 /* software based registers */
 enum cpu_register_t {
 	REG_HWCAP = 0,
 	REG_HWCAP2,
+	REG_PLATFORM,
 };
 
 /**
@@ -89,6 +95,7 @@ enum rte_cpu_flag_t {
 	RTE_CPUFLAG_SHA1,
 	RTE_CPUFLAG_SHA2,
 	RTE_CPUFLAG_CRC32,
+	RTE_CPUFLAG_V7L,
 	/* The last item */
 	RTE_CPUFLAG_NUMFLAGS,/**< This should always be the last! */
 };
@@ -121,6 +128,7 @@ static const struct feature_entry cpu_feature_table[] = {
 	FEAT_DEF(SHA1,      0x00000001, 0, REG_HWCAP2,  2)
 	FEAT_DEF(SHA2,      0x00000001, 0, REG_HWCAP2,  3)
 	FEAT_DEF(CRC32,     0x00000001, 0, REG_HWCAP2,  4)
+	FEAT_DEF(V7L,       0x00000001, 0, REG_PLATFORM, 0)
 };
 
 /*
@@ -141,6 +149,10 @@ rte_cpu_get_features(__attribute__((unused)) uint32_t leaf,
 			out[REG_HWCAP] = auxv.a_un.a_val;
 		else if (auxv.a_type == AT_HWCAP2)
 			out[REG_HWCAP2] = auxv.a_un.a_val;
+		else if (auxv.a_type == AT_PLATFORM) {
+			if (!strcmp((const char *)auxv.a_un.a_val, "v7l"))
+				out[REG_PLATFORM] = 0x0001;
+		}
 	}
 }
 
Signature · 1 line
2.6.2
#11 lore raw

PATCH v6 11/15 eal/arm: rwlock support for ARM

In reply to Jan Viktorin

Just a copy from PPC.

---
 .../common/include/arch/arm/rte_rwlock.h           | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_rwlock.h
lib/librte_eal/common/include/arch/arm/rte_rwlock.h new file +40 -0
new file mode 100644
index 0000000..664bec8
@@ -0,0 +1,40 @@
+/* copied from ppc_64 */
+
+#ifndef _RTE_RWLOCK_ARM_H_
+#define _RTE_RWLOCK_ARM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "generic/rte_rwlock.h"
+
+static inline void
+rte_rwlock_read_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_lock(rwl);
+}
+
+static inline void
+rte_rwlock_read_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_read_unlock(rwl);
+}
+
+static inline void
+rte_rwlock_write_lock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_lock(rwl);
+}
+
+static inline void
+rte_rwlock_write_unlock_tm(rte_rwlock_t *rwl)
+{
+	rte_rwlock_write_unlock(rwl);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _RTE_RWLOCK_ARM_H_ */
Signature · 1 line
2.6.2
#12 lore raw

PATCH v6 12/15 eal/arm: add very incomplete rte_vect

In reply to Jan Viktorin

This patch does not map x86 SIMD operations to the ARM ones. It just fills the necessary gap between the platforms to enable compilation of libraries LPM (includes rte_vect.h, lpm_test needs those SIMD functions) and ACL (includes rte_vect.h).

---
v4: checkpatch reports warning for the new typedef

---
 lib/librte_eal/common/include/arch/arm/rte_vect.h | 84 +++++++++++++++++++++++
 1 file changed, 84 insertions(+)
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_vect.h
lib/librte_eal/common/include/arch/arm/rte_vect.h new file +84 -0
new file mode 100644
index 0000000..7d5de97
@@ -0,0 +1,84 @@
+/*-
+ *   BSD LICENSE
+ *
+ *   Copyright(c) 2015 RehiveTech. All rights reserved.
+ *
+ *   Redistribution and use in source and binary forms, with or without
+ *   modification, are permitted provided that the following conditions
+ *   are met:
+ *
+ *     * Redistributions of source code must retain the above copyright
+ *       notice, this list of conditions and the following disclaimer.
+ *     * Redistributions in binary form must reproduce the above copyright
+ *       notice, this list of conditions and the following disclaimer in
+ *       the documentation and/or other materials provided with the
+ *       distribution.
+ *     * Neither the name of RehiveTech nor the names of its
+ *       contributors may be used to endorse or promote products derived
+ *       from this software without specific prior written permission.
+ *
+ *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#ifndef _RTE_VECT_ARM_H_
+#define _RTE_VECT_ARM_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define XMM_SIZE 16
+#define XMM_MASK (XMM_MASK - 1)
+
+typedef struct {
+	union uint128 {
+		uint8_t uint8[16];
+		uint32_t uint32[4];
+	} val;
+} __m128i;
+
+static inline __m128i
+_mm_set_epi32(uint32_t v0, uint32_t v1, uint32_t v2, uint32_t v3)
+{
+	__m128i res;
+
+	res.val.uint32[0] = v0;
+	res.val.uint32[1] = v1;
+	res.val.uint32[2] = v2;
+	res.val.uint32[3] = v3;
+	return res;
+}
+
+static inline __m128i
+_mm_loadu_si128(__m128i *v)
+{
+	__m128i res;
+
+	res = *v;
+	return res;
+}
+
+static inline __m128i
+_mm_load_si128(__m128i *v)
+{
+	__m128i res;
+
+	res = *v;
+	return res;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
Signature · 1 line
2.6.2
#13 lore raw

PATCH v6 13/15 gcc/arm: avoid alignment errors to break build

In reply to Jan Viktorin

There several issues with alignment when compiling for ARMv7. They are not considered to be fatal (ARMv7 supports unaligned access of 32b words), so we just leave them as warnings. They should be solved later, however.

---
v4: restrict -Wno-error to the cast-align only

---
 mk/toolchain/gcc/rte.vars.mk | 6 ++++++
 1 file changed, 6 insertions(+)
mk/toolchain/gcc/rte.vars.mk +6 -0
index 0f51c66..c2c5255 100644
@@ -77,6 +77,12 @@ WERROR_FLAGS += -Wcast-align -Wnested-externs -Wcast-qual
 WERROR_FLAGS += -Wformat-nonliteral -Wformat-security
 WERROR_FLAGS += -Wundef -Wwrite-strings
 
+# There are many issues reported for ARMv7 architecture
+# which are not necessarily fatal. Report as warnings.
+ifeq ($(CONFIG_RTE_ARCH_ARMv7),y)
+WERROR_FLAGS += -Wno-error=cast-align
+endif
+
 # process cpu flags
 include $(RTE_SDK)/mk/toolchain/$(RTE_TOOLCHAIN)/rte.toolchain-compat.mk
 
Signature · 1 line
2.6.2
#14 lore raw

PATCH v6 14/15 mk: Introduce ARMv7 architecture

In reply to Jan Viktorin

From: Vlastimil Kosar <[email protected]>

Make DPDK run on ARMv7-A architecture. This patch assumes ARM Cortex-A9. However, it is known to be working on Cortex-A7 and Cortex-A15.

---
v2:
* the -mtune parameter of GCC is configurable now
* the -mfpu=neon can be turned off

v3: XMM_SIZE is defined in rte_vect.h in a following patch

v4:
* update release notes for 2.2
* get rid of CONFIG_RTE_BITMAP_OPTIMIZATIONS=0 setting
* rename arm defconfig: "armv7-a" -> "arvm7a"
* disable pipeline and table modules unless lpm is fixed

---
 config/defconfig_arm-armv7a-linuxapp-gcc | 76 ++++++++++++++++++++++++++++++++
 doc/guides/rel_notes/release_2_2.rst     |  5 +++
 mk/arch/arm/rte.vars.mk                  | 39 ++++++++++++++++
 mk/machine/armv7-a/rte.vars.mk           | 67 ++++++++++++++++++++++++++++
 4 files changed, 187 insertions(+)
 create mode 100644 config/defconfig_arm-armv7a-linuxapp-gcc
 create mode 100644 mk/arch/arm/rte.vars.mk
 create mode 100644 mk/machine/armv7-a/rte.vars.mk
config/defconfig_arm-armv7a-linuxapp-gcc new file +76 -0
new file mode 100644
index 0000000..82143af
@@ -0,0 +1,76 @@
+#   BSD LICENSE
+#
+#   Copyright (C) 2015 RehiveTech. All right reserved.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of RehiveTech nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+#include "common_linuxapp"
+
+CONFIG_RTE_MACHINE="armv7-a"
+
+CONFIG_RTE_ARCH="arm"
+CONFIG_RTE_ARCH_ARM=y
+CONFIG_RTE_ARCH_ARMv7=y
+CONFIG_RTE_ARCH_ARM_TUNE="cortex-a9"
+CONFIG_RTE_ARCH_ARM_NEON=y
+
+CONFIG_RTE_FORCE_INTRINSICS=y
+
+CONFIG_RTE_TOOLCHAIN="gcc"
+CONFIG_RTE_TOOLCHAIN_GCC=y
+
+# ARM doesn't have support for vmware TSC map
+CONFIG_RTE_LIBRTE_EAL_VMWARE_TSC_MAP_SUPPORT=n
+
+# KNI is not supported on 32-bit
+CONFIG_RTE_LIBRTE_KNI=n
+
+# PCI is usually not used on ARM
+CONFIG_RTE_EAL_IGB_UIO=n
+
+# fails to compile on ARM
+CONFIG_RTE_LIBRTE_ACL=n
+CONFIG_RTE_LIBRTE_LPM=n
+CONFIG_RTE_LIBRTE_TABLE=n
+CONFIG_RTE_LIBRTE_PIPELINE=n
+
+# cannot use those on ARM
+CONFIG_RTE_KNI_KMOD=n
+CONFIG_RTE_LIBRTE_EM_PMD=n
+CONFIG_RTE_LIBRTE_IGB_PMD=n
+CONFIG_RTE_LIBRTE_CXGBE_PMD=n
+CONFIG_RTE_LIBRTE_E1000_PMD=n
+CONFIG_RTE_LIBRTE_ENIC_PMD=n
+CONFIG_RTE_LIBRTE_FM10K_PMD=n
+CONFIG_RTE_LIBRTE_I40E_PMD=n
+CONFIG_RTE_LIBRTE_IXGBE_PMD=n
+CONFIG_RTE_LIBRTE_MLX4_PMD=n
+CONFIG_RTE_LIBRTE_MPIPE_PMD=n
+CONFIG_RTE_LIBRTE_VIRTIO_PMD=n
+CONFIG_RTE_LIBRTE_VMXNET3_PMD=n
+CONFIG_RTE_LIBRTE_PMD_XENVIRT=n
+CONFIG_RTE_LIBRTE_PMD_BNX2X=n
doc/guides/rel_notes/release_2_2.rst +5 -0
index be6f827..43a3a3c 100644
@@ -23,6 +23,11 @@ New Features
 
 * **Added vhost-user multiple queue support.**
 
+* **Introduce ARMv7 architecture**
+
+  It is now possible to build DPDK for the ARMv7 platform and test with
+  virtual PMD drivers.
+
 
 Resolved Issues
 ---------------
mk/arch/arm/rte.vars.mk new file +39 -0
new file mode 100644
index 0000000..df0c043
@@ -0,0 +1,39 @@
+#   BSD LICENSE
+#
+#   Copyright (C) 2015 RehiveTech. All rights reserved.
+#
+#   Redistribution and use in source and binary forms, with or without
+#   modification, are permitted provided that the following conditions
+#   are met:
+#
+#     * Redistributions of source code must retain the above copyright
+#       notice, this list of conditions and the following disclaimer.
+#     * Redistributions in binary form must reproduce the above copyright
+#       notice, this list of conditions and the following disclaimer in
+#       the documentation and/or other materials provided with the
+#       distribution.
+#     * Neither the name of RehiveTech nor the names of its
+#       contributors may be used to endorse or promote products derived
+#       from this software without specific prior written permission.
+#
+#   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+#   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+#   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+#   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+#   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+#   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+#   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+#   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+#   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+#   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+#   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+
+ARCH  ?= arm
+CROSS ?=
+
+CPU_CFLAGS  ?= -marm -DRTE_CACHE_LINE_SIZE=64 -munaligned-access
+CPU_LDFLAGS ?=
+CPU_ASFLAGS ?= -felf
+
+export ARCH CROSS CPU_CFLAGS CPU_LDFLAGS CPU_ASFLAGS
mk/machine/armv7-a/rte.vars.mk new file +67 -0

67 lines not on this page · raw message

Signature · 1 line
2.6.2
#15 lore raw

Re: [PATCH v6 14/15] mk: Introduce ARMv7 architecture

On 02/11/2015 23:47, Jan Viktorin wrote:
--snip--

doc/guides/rel_notes/release_2_2.rst New Features · line 24

Quoted 7 lines
doc/guides/rel_notes/release_2_2.rst +0 -0
index be6f827..43a3a3c 100644
@@ -23,6 +23,11 @@ New Features
 
  * **Added vhost-user multiple queue support.**

Jan,
There's a small issue here. To apply cleanly on the latest head, this line needs to be
* **Added port hotplug support to xenvirt.**

Rgds,
Dave.

#16 lore raw

Re: [PATCH v6 14/15] mk: Introduce ARMv7 architecture

Quoted 15 lines · David

On 02/11/2015 23:47, Jan Viktorin wrote:
--snip--

doc/guides/rel_notes/release_2_2.rst New Features · line 24

Quoted 7 lines
doc/guides/rel_notes/release_2_2.rst +0 -0
index be6f827..43a3a3c 100644
@@ -23,6 +23,11 @@ New Features
 
 * **Added vhost-user multiple queue support.**

Jan,
There's a small issue here. To apply cleanly on the latest head, this line needs to be
* **Added port hotplug support to xenvirt.**

Quoted 2 lines

Rgds,
Dave.

The release notes "New Feature" section is always one that causes conflicts on apply of patches. I think Thomas is ok to handle that on apply, or else we'd all be constantly rebasing.

For 2.3 we maybe need to come up with a new way to modify this to make applying patches easier. For example, can the new features section just be pulled from a set of individual single-bullet-point files inside a directory? Then each new feature just drops its addition in a new file and there are no conflicts. Can rst be used to pull into a doc a directory: e.g. "new_features/*.rst"?

/Bruce

#17 lore raw

Re: [PATCH v6 14/15] mk: Introduce ARMv7 architecture

2015-11-03 10:24, Bruce Richardson:

Quoted 3 lines

The release notes "New Feature" section is always one that causes conflicts on apply of patches. I think Thomas is ok to handle that on apply, or else we'd all be constantly rebasing.

Yes, it is a common conflict managed when applying.

Quoted 5 lines

For 2.3 we maybe need to come up with a new way to modify this to make applying patches easier. For example, can the new features section just be pulled from a set of individual single-bullet-point files inside a directory? Then each new feature just drops its addition in a new file and there are no conflicts. Can rst be used to pull into a doc a directory: e.g. "new_features/*.rst"?

Good idea.
But we should try to have some automatic sorting in the list.

#18 lore raw

Re: [PATCH v6 14/15] mk: Introduce ARMv7 architecture

In reply to Hunt, David
Quoted 8 lines · David

On 02/11/2015 23:47, Jan Viktorin wrote:
--snip--

Quoted 6 lines
doc/guides/rel_notes/release_2_2.rst +0 -0
index be6f827..43a3a3c 100644
@@ -23,6 +23,11 @@ New Features
 
Quoted 6 lines

doc/guides/rel_notes/release_2_2.rst New Features · line 24

Quoted 1 line
doc/guides/rel_notes/release_2_2.rst +0 -0
  * **Added vhost-user multiple queue support.**  

Jan,
There's a small issue here. To apply cleanly on the latest head, this line needs to be
* **Added port hotplug support to xenvirt.**

Yes, the original v6 patchset was rebased on 82fb70207 (as stated in the cover letter). I've force pushed an update (as resubmitting all the series just due to this trivial conflict seems to be meaningless to me):

You can pull the changes from 647d1eaf758b97311ab3692770acac72144eea87:

https://github.com/RehiveTech/dpdk.git arm-support-v6

since commit :

i40evf: support AQ based RSS config (2015-11-03 11:13:32 +0100)

up to 46dcc0857d7a5c760e6ec991906619351618f290:

maintainers: claim responsibility for ARMv7 (2015-11-03 11:18:56 +0100)

Quoted 3 lines

Rgds,
Dave.

Signature · 4 lines
  Jan Viktorin                E-mail: [email protected]
  System Architect            Web:    www.RehiveTech.com
  RehiveTech
  Brno, Czech Republic
#19 lore raw

Re: [PATCH v6 14/15] mk: Introduce ARMv7 architecture

Quoted 18 lines · Jan Viktorin
Quoted 8 lines · David

On 02/11/2015 23:47, Jan Viktorin wrote:
--snip--

Quoted 6 lines
doc/guides/rel_notes/release_2_2.rst +0 -0
index be6f827..43a3a3c 100644
@@ -23,6 +23,11 @@ New Features
 
Quoted 6 lines

doc/guides/rel_notes/release_2_2.rst New Features · line 24

Quoted 1 line
doc/guides/rel_notes/release_2_2.rst +0 -0
   * **Added vhost-user multiple queue support.**

Jan,
There's a small issue here. To apply cleanly on the latest head, this line needs to be
* **Added port hotplug support to xenvirt.**

Quoted 3 lines

Yes, the original v6 patchset was rebased on 82fb70207 (as stated in the cover letter). I've force pushed an update (as resubmitting all the series just due to this trivial conflict seems to be meaningless to me):

Agreed, just noting for the future :)

Dave

#20 lore raw

PATCH v6 15/15 maintainers: claim responsibility for ARMv7

In reply to Jan Viktorin
---
 MAINTAINERS | 4 ++++
 1 file changed, 4 insertions(+)
MAINTAINERS +4 -0
index 080a8e8..a8933eb 100644
@@ -124,6 +124,10 @@ IBM POWER
 M: Chao Zhu <[email protected]>
 F: lib/librte_eal/common/include/arch/ppc_64/
 
+ARM v7
+M: Jan Viktorin <[email protected]>
+F: lib/librte_eal/common/include/arch/arm/
+
 Intel x86
 M: Bruce Richardson <[email protected]>
 M: Konstantin Ananyev <[email protected]>
Signature · 1 line
2.6.2
#21 lore raw
In reply to Jan Viktorin
Quoted 7 lines · Jan Viktorin

Hello DPDK community,

ARMv7 again, changes:

* removed unnecessary code in the #ifndef RTE_FORCE_INTRINSICS .. #endif (atomic, spinlock, byteorder)
* more splitting of headers to have 32/64 bit variants (atomic, cpuflags)
* fixed cpuflags AT_PLATFORM

Thanks Jan, Dave .
I will rework on the arm64 support based on this version.

Quoted 82 lines

Other details in the individual commits as usual.

---

You can pull the changes from

https://github.com/RehiveTech/dpdk.git arm-support-v6

since commit 82fb702077f67585d64a07de0080e5cb6a924a72:

ixgbe: support new flow director modes for X550 (2015-10-29 00:06:01 +0100)

up to 9d686e4bd972dea2f9baef0a419a57a1c037d26e:

maintainers: claim responsibility for ARMv7 (2015-11-02 23:34:14 +0100)

---

Jan Viktorin (7):
eal/arm: implement rdtsc by PMU or clock_gettime eal/arm: use vector memcpy only when NEON is enabled eal/arm: detect arm architecture in cpu flags eal/arm: rwlock support for ARM
eal/arm: add very incomplete rte_vect gcc/arm: avoid alignment errors to break build
maintainers: claim responsibility for ARMv7

Vlastimil Kosar (8):
eal/arm: atomic operations for ARM eal/arm: byte order operations for ARM eal/arm: cpu cycle operations for ARM eal/arm: prefetch operations for ARM eal/arm: spinlock operations for ARM (without HTM) eal/arm: vector memcpy for ARM
eal/arm: cpu flag checks for ARM
mk: Introduce ARMv7 architecture

 MAINTAINERS                                        |   4 +
 app/test/test_cpuflags.c                           |   5 +
 config/defconfig_arm-armv7a-linuxapp-gcc           |  76 +++++
 doc/guides/rel_notes/release_2_2.rst               |   5 +
 .../common/include/arch/arm/rte_atomic.h           |  38 +++
 .../common/include/arch/arm/rte_atomic_32.h        |  74 +++++
 .../common/include/arch/arm/rte_byteorder.h        | 107 +++++++
 .../common/include/arch/arm/rte_cpuflags.h         |  38 +++
 .../common/include/arch/arm/rte_cpuflags_32.h      | 189 ++++++++++++
 .../common/include/arch/arm/rte_cycles.h           |  38 +++
 .../common/include/arch/arm/rte_cycles_32.h        | 121 ++++++++
 .../common/include/arch/arm/rte_memcpy.h           |  38 +++
 .../common/include/arch/arm/rte_memcpy_32.h        | 334 +++++++++++++++++++++
 .../common/include/arch/arm/rte_prefetch.h         |  38 +++
 .../common/include/arch/arm/rte_prefetch_32.h      |  61 ++++
 .../common/include/arch/arm/rte_rwlock.h           |  40 +++
 .../common/include/arch/arm/rte_spinlock.h         |  92 ++++++
 lib/librte_eal/common/include/arch/arm/rte_vect.h  |  84 ++++++
 mk/arch/arm/rte.vars.mk                            |  39 +++
 mk/machine/armv7-a/rte.vars.mk                     |  67 +++++
 mk/rte.cpuflags.mk                                 |   6 +
 mk/toolchain/gcc/rte.vars.mk                       |   6 +
 22 files changed, 1500 insertions(+)
 create mode 100644 config/defconfig_arm-armv7a-linuxapp-gcc
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_atomic_32.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_byteorder.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cpuflags_32.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_cycles_32.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_memcpy_32.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_prefetch_32.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_rwlock.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_spinlock.h
 create mode 100644 lib/librte_eal/common/include/arch/arm/rte_vect.h
 create mode 100644 mk/arch/arm/rte.vars.mk
 create mode 100644 mk/machine/armv7-a/rte.vars.mk
Signature · 1 line
2.6.2
#22 lore raw
Quoted 11 lines · Jerin Jacob
Quoted 7 lines · Jan Viktorin

Hello DPDK community,

ARMv7 again, changes:

* removed unnecessary code in the #ifndef RTE_FORCE_INTRINSICS .. #endif (atomic, spinlock, byteorder)
* more splitting of headers to have 32/64 bit variants (atomic, cpuflags)
* fixed cpuflags AT_PLATFORM

Thanks Jan, Dave .
I will rework on the arm64 support based on this version.

Jerin,
I've got an updated ARMv8 patchset almost ready based on Jan's latest patchset (v6). Will I post it to the list? I suspect that your patchset will be the preferred option for acceptance into DPDK, but there may be one or two snippets of code worth merging together for the final patchset. Rgds,
Dave.

#23 lore raw

I will be posting the new version with in a hour.

Thanks,
Jerin

________________________________________
From: Hunt, David <[email protected]>
Sent: Tuesday, November 3, 2015 5:03 PM
To: Jacob, Jerin; Jan Viktorin
Cc: [email protected]; Thomas Monjalon; [email protected]
Subject: Re: [PATCH v6 00/15] Support ARMv7 architecture

Quoted 11 lines · Jerin Jacob
Quoted 7 lines · Jan Viktorin

Hello DPDK community,

ARMv7 again, changes:

* removed unnecessary code in the #ifndef RTE_FORCE_INTRINSICS .. #endif (atomic, spinlock, byteorder)
* more splitting of headers to have 32/64 bit variants (atomic, cpuflags)
* fixed cpuflags AT_PLATFORM

Thanks Jan, Dave .
I will rework on the arm64 support based on this version.

Jerin,
I've got an updated ARMv8 patchset almost ready based on Jan's latest patchset (v6). Will I post it to the list? I suspect that your patchset will be the preferred option for acceptance into DPDK, but there may be one or two snippets of code worth merging together for the final patchset. Rgds,
Dave.

Acked-by on the v6 series
#24 lore raw
In reply to Jan Viktorin

Hello,

Quoted 24 lines · Jan Viktorin

Hello DPDK community,

ARMv7 again, changes:

* removed unnecessary code in the #ifndef RTE_FORCE_INTRINSICS .. #endif (atomic, spinlock, byteorder)
* more splitting of headers to have 32/64 bit variants (atomic, cpuflags)
* fixed cpuflags AT_PLATFORM

Other details in the individual commits as usual.

---
[snip]
---

Jan Viktorin (7):
eal/arm: implement rdtsc by PMU or clock_gettime eal/arm: use vector memcpy only when NEON is enabled eal/arm: detect arm architecture in cpu flags eal/arm: rwlock support for ARM
eal/arm: add very incomplete rte_vect gcc/arm: avoid alignment errors to break build
maintainers: claim responsibility for ARMv7

Quoted 11 lines

Vlastimil Kosar (8):
eal/arm: atomic operations for ARM eal/arm: byte order operations for ARM eal/arm: cpu cycle operations for ARM eal/arm: prefetch operations for ARM eal/arm: spinlock operations for ARM (without HTM) eal/arm: vector memcpy for ARM
eal/arm: cpu flag checks for ARM
mk: Introduce ARMv7 architecture

Looks good to me.

Thanks Jan.

Signature · 1 line
David Marchand
#25 lore raw
Quoted 20 lines
Quoted 9 lines

Jan Viktorin (7):
eal/arm: implement rdtsc by PMU or clock_gettime eal/arm: use vector memcpy only when NEON is enabled eal/arm: detect arm architecture in cpu flags eal/arm: rwlock support for ARM
eal/arm: add very incomplete rte_vect gcc/arm: avoid alignment errors to break build
maintainers: claim responsibility for ARMv7

Quoted 11 lines

Vlastimil Kosar (8):
eal/arm: atomic operations for ARM eal/arm: byte order operations for ARM eal/arm: cpu cycle operations for ARM eal/arm: prefetch operations for ARM eal/arm: spinlock operations for ARM (without HTM) eal/arm: vector memcpy for ARM
eal/arm: cpu flag checks for ARM
mk: Introduce ARMv7 architecture

Quoted 4 lines

Looks good to me.

Thanks Jan.

Applied, thanks
The rte_vect patch is squashed/removed because Jerin's patch replace it.