Patch "drm/amdgpu: Make display watermark calculations more accurate" has been added to the 4.11-stable tree
Subsystems (3)
This is a note to let you know that I've just added the patch titled
drm/amdgpu: Make display watermark calculations more accurate
to the 4.11-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary
The filename of the patch is:
drm-amdgpu-make-display-watermark-calculations-more-accurate.patch
and it can be found in the queue-4.11 subdirectory.
If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.
Quoted 1 line
From
d63c277dc672e0c568481af043359420fa9d4736Mon Sep 17 00:00:00 2001
From: Mario Kleiner <[email protected]>
Date: Wed, 29 Mar 2017 22:09:11 +0200
Subject: drm/amdgpu: Make display watermark calculations more accurate
From: Mario Kleiner <[email protected]>
commit d63c277dc672e0c568481af043359420fa9d4736 upstream.
Avoid big roundoff errors in scanline/hactive durations for high pixel clocks, especially for >= 500 Mhz, and thereby program more accurate display fifo watermarks.
Implemented here for DCE 6,8,10,11. Successfully tested on DCE 10 with AMD R9 380 Tonga.
Reviewed-by Alex Deucher <[email protected]>
Signed-off-by Mario Kleiner <[email protected]>
Signed-off-by Alex Deucher <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
--- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 10 +++++----- drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 10 +++++----- 4 files changed, 20 insertions(+), 20 deletions(-)
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +5 -5
@@ -1214,14 +1214,14 @@ static void dce_v10_0_program_watermarks {struct drm_display_mode *mode = &amdgpu_crtc->base.mode;struct dce10_wm_params wm_low, wm_high; -u32 pixel_period; +u32 active_time;u32 line_time =0 ;u32 latency_watermark_a =0 , latency_watermark_b =0 ;u32 tmp, wm_mask, lb_vblank_lead_lines =0 ;if (amdgpu_crtc->base.enabled && num_heads && mode) { - pixel_period =1000000 / (u32 )mode->clock; - line_time =min ((u32 )mode->crtc_htotal * pixel_period, (u32 )65535 ); + active_time =1000000UL * (u32 )mode->crtc_hdisplay / (u32 )mode->clock; + line_time =min ((u32) (1000000UL * (u32 )mode->crtc_htotal / (u32 )mode->clock), (u32 )65535 );/* watermark for high clocks */ if (adev->pm.dpm_enabled) {
@@ -1236,7 +1236,7 @@ static void dce_v10_0_program_watermarks wm_high.disp_clk = mode->clock; wm_high.src_width = mode->crtc_hdisplay; - wm_high.active_time = mode->crtc_hdisplay * pixel_period; + wm_high.active_time = active_time; wm_high.blank_time = line_time - wm_high.active_time; wm_high.interlaced = false;if (mode->flags &DRM_MODE_FLAG_INTERLACE )
@@ -1275,7 +1275,7 @@ static void dce_v10_0_program_watermarks wm_low.disp_clk = mode->clock; wm_low.src_width = mode->crtc_hdisplay; - wm_low.active_time = mode->crtc_hdisplay * pixel_period; + wm_low.active_time = active_time; wm_low.blank_time = line_time - wm_low.active_time; wm_low.interlaced = false;if (mode->flags &DRM_MODE_FLAG_INTERLACE )
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +5 -5
@@ -1183,14 +1183,14 @@ static void dce_v11_0_program_watermarks {struct drm_display_mode *mode = &amdgpu_crtc->base.mode;struct dce10_wm_params wm_low, wm_high; -u32 pixel_period; +u32 active_time;u32 line_time =0 ;u32 latency_watermark_a =0 , latency_watermark_b =0 ;u32 tmp, wm_mask, lb_vblank_lead_lines =0 ;if (amdgpu_crtc->base.enabled && num_heads && mode) { - pixel_period =1000000 / (u32 )mode->clock; - line_time =min ((u32 )mode->crtc_htotal * pixel_period, (u32 )65535 ); + active_time =1000000UL * (u32 )mode->crtc_hdisplay / (u32 )mode->clock; + line_time =min ((u32) (1000000UL * (u32 )mode->crtc_htotal / (u32 )mode->clock), (u32 )65535 );/* watermark for high clocks */ if (adev->pm.dpm_enabled) {
@@ -1205,7 +1205,7 @@ static void dce_v11_0_program_watermarks wm_high.disp_clk = mode->clock; wm_high.src_width = mode->crtc_hdisplay; - wm_high.active_time = mode->crtc_hdisplay * pixel_period; + wm_high.active_time = active_time; wm_high.blank_time = line_time - wm_high.active_time; wm_high.interlaced = false;if (mode->flags &DRM_MODE_FLAG_INTERLACE )
@@ -1244,7 +1244,7 @@ static void dce_v11_0_program_watermarks wm_low.disp_clk = mode->clock; wm_low.src_width = mode->crtc_hdisplay; - wm_low.active_time = mode->crtc_hdisplay * pixel_period; + wm_low.active_time = active_time; wm_low.blank_time = line_time - wm_low.active_time; wm_low.interlaced = false;if (mode->flags &DRM_MODE_FLAG_INTERLACE )
drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +5 -5
@@ -986,7 +986,7 @@ static void dce_v6_0_program_watermarks(struct drm_display_mode *mode = &amdgpu_crtc->base.mode;struct dce6_wm_params wm_low, wm_high;u32 dram_channels; -u32 pixel_period; +u32 active_time;u32 line_time =0 ;u32 latency_watermark_a =0 , latency_watermark_b =0 ;u32 priority_a_mark =0 , priority_b_mark =0 ;
@@ -996,8 +996,8 @@ static void dce_v6_0_program_watermarks(fixed20_12 a, b, c;if (amdgpu_crtc->base.enabled && num_heads && mode) { - pixel_period =1000000 / (u32 )mode->clock; - line_time =min ((u32 )mode->crtc_htotal * pixel_period, (u32 )65535 ); + active_time =1000000UL * (u32 )mode->crtc_hdisplay / (u32 )mode->clock; + line_time =min ((u32) (1000000UL * (u32 )mode->crtc_htotal / (u32 )mode->clock), (u32 )65535 ); priority_a_cnt =0 ; priority_b_cnt =0 ;
@@ -1016,7 +1016,7 @@ static void dce_v6_0_program_watermarks( wm_high.disp_clk = mode->clock; wm_high.src_width = mode->crtc_hdisplay; - wm_high.active_time = mode->crtc_hdisplay * pixel_period; + wm_high.active_time = active_time; wm_high.blank_time = line_time - wm_high.active_time; wm_high.interlaced = false;if (mode->flags &DRM_MODE_FLAG_INTERLACE )
@@ -1043,7 +1043,7 @@ static void dce_v6_0_program_watermarks( wm_low.disp_clk = mode->clock; wm_low.src_width = mode->crtc_hdisplay; - wm_low.active_time = mode->crtc_hdisplay * pixel_period; + wm_low.active_time = active_time; wm_low.blank_time = line_time - wm_low.active_time; wm_low.interlaced = false;if (mode->flags &DRM_MODE_FLAG_INTERLACE )
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +5 -5
@@ -1098,14 +1098,14 @@ static void dce_v8_0_program_watermarks( {struct drm_display_mode *mode = &amdgpu_crtc->base.mode;struct dce8_wm_params wm_low, wm_high; -u32 pixel_period; +u32 active_time;u32 line_time =0 ;u32 latency_watermark_a =0 , latency_watermark_b =0 ;u32 tmp, wm_mask, lb_vblank_lead_lines =0 ;if (amdgpu_crtc->base.enabled && num_heads && mode) { - pixel_period =1000000 / (u32 )mode->clock; - line_time =min ((u32 )mode->crtc_htotal * pixel_period, (u32 )65535 ); + active_time =1000000UL * (u32 )mode->crtc_hdisplay / (u32 )mode->clock; + line_time =min ((u32) (1000000UL * (u32 )mode->crtc_htotal / (u32 )mode->clock), (u32 )65535 );/* watermark for high clocks */ if (adev->pm.dpm_enabled) {
@@ -1120,7 +1120,7 @@ static void dce_v8_0_program_watermarks( wm_high.disp_clk = mode->clock; wm_high.src_width = mode->crtc_hdisplay; - wm_high.active_time = mode->crtc_hdisplay * pixel_period; + wm_high.active_time = active_time; wm_high.blank_time = line_time - wm_high.active_time; wm_high.interlaced = false;if (mode->flags &DRM_MODE_FLAG_INTERLACE )
@@ -1159,7 +1159,7 @@ static void dce_v8_0_program_watermarks( wm_low.disp_clk = mode->clock; wm_low.src_width = mode->crtc_hdisplay; - wm_low.active_time = mode->crtc_hdisplay * pixel_period; + wm_low.active_time = active_time; wm_low.blank_time = line_time - wm_low.active_time; wm_low.interlaced = false;if (mode->flags &DRM_MODE_FLAG_INTERLACE )
Patches currently in stable-queue which might be from [email protected] are
queue-4.11/drm-amdgpu-add-missing-lb_vblank_lead_lines-setup-to-dce-6-path.patch queue-4.11/drm-amdgpu-avoid-overflows-divide-by-zero-in-latency_watermark-calculations.patch queue-4.11/drm-amdgpu-make-display-watermark-calculations-more-accurate.patch