Add Intel Arria 10 SoC FPGA driver

From: Tien Fong Chee <[email protected]>

This is the 4th version of patchset to adds support for Intel Arria 10 SoC FPGA driver. This version mainly resolved comments from Ley Foon and Dinh in [v3]. This series is working on top of u-boot-socfpga-next branch
http://git.denx.de/?p=u-boot/u-boot-socfpga.git;a=shortlog;h=refs/heads/next.

[v3]: https://www.mail-archive.com/u-boot at lists.denx.de/msg249160.html

v3 -> v4 changes:
-----------------
- Fixed typo on patch 1 and patch 2.
- Created separate patch for enabling FPGA driver build on SPL.
- No change on patch 3.
- Removed some unnecessary wrappers and unused function.

Patchset history
----------------
[v1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg247788.html [v2]: https://www.mail-archive.com/u-boot at lists.denx.de/msg248541.html

Tien Fong Chee (5):
arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
arm: socfpga: Restructure FPGA driver in the preparation to support

    A10.

arm: socfpga: Enable FPGA driver on SPL
arm: socfpga: Move FPGA manager driver to FPGA driver
arm: socfpga: Add FPGA driver support for Arria 10

 arch/arm/mach-socfpga/Makefile                     |   1 -
 arch/arm/mach-socfpga/fpga_manager.c               |  78 ----
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  70 +--
 .../include/mach/fpga_manager_arria10.h            | 100 +++++
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 ++-
 .../include/mach/reset_manager_arria10.h           |   2 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c      |   4 +-
 drivers/Makefile                                   |   1 +
 drivers/fpga/Makefile                              |   2 +
 drivers/fpga/socfpga.c                             | 241 +----------
 drivers/fpga/socfpga_arria10.c                     | 479 +++++++++++++++++++++
 drivers/fpga/{socfpga.c => socfpga_gen5.c}         |  98 ++---
 include/configs/socfpga_common.h                   |   3 +-
 13 files changed, 684 insertions(+), 464 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
 create mode 100644 drivers/fpga/socfpga_arria10.c
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (85%)

1.8.2.3

From: Tien Fong Chee <[email protected]>

Remove parameter from socfpga_bridges_reset(), and keeping this function for single purpose which is just triggering reset on bridges. socfpga_reset_deassert_bridges_handoff() can be called for releasing reset on any bridges based on the bridge setting defined in fdt.

---
 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 2 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c              | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

index 7922db8..b6d7f4f 100644
@@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void);
 void socfpga_reset_assert_fpga_connected_peripherals(void);
 void socfpga_reset_deassert_osc1wd0(void);
 void socfpga_reset_uart(int assert);
-int socfpga_bridges_reset(int enable);
+int socfpga_bridges_reset(void);
 
 struct socfpga_reset_manager {
 	u32	stat;

index d8c858c..66f1ec2 100644
@@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
 }
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
 {
 	/* For SoCFPGA-VT, this is NOP. */
 	return 0;
 }
 #else
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
 {
 	int ret;
 

1.8.2.3

From: Tien Fong Chee <[email protected]>

Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver er intact. All the changes are still keeping in driver/fpga/ and no functional change. Subsequent patch would move FPGA manager driver from arch/arm into driver/fpga/ .

---
 arch/arm/mach-socfpga/Makefile                     |   2 +-
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  68 +-----
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 +++---
 drivers/fpga/Makefile                              |   1 +
 drivers/fpga/socfpga.c                             | 241 +--------------------
 drivers/fpga/{socfpga.c => socfpga_gen5.c}         |  54 +----
 6 files changed, 49 insertions(+), 386 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)

index 41b779c..286bfef 100644
@@ -9,7 +9,6 @@
 
 obj-y	+= board.o
 obj-y	+= clock_manager.o
-obj-y	+= fpga_manager.o
 obj-y	+= misc.o
 obj-y	+= reset_manager.o
 obj-y	+= timer.o

@@ -21,6 +20,7 @@ obj-y	+= reset_manager_gen5.o
 obj-y	+= scan_manager.o
 obj-y	+= system_manager_gen5.o
 obj-y	+= wrap_pll_config.o
+obj-y	+= fpga_manager.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10

index 777706f..b65e5ba 100644
@@ -20,4 +20,5 @@ obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
 obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
 obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
 obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
 endif

1.8.2.3

remove the 'er'.

Also remove the ending '.' at the end of the commit header.

Dinh

Okay.

From: Tien Fong Chee <[email protected]>

Enable FPGA driver build for SPL. FPGA driver is needed for SPL to configure and getting DDR up before loading U-boot into DDR and booting from there.

---
 drivers/Makefile | 1 +
 1 file changed, 1 insertion(+)

index 4a4b237..b4a2230 100644
@@ -47,6 +47,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_FPGA) += fpga/
 endif
 
 ifdef CONFIG_TPL_BUILD

1.8.2.3

Also with the above change, you're building in the FPGA driver into the SPL for Gen5 devices, you probably didn't want that.

  CC      spl/drivers/fpga/fpga.o
  CC      spl/drivers/fpga/altera.o
  CC      spl/drivers/fpga/socfpga.o

Dinh

Okay, sure.

From: Tien Fong Chee <[email protected]>

Move FPGA manager driver which is Gen5 specific code from arch/arm/ into FPGA driver at driver/fpga/. No functional change.

---
 arch/arm/mach-socfpga/Makefile       |  1 -
 arch/arm/mach-socfpga/fpga_manager.c | 78 ------------------------------------
 drivers/fpga/socfpga_gen5.c          | 54 +++++++++++++++++++++++++
 3 files changed, 54 insertions(+), 79 deletions(-)
 delete mode 100644 arch/arm/mach-socfpga/fpga_manager.c

index 286bfef..824cd8e 100644
@@ -20,7 +20,6 @@ obj-y	+= reset_manager_gen5.o
 obj-y	+= scan_manager.o
 obj-y	+= system_manager_gen5.o
 obj-y	+= wrap_pll_config.o
-obj-y	+= fpga_manager.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10

1.8.2.3

From: Tien Fong Chee <[email protected]>

Add FPGA driver support for Arria 10.

---
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |   2 +
 .../include/mach/fpga_manager_arria10.h            | 100 +++++
 drivers/fpga/Makefile                              |   1 +
 drivers/fpga/socfpga_arria10.c                     | 479 +++++++++++++++++++++
 include/configs/socfpga_common.h                   |   3 +-
 5 files changed, 583 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
 create mode 100644 drivers/fpga/socfpga_arria10.c

index b046c2c..a21c716 100644
@@ -12,6 +12,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include <asm/arch/fpga_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/fpga_manager_arria10.h>
 #endif
 
 /* FPGA CD Ratio Value */

index b65e5ba..08c9ff8 100644
@@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
 obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
 obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
 endif

index da7e4ad..913b9f1 100644
@@ -105,14 +105,13 @@
 /*
  * FPGA Driver
  */
-#ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_CMD_FPGA
 #define CONFIG_FPGA
 #define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT		1
 #endif
-#endif
+
 /*
  * L4 OSC1 Timer 0
  */

1.8.2.3

Hi Marek,

How about this series of patches? Good to get accepted?

Thanks.

How many A-B/R-B tags did it collect thus far ?

Best regards,
Marek Vasut