drm/i915/gvt: Dma-buf support for GVT-g

drivers/gpu/drm/i915/gvt/dmabuf.c new file +11 -0

+	} else if (plane_id == INTEL_GVT_PLANE_CURSOR) {
+		c = &pipe->cursor;
+		if (c != NULL) {
+			info->start = c->base;
+			info->width = c->width;
+			info->height = c->height;
+			info->stride = c->width * (c->bpp / 8);
+			info->drm_format_mod = 0;
+			info->x_pos = c->x_pos;
+			info->y_pos = c->y_pos;
+			info->size = (((info->stride * c->height *

c->bpp) / 8)

(quoted diff) +1 -0

+					+ (PAGE_SIZE - 1)) >>

PAGE_SHIFT;

dmabuf for GVT-g can be exported to users who can use the dmabuf to show the desktop of vm which use intel vgpu.

Currently we provide query and create new dmabuf operations.

Users of dmabuf can cache some created dmabufs and related information such as the framebuffer's address, size, tiling mode, width, height etc. When refresh the screen first query the currnet vgpu's frambuffer and compare with the cached ones(address, size, tiling, width, height etc) if found one then reuse the found dmabuf to gain performance improvment.

If there is no dmabuf created yet or not found in the cached dmabufs then need to create a new dmabuf. To create a dmabuf first a gem object will be created and the backing storage of this gem object is the vgpu's framebuffer(primary/cursor).
Set caching mode, change tiling mode and set domains of this gem object is not supported.
Then associate this gem object to a dmabuf and export this dmabuf. A file descriptor will be generated for this dmabuf and this file descriptor can be sent to user space to do display.

Signed-off-by Xiaoguang Chen <[email protected]>

---
 drivers/gpu/drm/i915/gvt/Makefile      |   2 +-
 drivers/gpu/drm/i915/gvt/dmabuf.c      | 276 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/dmabuf.h      |  53 +++++++
 drivers/gpu/drm/i915/gvt/gvt.h         |   1 +
 drivers/gpu/drm/i915/i915_gem.c        |   8 +
 drivers/gpu/drm/i915/i915_gem_object.h |   9 ++
 6 files changed, 348 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h

drivers/gpu/drm/i915/gvt/Makefile +1 -1

index 192ca26..e480f7d 100644
@@ -2,7 +2,7 @@ GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
 	interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
 	execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
-	fb_decoder.o
+	fb_decoder.o dmabuf.o
 
 ccflags-y				+= -I$(src) -I$(src)/$(GVT_DIR) -Wall
 i915-y					+= $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))

drivers/gpu/drm/i915/gvt/dmabuf.c new file +40 -0

new file mode 100644
index 0000000..415453b
@@ -0,0 +1,276 @@
+/*
+ * Copyright 2017 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Zhiyuan Lv <[email protected]>
+ *
+ * Contributors:
+ *    Xiaoguang Chen <[email protected]>
+ */
+
+#include <linux/dma-buf.h>
+#include <drm/drmP.h>
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define GEN8_DECODE_PTE(pte) \
+	((dma_addr_t)(((((u64)pte) >> 12) & 0x7ffffffULL) << 12))
+
+static struct sg_table *intel_vgpu_gem_get_pages(
+		struct drm_i915_gem_object *obj)

drivers/gpu/drm/i915/gvt/dmabuf.c new file +100 -0

+	if (WARN_ON(!plane_info))
+		return ERR_PTR(-EINVAL);
+
+	fb_gma = plane_info->start;
+	fb_size = plane_info->size;
+
+	st = kmalloc(sizeof(*st), GFP_KERNEL);
+	if (!st) {
+		ret = -ENOMEM;
+		return ERR_PTR(ret);
+	}
+
+	ret = sg_alloc_table(st, fb_size, GFP_KERNEL);
+	if (ret) {
+		kfree(st);
+		return ERR_PTR(ret);
+	}
+	gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+		(fb_gma >> PAGE_SHIFT);
+	for_each_sg(st->sgl, sg, fb_size, i) {
+		sg->offset = 0;
+		sg->length = PAGE_SIZE;
+		sg_dma_address(sg) =
+			GEN8_DECODE_PTE(readq(&gtt_entries[i]));
+		sg_dma_len(sg) = PAGE_SIZE;
+	}
+
+	return st;
+}
+
+static void intel_vgpu_gem_put_pages(struct drm_i915_gem_object *obj,
+		struct sg_table *pages)
+{
+	struct intel_vgpu_plane_info *plane_info;
+
+	plane_info = (struct intel_vgpu_plane_info *)obj->gvt_plane_info;
+	if (WARN_ON(!plane_info))
+		return;
+
+	sg_free_table(pages);
+	kfree(pages);
+}
+
+static const struct drm_i915_gem_object_ops intel_vgpu_gem_ops = {
+	.flags = I915_GEM_OBJECT_IS_GVT_DMABUF,
+	.get_pages = intel_vgpu_gem_get_pages,
+	.put_pages = intel_vgpu_gem_put_pages,
+};
+
+static struct drm_i915_gem_object *intel_vgpu_create_gem(struct drm_device *dev,
+		struct intel_vgpu_plane_info *info)
+{
+	struct drm_i915_private *pri = dev->dev_private;
+	struct drm_i915_gem_object *obj;
+
+	obj = i915_gem_object_alloc(pri);
+	if (obj == NULL)
+		return NULL;
+
+	drm_gem_private_object_init(dev, &obj->base,
+		info->size << PAGE_SHIFT);
+	i915_gem_object_init(obj, &intel_vgpu_gem_ops);
+
+	obj->base.read_domains = I915_GEM_DOMAIN_GTT;
+	obj->base.write_domain = 0;
+	obj->framebuffer_references++;
+	obj->gvt_plane_info = info;
+
+	if (IS_SKYLAKE(pri)) {
+		unsigned int tiling_mode = 0;
+
+		switch (info->drm_format_mod << 10) {
+		case PLANE_CTL_TILED_LINEAR:
+			tiling_mode = I915_TILING_NONE;
+			break;
+		case PLANE_CTL_TILED_X:
+			tiling_mode = I915_TILING_X;
+			break;
+		case PLANE_CTL_TILED_Y:
+			tiling_mode = I915_TILING_Y;
+			break;
+		default:
+			gvt_dbg_core("not supported tiling mode\n");
+		}
+		obj->tiling_and_stride = tiling_mode | info->stride;
+	} else {
+		obj->tiling_and_stride = info->drm_format_mod ?
+					I915_TILING_X : 0;
+	}
+
+	return obj;
+}
+
+static struct intel_vgpu_plane_info *intel_vgpu_get_plane_info(
+		struct drm_device *dev,
+		struct intel_vgpu *vgpu, uint32_t plane_id)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_vgpu_primary_plane_format *p;
+	struct intel_vgpu_cursor_plane_format *c;

drivers/gpu/drm/i915/gvt/dmabuf.c new file +53 -0

+
+	if (plane_id == INTEL_GVT_PLANE_PRIMARY) {
+		p = &pipe->primary;
+		if (p != NULL) {
+			info->start = p->base;
+			info->width = p->width;
+			info->height = p->height;
+			info->stride = p->stride;
+			info->drm_format = p->drm_format;
+			info->drm_format_mod = p->tiled;
+			info->size = (((p->stride * p->height * p->bpp) / 8) +
+					(PAGE_SIZE - 1)) >> PAGE_SHIFT;
+		} else {
+			kfree(info);
+			gvt_vgpu_err("invalid primary plane\n");
+			return NULL;
+		}
+	} else if (plane_id == INTEL_GVT_PLANE_CURSOR) {
+		c = &pipe->cursor;
+		if (c != NULL) {
+			info->start = c->base;
+			info->width = c->width;
+			info->height = c->height;
+			info->stride = c->width * (c->bpp / 8);
+			info->drm_format_mod = 0;
+			info->x_pos = c->x_pos;
+			info->y_pos = c->y_pos;
+			info->size = (((info->stride * c->height * c->bpp) / 8)
+					+ (PAGE_SIZE - 1)) >> PAGE_SHIFT;
+		} else {
+			kfree(info);
+			gvt_vgpu_err("invalid cursor plane\n");
+			return NULL;
+		}
+	} else {
+		kfree(info);
+		gvt_vgpu_err("invalid plane id:%d\n", plane_id);
+		return NULL;
+	}
+
+	if (info->size == 0) {
+		kfree(info);
+		gvt_vgpu_err("fb size is zero\n");
+		return NULL;
+	}
+
+	if (info->start & (PAGE_SIZE - 1)) {
+		kfree(info);
+		gvt_vgpu_err("Not aligned fb address:0x%x\n", info->start);
+		return NULL;
+	}
+	if (((info->start >> PAGE_SHIFT) + info->size) >
+		ggtt_total_entries(&dev_priv->ggtt)) {

drivers/gpu/drm/i915/gvt/dmabuf.c new file +12 -0

+
+	return 0;
+}
+
+int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args)
+{
+	struct dma_buf *dmabuf;
+	struct drm_i915_gem_object *obj;
+	struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
+	struct intel_vgpu_dmabuf *gvt_dmabuf = args;
+	struct intel_vgpu_plane_info *info;
+	int ret;

drivers/gpu/drm/i915/gvt/dmabuf.c new file +1 -0

+}

drivers/gpu/drm/i915/gvt/dmabuf.h new file +30 -0

new file mode 100644
index 0000000..43562af
@@ -0,0 +1,53 @@
+
+/*
+ * Copyright(c) 2017 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ */
+
+#ifndef _GVT_DMABUF_H_
+#define _GVT_DMABUF_H_
+
+struct intel_vgpu_plane_info {
+	uint32_t plane_id;

drivers/gpu/drm/i915/gvt/dmabuf.h new file +5 -0

+
+int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args);
+int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args);
+
+#endif

drivers/gpu/drm/i915/gvt/gvt.h +1 -0

index c42266c..763a8c5 100644
@@ -47,6 +47,7 @@
 #include "render.h"
 #include "cmd_parser.h"
 #include "fb_decoder.h"
+#include "dmabuf.h"
 
 #define GVT_MAX_VGPU 8
 

drivers/gpu/drm/i915/i915_gem.c +8 -0

index 0c1cbe9..54f7a0f 100644
@@ -1609,6 +1609,10 @@ i915_gem_set_domain_ioctl(struct drm_device *dev, void *data,
 	if (!obj)
 		return -ENOENT;
 
+	/* The obj is a gvt dma-buf object and set domain is not supported */
+	if (i915_gem_object_is_gvt_dmabuf(obj))
+		return -EPERM;
+
 	/* Try to flush the object off the GPU without holding the lock.
 	 * We will repeat the flush holding the lock in the normal manner
 	 * to catch cases where we are gazumped.

@@ -3717,6 +3721,10 @@ int i915_gem_set_caching_ioctl(struct drm_device *dev, void *data,
 	if (!obj)
 		return -ENOENT;
 
+	/* the obj is a gvt dma-buf and set caching mode is not supported */
+	if (i915_gem_object_is_gvt_dmabuf(obj))
+		return -EPERM;
+
 	if (obj->cache_level == level)
 		goto out;
 

drivers/gpu/drm/i915/i915_gem_object.h +3 -0

index 174cf92..986af43 100644
@@ -39,6 +39,7 @@ struct drm_i915_gem_object_ops {
 	unsigned int flags;
 #define I915_GEM_OBJECT_HAS_STRUCT_PAGE 0x1
 #define I915_GEM_OBJECT_IS_SHRINKABLE   0x2
+#define I915_GEM_OBJECT_IS_GVT_DMABUF	0x4
 
 	/* Interface between the GEM object and its backing storage.
 	 * get_pages() is called once prior to the use of the associated set

@@ -184,6 +185,8 @@ struct drm_i915_gem_object {
 		} userptr;
 
 		unsigned long scratch;
+
+		void *gvt_plane_info;
 	};
 
 	/** for phys allocated objects */

@@ -286,6 +289,12 @@ i915_gem_object_is_shrinkable(const struct drm_i915_gem_object *obj)
 }
 

dmabuf for GVT-g can be exported to users who can use the dmabuf to show the desktop of vm which use intel vgpu.

Currently we provide query and create new dmabuf operations.

Users of dmabuf can cache some created dmabufs and related information such as the framebuffer's address, size, tiling mode, width, height etc. When refresh the screen first query the currnet vgpu's frambuffer and compare with the cached ones(address, size, tiling, width, height etc) if found one then reuse the found dmabuf to gain performance improvment.

If there is no dmabuf created yet or not found in the cached dmabufs then need to create a new dmabuf. To create a dmabuf first a gem object will be created and the backing storage of this gem object is the vgpu's framebuffer(primary/cursor).
Set caching mode, change tiling mode and set domains of this gem object is not supported.
Then associate this gem object to a dmabuf and export this dmabuf. A file descriptor will be generated for this dmabuf and this file descriptor can be sent to user space to do display.

Signed-off-by Xiaoguang Chen <[email protected]>

---
 drivers/gpu/drm/i915/gvt/Makefile      |   2 +-
 drivers/gpu/drm/i915/gvt/dmabuf.c      | 276 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/dmabuf.h      |  53 +++++++
 drivers/gpu/drm/i915/gvt/gvt.h         |   1 +
 drivers/gpu/drm/i915/i915_gem.c        |   8 +
 drivers/gpu/drm/i915/i915_gem_object.h |   9 ++
 6 files changed, 348 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h

drivers/gpu/drm/i915/gvt/Makefile +1 -1

index 192ca26..e480f7d 100644
@@ -2,7 +2,7 @@ GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
 	interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
 	execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
-	fb_decoder.o
+	fb_decoder.o dmabuf.o
 
 ccflags-y				+= -I$(src) -I$(src)/$(GVT_DIR) -Wall
 i915-y					+= $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))

drivers/gpu/drm/i915/gvt/dmabuf.c new file +27 -0

new file mode 100644
index 0000000..415453b
@@ -0,0 +1,276 @@
+/*
+ * Copyright 2017 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Zhiyuan Lv <[email protected]>
+ *
+ * Contributors:
+ *    Xiaoguang Chen <[email protected]>

drivers/gpu/drm/i915/gvt/dmabuf.c new file +5 -0

+
+static struct sg_table *intel_vgpu_gem_get_pages(
+		struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);

drivers/gpu/drm/i915/gvt/dmabuf.c new file +12 -0

+	fb_gma = plane_info->start;
+	fb_size = plane_info->size;
+
+	st = kmalloc(sizeof(*st), GFP_KERNEL);
+	if (!st) {
+		ret = -ENOMEM;
+		return ERR_PTR(ret);
+	}
+
+	ret = sg_alloc_table(st, fb_size, GFP_KERNEL);
+	if (ret) {
+		kfree(st);

drivers/gpu/drm/i915/gvt/dmabuf.c new file +5 -0

+	struct drm_i915_gem_object *obj;
+
+	obj = i915_gem_object_alloc(pri);
+	if (obj == NULL)
+		return NULL;

drivers/gpu/drm/i915/gvt/dmabuf.c new file +9 -0

+	obj->gvt_plane_info = info;
+
+	if (IS_SKYLAKE(pri)) {
+		unsigned int tiling_mode = 0;
+
+		switch (info->drm_format_mod << 10) {
+		case PLANE_CTL_TILED_LINEAR:
+			tiling_mode = I915_TILING_NONE;
+			break;

drivers/gpu/drm/i915/gvt/dmabuf.c new file +20 -0

+int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args)
+{
+	struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
+	struct intel_vgpu_plane_info *info = args;
+
+	info = intel_vgpu_get_plane_info(dev, vgpu, info->plane_id);
+	if (info == NULL)
+		return -EINVAL;
+
+	return 0;
+}
+
+int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args)
+{
+	struct dma_buf *dmabuf;
+	struct drm_i915_gem_object *obj;
+	struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
+	struct intel_vgpu_dmabuf *gvt_dmabuf = args;
+	struct intel_vgpu_plane_info *info;
+	int ret;

drivers/gpu/drm/i915/gvt/dmabuf.c new file +6 -0

+	}
+	gvt_dmabuf->fd = ret;
+	gvt_dmabuf->plane_info = *info;
+
+	return 0;
+}

drivers/gpu/drm/i915/gvt/gvt.h +1 -0

index c42266c..763a8c5 100644
@@ -47,6 +47,7 @@
 #include "render.h"
 #include "cmd_parser.h"
 #include "fb_decoder.h"
+#include "dmabuf.h"
 
 #define GVT_MAX_VGPU 8
 

drivers/gpu/drm/i915/i915_gem.c +0 -0

index 0c1cbe9..54f7a0f 100644

drivers/gpu/drm/i915/gvt/dmabuf.c line 75

Quoted 8 lines · Xiaoguang Chen

drivers/gpu/drm/i915/gvt/dmabuf.c new file +8 -0

+	gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+		(fb_gma >> PAGE_SHIFT);
+	for_each_sg(st->sgl, sg, fb_size, i) {
+		sg->offset = 0;
+		sg->length = PAGE_SIZE;
+		sg_dma_address(sg) =
+			GEN8_DECODE_PTE(readq(&gtt_entries[i]));
+		sg_dma_len(sg) = PAGE_SIZE;

This assumes that the entries are PAGE_SIZE. This will not remain true.

include/uapi/linux/vfio.h +0 -0

index ae46105..285dc16 100644
@@ -502,10 +502,58 @@ struct vfio_pci_hot_reset {

 #define VFIO_DEVICE_PCI_HOT_RESET _IO(VFIO_TYPE, VFIO_BASE +
13)

+/**
+ * VFIO_DEVICE_GET_FD - _IO(VFIO_TYPE, VFIO_BASE + 14, __u32)
+ *
+ * Create a fd for a vfio device based on the input type
+ * Vendor driver should handle this ioctl to create a fd and manage the
+ * life cycle of this fd.
+ *
+ * Return: a fd if vendor support that type, -errno if not supported
+ */

include/uapi/linux/vfio.h +7 -0

+
+#define VFIO_DEVICE_GET_FD	_IO(VFIO_TYPE, VFIO_BASE + 14)
+
+#define VFIO_DEVICE_DMABUF_MGR_FD	0 /* Supported fd types */
+
+/*
+ * VFIO_DEVICE_QUERY_PLANE - _IO(VFIO_TYPE, VFIO_BASE + 15, struct

plane_info)
+ * Query plane information for a plane
+ */
+struct plane_info {

include/uapi/linux/vfio.h +4 -0

+	__u32 plane_id;
+	__u32 drm_format;
+	__u32 width;
+	__u32 height;

Hi,

Quoted 25 lines

include/uapi/linux/vfio.h +5 -0

index ae46105..285dc16 100644
@@ -502,10 +502,58 @@ struct vfio_pci_hot_reset {
 
 #define VFIO_DEVICE_PCI_HOT_RESET	_IO(VFIO_TYPE, VFIO_BASE +
 13)
 
+/**
+ * VFIO_DEVICE_GET_FD - _IO(VFIO_TYPE, VFIO_BASE + 14, __u32)
+ *
+ * Create a fd for a vfio device based on the input type
+ * Vendor driver should handle this ioctl to create a fd and manage

the
+ * life cycle of this fd.
+ *
+ * Return: a fd if vendor support that type, -errno if not supported
+ */

include/uapi/linux/vfio.h +6 -0

+
+#define VFIO_DEVICE_GET_FD	_IO(VFIO_TYPE, VFIO_BASE + 14)
+
+#define VFIO_DEVICE_DMABUF_MGR_FD	0 /* Supported fd types */
+
+/*

Quoted 5 lines

+ * VFIO_DEVICE_QUERY_PLANE - _IO(VFIO_TYPE, VFIO_BASE + 15, struct plane_info)
+ * Query plane information for a plane
+ */
+struct plane_info {

That is a pretty generic name. vfio_vgpu_plane_info? Or vfio_dmabuf_plane_info?

Quoted 4 lines

include/uapi/linux/vfio.h +4 -0

+	__u32 plane_id;
+	__u32 drm_format;
+	__u32 width;
+	__u32 height;

include/uapi/linux/vfio.h struct vfio_pci_hot_reset { · line 537

Quoted 10 lines

include/uapi/linux/vfio.h +10 -0

+	__u32 stride;
+	__u32 start;
+	__u32 x_pos;
+	__u32 y_pos;
+	__u32 size;
+	__u64 drm_format_mod;
+};
+
+#define VFIO_PRIMARY_PLANE		1
+#define VFIO_CURSOR_PLANE		2

I think we should use "enum drm_plane_type" values instead of creating something new.

cheers,
Gerd

User space will try to create a management fd for the dma-buf operation. Using this management fd user can query the plane information and create a dma-buf fd if necessary.
GVT-g will handle the life cycle of the management fd and will align the life cycle of the fd with the vfio device.
User space should handle the life cycle of the created dma-buf fd close the dma-buf fd timely when finishing use.

Signed-off-by Xiaoguang Chen <[email protected]>

---
 drivers/gpu/drm/i915/gvt/dmabuf.c     |  25 ++++----
 drivers/gpu/drm/i915/gvt/dmabuf.h     |  21 -------
 drivers/gpu/drm/i915/gvt/fb_decoder.h |   2 -
 drivers/gpu/drm/i915/gvt/gvt.c        |   2 +
 drivers/gpu/drm/i915/gvt/gvt.h        |   4 ++
 drivers/gpu/drm/i915/gvt/kvmgt.c      | 107 ++++++++++++++++++++++++++++++++++
 include/uapi/linux/vfio.h             |  50 +++++++++++++++-
 7 files changed, 175 insertions(+), 36 deletions(-)

drivers/gpu/drm/i915/gvt/dmabuf.c +13 -12

index 415453b..a72b86efb 100644
@@ -29,6 +29,7 @@
 
 #include <linux/dma-buf.h>
 #include <drm/drmP.h>
+#include <linux/vfio.h>
 
 #include "i915_drv.h"
 #include "gvt.h"

@@ -45,9 +46,9 @@ static struct sg_table *intel_vgpu_gem_get_pages(
 	int i, ret;
 	gen8_pte_t __iomem *gtt_entries;
 	unsigned int fb_gma = 0, fb_size = 0;
-	struct intel_vgpu_plane_info *plane_info;
+	struct plane_info *plane_info;
 
-	plane_info = (struct intel_vgpu_plane_info *)obj->gvt_plane_info;
+	plane_info = (struct plane_info *)obj->gvt_plane_info;
 	if (WARN_ON(!plane_info))
 		return ERR_PTR(-EINVAL);
 

@@ -81,9 +82,9 @@ static struct sg_table *intel_vgpu_gem_get_pages(
 static void intel_vgpu_gem_put_pages(struct drm_i915_gem_object *obj,
 		struct sg_table *pages)
 {
-	struct intel_vgpu_plane_info *plane_info;
+	struct plane_info *plane_info;
 
-	plane_info = (struct intel_vgpu_plane_info *)obj->gvt_plane_info;
+	plane_info = (struct plane_info *)obj->gvt_plane_info;
 	if (WARN_ON(!plane_info))
 		return;
 

@@ -98,7 +99,7 @@ static const struct drm_i915_gem_object_ops intel_vgpu_gem_ops = {
 };
 
 static struct drm_i915_gem_object *intel_vgpu_create_gem(struct drm_device *dev,
-		struct intel_vgpu_plane_info *info)
+		struct plane_info *info)
 {
 	struct drm_i915_private *pri = dev->dev_private;
 	struct drm_i915_gem_object *obj;

@@ -141,14 +142,14 @@ static struct drm_i915_gem_object *intel_vgpu_create_gem(struct drm_device *dev,
 	return obj;
 }
 
-static struct intel_vgpu_plane_info *intel_vgpu_get_plane_info(
+static struct plane_info *intel_vgpu_get_plane_info(
 		struct drm_device *dev,
 		struct intel_vgpu *vgpu, uint32_t plane_id)
 {
 	struct drm_i915_private *dev_priv = dev->dev_private;
 	struct intel_vgpu_primary_plane_format *p;
 	struct intel_vgpu_cursor_plane_format *c;
-	struct intel_vgpu_plane_info *info;
+	struct plane_info *info;
 	struct intel_vgpu_pipe_format *pipe;
 
 	info = kmalloc(sizeof(*info), GFP_KERNEL);

@@ -159,7 +160,7 @@ static struct intel_vgpu_plane_info *intel_vgpu_get_plane_info(
 	if (pipe == NULL)
 		return NULL;
 
-	if (plane_id == INTEL_GVT_PLANE_PRIMARY) {
+	if (plane_id == VFIO_PRIMARY_PLANE) {
 		p = &pipe->primary;
 		if (p != NULL) {
 			info->start = p->base;

@@ -175,7 +176,7 @@ static struct intel_vgpu_plane_info *intel_vgpu_get_plane_info(
 			gvt_vgpu_err("invalid primary plane\n");
 			return NULL;
 		}
-	} else if (plane_id == INTEL_GVT_PLANE_CURSOR) {
+	} else if (plane_id == VFIO_CURSOR_PLANE) {
 		c = &pipe->cursor;
 		if (c != NULL) {
 			info->start = c->base;

@@ -228,7 +229,7 @@ static struct intel_vgpu_plane_info *intel_vgpu_get_plane_info(
 int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args)
 {
 	struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
-	struct intel_vgpu_plane_info *info = args;
+	struct plane_info *info = args;
 
 	info = intel_vgpu_get_plane_info(dev, vgpu, info->plane_id);
 	if (info == NULL)

@@ -242,8 +243,8 @@ int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args)
 	struct dma_buf *dmabuf;
 	struct drm_i915_gem_object *obj;
 	struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
-	struct intel_vgpu_dmabuf *gvt_dmabuf = args;
-	struct intel_vgpu_plane_info *info;
+	struct dmabuf_info *gvt_dmabuf = args;
+	struct plane_info *info;
 	int ret;
 
 	info = intel_vgpu_get_plane_info(dev, vgpu,

drivers/gpu/drm/i915/gvt/dmabuf.h +0 -21

index 43562af..e49bd4f 100644
@@ -26,27 +26,6 @@
 #ifndef _GVT_DMABUF_H_
 #define _GVT_DMABUF_H_
 
-struct intel_vgpu_plane_info {
-	uint32_t plane_id;
-	uint32_t drm_format;
-	uint32_t width;
-	uint32_t height;
-	uint32_t stride;
-	uint32_t start;
-	uint32_t x_pos;
-	uint32_t y_pos;
-	uint32_t size;
-	uint64_t drm_format_mod;
-};
-
-#define INTEL_VGPU_QUERY_PLANE		0
-#define INTEL_VGPU_GENERATE_DMABUF	1
-
-struct intel_vgpu_dmabuf {
-	uint32_t fd;
-	struct intel_vgpu_plane_info plane_info;
-};
-
 int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args);
 int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args);
 

drivers/gpu/drm/i915/gvt/fb_decoder.h +0 -2

index 1fd597f..96248ed 100644
@@ -81,8 +81,6 @@
 #define _SPRITE_OFFSET_START_X_MASK	(0x1fff << _SPRITE_OFFSET_START_X_SHIFT)
 #define _SPRITE_OFFSET_START_Y_MASK	(0xfff << _SPRITE_OFFSET_START_Y_SHIFT)
 
-#define INTEL_GVT_PLANE_PRIMARY		1
-#define INTEL_GVT_PLANE_CURSOR		2
 #define INTEL_GVT_PLANE_SPRITE		3
 
 enum GVT_FB_EVENT {

drivers/gpu/drm/i915/gvt/gvt.c +2 -0

index 2032917..dbc3f86 100644
@@ -54,6 +54,8 @@ static const struct intel_gvt_ops intel_gvt_ops = {
 	.vgpu_reset = intel_gvt_reset_vgpu,
 	.vgpu_activate = intel_gvt_activate_vgpu,
 	.vgpu_deactivate = intel_gvt_deactivate_vgpu,
+	.vgpu_query_plane = intel_vgpu_query_plane,
+	.vgpu_create_dmabuf = intel_vgpu_create_dmabuf,
 };
 
 /**

drivers/gpu/drm/i915/gvt/gvt.h +4 -0

index 763a8c5..0be422d 100644
@@ -185,8 +185,10 @@ struct intel_vgpu {
 		struct kvm *kvm;
 		struct work_struct release_work;
 		atomic_t released;
+		struct vfio_device *vfio_device;
 	} vdev;
 #endif
+	int dmabuf_mgr_fd;
 };
 
 struct intel_gvt_gm {

@@ -467,6 +469,8 @@ struct intel_gvt_ops {
 	void (*vgpu_reset)(struct intel_vgpu *);
 	void (*vgpu_activate)(struct intel_vgpu *);
 	void (*vgpu_deactivate)(struct intel_vgpu *);
+	int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *);
+	int (*vgpu_create_dmabuf)(struct intel_vgpu *vgpu, void *);
 };
 
 

drivers/gpu/drm/i915/gvt/kvmgt.c +107 -0

index 389f072..765d742 100644
@@ -41,6 +41,7 @@
 #include <linux/kvm_host.h>
 #include <linux/vfio.h>
 #include <linux/mdev.h>
+#include <linux/anon_inodes.h>
 
 #include "i915_drv.h"
 #include "gvt.h"

@@ -524,6 +525,85 @@ static int intel_vgpu_reg_init_opregion(struct intel_vgpu *vgpu)
 	return ret;
 }
 
+static int intel_vgpu_dmabuf_mgr_fd_mmap(struct file *file,
+		struct vm_area_struct *vma)
+{
+	return -EPERM;
+}
+
+static int intel_vgpu_dmabuf_mgr_fd_release(struct inode *inode,
+		struct file *filp)
+{
+	struct intel_vgpu *vgpu = filp->private_data;
+
+	if (WARN_ON(!vgpu->vdev.vfio_device))
+		return -EINVAL;
+
+	vfio_device_put(vgpu->vdev.vfio_device);
+
+	return 0;
+}
+
+static long intel_vgpu_dmabuf_mgr_fd_ioctl(struct file *filp,
+		unsigned int ioctl, unsigned long arg)
+{
+	struct intel_vgpu *vgpu = filp->private_data;
+	int minsz;
+	int ret;
+	struct fd f;
+
+	f = fdget(vgpu->dmabuf_mgr_fd);
+	if (!f.file)
+		return -EBADF;
+
+	if (ioctl == VFIO_DEVICE_QUERY_PLANE) {
+		struct plane_info info;
+
+		minsz = offsetofend(struct plane_info, drm_format_mod);
+		if (copy_from_user(&info, (void __user *)arg, minsz)) {
+			fdput(f);
+			return -EFAULT;
+		}
+		ret = intel_gvt_ops->vgpu_query_plane(vgpu, &info);
+		if (ret != 0) {
+			fdput(f);
+			gvt_vgpu_err("query plane failed:%d\n", ret);
+			return -EINVAL;
+		}
+		fdput(f);
+		return copy_to_user((void __user *)arg, &info, minsz) ?
+								-EFAULT : 0;
+	} else if (ioctl == VFIO_DEVICE_CREATE_DMABUF) {
+		struct dmabuf_info dmabuf;
+
+		minsz = offsetofend(struct dmabuf_info, plane_info);
+		if (copy_from_user(&dmabuf, (void __user *)arg, minsz)) {
+			fdput(f);
+			return -EFAULT;
+		}
+		ret = intel_gvt_ops->vgpu_create_dmabuf(vgpu, &dmabuf);
+		if (ret != 0) {
+			fdput(f);
+			gvt_vgpu_err("create dmabuf failed:%d\n", ret);
+			return -EINVAL;
+		}
+		fdput(f);
+		return copy_to_user((void __user *)arg, &dmabuf, minsz) ?
+								-EFAULT : 0;
+	}
+
+	fdput(f);
+	gvt_vgpu_err("unsupported dmabuf operation\n");
+
+	return -EINVAL;
+}
+
+static const struct file_operations intel_vgpu_dmabuf_mgr_fd_ops = {
+	.release        = intel_vgpu_dmabuf_mgr_fd_release,
+	.unlocked_ioctl = intel_vgpu_dmabuf_mgr_fd_ioctl,
+	.mmap           = intel_vgpu_dmabuf_mgr_fd_mmap,
+	.llseek         = noop_llseek,
+};
 static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
 {
 	struct intel_vgpu *vgpu = NULL;

@@ -1259,6 +1339,33 @@ static long intel_vgpu_ioctl(struct mdev_device *mdev, unsigned int cmd,
 	} else if (cmd == VFIO_DEVICE_RESET) {
 		intel_gvt_ops->vgpu_reset(vgpu);
 		return 0;
+	} else if (cmd == VFIO_DEVICE_GET_FD) {
+		int fd;
+		u32 type;
+		struct vfio_device *device;
+
+		if (copy_from_user(&type, (void __user *)arg, sizeof(type)))
+			return -EINVAL;
+		if (type != VFIO_DEVICE_DMABUF_MGR_FD)
+			return -EINVAL;
+
+		device = vfio_device_get_from_dev(mdev_dev(mdev));
+		if (device == NULL) {
+			gvt_vgpu_err("kvmgt: vfio device is null\n");
+			return -EINVAL;
+		}
+		vgpu->vdev.vfio_device = device;
+
+		fd = anon_inode_getfd("intel-vgpu-dmabuf-mgr-fd",
+			&intel_vgpu_dmabuf_mgr_fd_ops,
+			vgpu, O_RDWR | O_CLOEXEC);
+		if (fd < 0) {
+			gvt_vgpu_err("create dmabuf mgr fd failed\n");
+			return -EINVAL;
+		}
+		vgpu->dmabuf_mgr_fd = fd;
+
+		return fd;
 	}
 
 	return 0;

include/uapi/linux/vfio.h +20 -0

index ae46105..285dc16 100644
@@ -502,10 +502,58 @@ struct vfio_pci_hot_reset {
 
 #define VFIO_DEVICE_PCI_HOT_RESET	_IO(VFIO_TYPE, VFIO_BASE + 13)
 
+/**
+ * VFIO_DEVICE_GET_FD - _IO(VFIO_TYPE, VFIO_BASE + 14, __u32)
+ *
+ * Create a fd for a vfio device based on the input type
+ * Vendor driver should handle this ioctl to create a fd and manage the
+ * life cycle of this fd.
+ *
+ * Return: a fd if vendor support that type, -errno if not supported
+ */
+
+#define VFIO_DEVICE_GET_FD	_IO(VFIO_TYPE, VFIO_BASE + 14)
+
+#define VFIO_DEVICE_DMABUF_MGR_FD	0 /* Supported fd types */
+
+/*
+ * VFIO_DEVICE_QUERY_PLANE - _IO(VFIO_TYPE, VFIO_BASE + 15, struct plane_info)
+ * Query plane information for a plane
+ */
+struct plane_info {
+	__u32 plane_id;

include/uapi/linux/vfio.h +7 -0

+
+#define VFIO_PRIMARY_PLANE		1
+#define VFIO_CURSOR_PLANE		2
+
+#define VFIO_DEVICE_QUERY_PLANE _IO(VFIO_TYPE, VFIO_BASE + 15)
+
+/*