drm/i915/gvt: Dma-buf support for GVT-g

OpRegion is needed to support display related operation for intel vgpu.

A vfio device region is added to intel vgpu to deliver the host OpRegion information to user space so user space can construct the OpRegion for vgpu.

Signed-off-by Bing Niu <[email protected]>

Signed-off-by Xiaoguang Chen <[email protected]>

---
 drivers/gpu/drm/i915/gvt/kvmgt.c    | 97 +++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/opregion.c |  8 ++-
 2 files changed, 104 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/gvt/kvmgt.c +88 -0

index 3c6a02b..389f072 100644
@@ -53,6 +53,8 @@ static const struct intel_gvt_ops *intel_gvt_ops;
 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) << VFIO_PCI_OFFSET_SHIFT)
 #define VFIO_PCI_OFFSET_MASK    (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
 
+#define OPREGION_SIGNATURE "IntelGraphicsMem"
+
 struct vfio_region;
 struct intel_vgpu_regops {
 	size_t (*rw)(struct intel_vgpu *vgpu, char *buf,

@@ -436,6 +438,92 @@ static void kvmgt_protect_table_del(struct kvmgt_guest_info *info,
 	}
 }
 
+static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf,
+		size_t count, loff_t *ppos, bool iswrite)
+{
+	unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) -
+			VFIO_PCI_NUM_REGIONS;
+	void *base = vgpu->vdev.region[i].data;
+	loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
+
+	if (pos >= vgpu->vdev.region[i].size || iswrite) {
+		gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n");
+		return -EINVAL;
+	}
+	count = min(count, (size_t)(vgpu->vdev.region[i].size - pos));
+	memcpy(buf, base + pos, count);
+
+	return count;
+}
+
+static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu,
+		struct vfio_region *region)
+{
+	memunmap(region->data);
+}
+
+static const struct intel_vgpu_regops intel_vgpu_regops_opregion = {
+	.rw = intel_vgpu_reg_rw_opregion,
+	.release = intel_vgpu_reg_release_opregion,
+};
+
+static int intel_vgpu_register_reg(struct intel_vgpu *vgpu,
+		unsigned int type, unsigned int subtype,
+		const struct intel_vgpu_regops *ops,
+		size_t size, u32 flags, void *data)
+{
+	struct vfio_region *region;
+
+	region = krealloc(vgpu->vdev.region,
+			(vgpu->vdev.num_regions + 1) * sizeof(*region),
+			GFP_KERNEL);
+	if (!region)
+		return -ENOMEM;
+
+	vgpu->vdev.region = region;
+	vgpu->vdev.region[vgpu->vdev.num_regions].type = type;
+	vgpu->vdev.region[vgpu->vdev.num_regions].subtype = subtype;
+	vgpu->vdev.region[vgpu->vdev.num_regions].ops = ops;
+	vgpu->vdev.region[vgpu->vdev.num_regions].size = size;
+	vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags;
+	vgpu->vdev.region[vgpu->vdev.num_regions].data = data;
+	vgpu->vdev.num_regions++;
+
+	return 0;
+}
+
+static int intel_vgpu_reg_init_opregion(struct intel_vgpu *vgpu)
+{
+	unsigned int addr;
+	void *base;
+	int ret;
+
+	addr = vgpu->gvt->opregion.opregion_pa;
+	if (!addr || !(~addr))
+		return -ENODEV;
+
+	base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB);
+	if (!base)
+		return -ENOMEM;
+
+	if (memcmp(base, OPREGION_SIGNATURE, 16)) {
+		memunmap(base);
+		return -EINVAL;
+	}
+
+	ret = intel_vgpu_register_reg(vgpu,
+			PCI_VENDOR_ID_INTEL | VFIO_REGION_TYPE_PCI_VENDOR_TYPE,
+			VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION,
+			&intel_vgpu_regops_opregion, OPREGION_SIZE,
+			VFIO_REGION_INFO_FLAG_READ, base);
+	if (ret) {
+		memunmap(base);
+		return ret;
+	}
+
+	return ret;
+}
+
 static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev)
 {
 	struct intel_vgpu *vgpu = NULL;

drivers/gpu/drm/i915/gvt/kvmgt.c +4 -0

+
+	gvt_dbg_core("create OpRegion succeeded for mdev:%s\n",
+			dev_name(mdev_dev(mdev)));
+
 	gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n",
 		     dev_name(mdev_dev(mdev)));
 	ret = 0;

drivers/gpu/drm/i915/gvt/opregion.c +1 -0

index 3117991..5c7496d 100644
@@ -114,6 +114,7 @@ void intel_vgpu_clean_opregion(struct intel_vgpu *vgpu)
 int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa)
 {
 	int ret;
+	unsigned long pfn;
 
 	gvt_dbg_core("vgpu%d: init vgpu opregion\n", vgpu->id);
 

drivers/gpu/drm/i915/gvt/opregion.c +0 -0

 	return 0;
 }

Signature · 1 line

2.7.4

-----Original Message-----
From: intel-gvt-dev [mailto:[email protected]] On Behalf Of Zhenyu Wang
Sent: Wednesday, May 31, 2017 12:47 PM
To: Chen, Xiaoguang <[email protected]>
Cc: Tian, Kevin <[email protected]>; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Niu, Bing <[email protected]>; [email protected]; Wang, Zhi A <[email protected]>; Lv, Zhiyuan <[email protected]>
Subject: Re: [PATCH v6 2/6] drm/i915/gvt: OpRegion support for GVT-g

Quoted 11 lines · Xiaoguang Chen

OpRegion is needed to support display related operation for intel vgpu.

A vfio device region is added to intel vgpu to deliver the host OpRegion information to user space so user space can construct the OpRegion for vgpu.

Signed-off-by Bing Niu <[email protected]>

Signed-off-by Xiaoguang Chen <[email protected]>

---
 drivers/gpu/drm/i915/gvt/kvmgt.c    | 97

+++++++++++++++++++++++++++++++++++++

drivers/gpu/drm/i915/gvt/kvmgt.c static const struct intel_gvt_ops *intel_gvt_ops; · line 53

Quoted 10 lines

 drivers/gpu/drm/i915/gvt/opregion.c |  8 ++-
 2 files changed, 104 insertions(+), 1 deletion(-)

drivers/gpu/drm/i915/gvt/kvmgt.c +0 -0

index 3c6a02b..389f072 100644
@@ -53,6 +53,8 @@ static const struct intel_gvt_ops *intel_gvt_ops;
 #define VFIO_PCI_INDEX_TO_OFFSET(index) ((u64)(index) <<

VFIO_PCI_OFFSET_SHIFT)

Quoted 72 lines

drivers/gpu/drm/i915/gvt/kvmgt.c +2 -0

 #define VFIO_PCI_OFFSET_MASK    (((u64)(1) << VFIO_PCI_OFFSET_SHIFT) - 1)
 
+#define OPREGION_SIGNATURE "IntelGraphicsMem"
+
 struct vfio_region;
 struct intel_vgpu_regops {
 	size_t (*rw)(struct intel_vgpu *vgpu, char *buf, @@ -436,6 +438,92

@@ static void kvmgt_protect_table_del(struct kvmgt_guest_info *info,

drivers/gpu/drm/i915/gvt/kvmgt.c +61 -0

 	}
 }
 
+static size_t intel_vgpu_reg_rw_opregion(struct intel_vgpu *vgpu, char *buf,
+		size_t count, loff_t *ppos, bool iswrite) {
+	unsigned int i = VFIO_PCI_OFFSET_TO_INDEX(*ppos) -
+			VFIO_PCI_NUM_REGIONS;
+	void *base = vgpu->vdev.region[i].data;
+	loff_t pos = *ppos & VFIO_PCI_OFFSET_MASK;
+
+	if (pos >= vgpu->vdev.region[i].size || iswrite) {
+		gvt_vgpu_err("invalid op or offset for Intel vgpu OpRegion\n");
+		return -EINVAL;
+	}
+	count = min(count, (size_t)(vgpu->vdev.region[i].size - pos));
+	memcpy(buf, base + pos, count);
+
+	return count;
+}
+
+static void intel_vgpu_reg_release_opregion(struct intel_vgpu *vgpu,
+		struct vfio_region *region)
+{
+	memunmap(region->data);
+}
+
+static const struct intel_vgpu_regops intel_vgpu_regops_opregion = {
+	.rw = intel_vgpu_reg_rw_opregion,
+	.release = intel_vgpu_reg_release_opregion, };
+
+static int intel_vgpu_register_reg(struct intel_vgpu *vgpu,
+		unsigned int type, unsigned int subtype,
+		const struct intel_vgpu_regops *ops,
+		size_t size, u32 flags, void *data) {
+	struct vfio_region *region;
+
+	region = krealloc(vgpu->vdev.region,
+			(vgpu->vdev.num_regions + 1) * sizeof(*region),
+			GFP_KERNEL);
+	if (!region)
+		return -ENOMEM;
+
+	vgpu->vdev.region = region;
+	vgpu->vdev.region[vgpu->vdev.num_regions].type = type;
+	vgpu->vdev.region[vgpu->vdev.num_regions].subtype = subtype;
+	vgpu->vdev.region[vgpu->vdev.num_regions].ops = ops;
+	vgpu->vdev.region[vgpu->vdev.num_regions].size = size;
+	vgpu->vdev.region[vgpu->vdev.num_regions].flags = flags;
+	vgpu->vdev.region[vgpu->vdev.num_regions].data = data;
+	vgpu->vdev.num_regions++;
+
+	return 0;
+}
+
+static int intel_vgpu_reg_init_opregion(struct intel_vgpu *vgpu) {
+	unsigned int addr;
+	void *base;
+	int ret;
+
+	addr = vgpu->gvt->opregion.opregion_pa;
+	if (!addr || !(~addr))
+		return -ENODEV;
+
+	base = memremap(addr, OPREGION_SIZE, MEMREMAP_WB);

drivers/gpu/drm/i915/gvt/kvmgt.c static void kvmgt_protect_table_del(struct kvmgt_guest_info *info,

Quoted 10 lines

drivers/gpu/drm/i915/gvt/kvmgt.c +10 -0

+	if (!base)
+		return -ENOMEM;
+
+	if (memcmp(base, OPREGION_SIGNATURE, 16)) {
+		memunmap(base);
+		return -EINVAL;
+	}
+
+	ret = intel_vgpu_register_reg(vgpu,
+			PCI_VENDOR_ID_INTEL |

VFIO_REGION_TYPE_PCI_VENDOR_TYPE,

drivers/gpu/drm/i915/gvt/kvmgt.c static int intel_vgpu_create(struct kobject *kobj,

Quoted 15 lines

drivers/gpu/drm/i915/gvt/kvmgt.c +11 -0

+			VFIO_REGION_SUBTYPE_INTEL_IGD_OPREGION,
+			&intel_vgpu_regops_opregion, OPREGION_SIZE,
+			VFIO_REGION_INFO_FLAG_READ, base);
+	if (ret) {
+		memunmap(base);
+		return ret;
+	}
+
+	return ret;
+}
+
 static int intel_vgpu_create(struct kobject *kobj, struct mdev_device

*mdev) {

drivers/gpu/drm/i915/gvt/kvmgt.c +0 -0

 	struct intel_vgpu *vgpu = NULL;

@@ -467,6 +555,15 @@ static int intel_vgpu_create(struct kobject *kobj,

struct mdev_device *mdev)

Quoted 3 lines

drivers/gpu/drm/i915/gvt/kvmgt.c +0 -0

 	vgpu->vdev.mdev = mdev;
 	mdev_set_drvdata(mdev, vgpu);
 

drivers/gpu/drm/i915/gvt/kvmgt.c static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev) · line 562

Quoted 5 lines

drivers/gpu/drm/i915/gvt/kvmgt.c +5 -0

+	ret = intel_vgpu_reg_init_opregion(vgpu);
+	if (ret) {
+		gvt_vgpu_err("create OpRegion failed\n");
+		goto out;
+	}

Still need to handle error path for created vgpu.

drivers/gpu/drm/i915/gvt/opregion.c int intel_vgpu_init_opregion(struct intel_vgpu *vgpu,

Quoted 22 lines

drivers/gpu/drm/i915/gvt/kvmgt.c +4 -0

+
+	gvt_dbg_core("create OpRegion succeeded for mdev:%s\n",
+			dev_name(mdev_dev(mdev)));
+
 	gvt_dbg_core("intel_vgpu_create succeeded for mdev: %s\n",
 		     dev_name(mdev_dev(mdev)));
 	ret = 0;

drivers/gpu/drm/i915/gvt/opregion.c +1 -0

index 3117991..5c7496d 100644
@@ -114,6 +114,7 @@ void intel_vgpu_clean_opregion(struct intel_vgpu
 *vgpu)  int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa)
 {
 	int ret;
+	unsigned long pfn;
 
 	gvt_dbg_core("vgpu%d: init vgpu opregion\n", vgpu->id);
 

@@ -127,7 +128,12 @@ int intel_vgpu_init_opregion(struct intel_vgpu *vgpu,

u32 gpa)

drivers/gpu/drm/i915/gvt/opregion.c int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa)

Quoted 6 lines

drivers/gpu/drm/i915/gvt/opregion.c +2 -1

 		ret = map_vgpu_opregion(vgpu, true);
 		if (ret)
 			return ret;
-	}
+	} else {
+		pfn = intel_gvt_hypervisor_gfn_to_mfn(vgpu, gpa >>

PAGE_SHIFT);

drivers/gpu/drm/i915/gvt/opregion.c int intel_vgpu_init_opregion(struct intel_vgpu *vgpu, u32 gpa) · line 136

Quoted 4 lines

drivers/gpu/drm/i915/gvt/opregion.c +4 -0

+		vgpu_opregion(vgpu)->va = memremap(pfn << PAGE_SHIFT,
+						INTEL_GVT_OPREGION_SIZE,
+						MEMREMAP_WB);
+		}

better to use switch for explicit KVM case, and no return check?

Quoted 7 lines

drivers/gpu/drm/i915/gvt/opregion.c +0 -1

 	return 0;
 }
--

2.7.4

--
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827

Quoted 5 lines

Review static int intel_vgpu_create(struct kobject *kobj,

Quoted 1 line

(quoted diff) +0 -0

@@ -467,6 +555,15 @@ static int intel_vgpu_create(struct kobject *kobj,

struct mdev_device *mdev)

Quoted 3 lines

drivers/gpu/drm/i915/gvt/kvmgt.c +0 -0

 	vgpu->vdev.mdev = mdev;
 	mdev_set_drvdata(mdev, vgpu);
 

Quoted 7 lines

drivers/gpu/drm/i915/gvt/kvmgt.c static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev) · line 562

Quoted 5 lines

drivers/gpu/drm/i915/gvt/kvmgt.c +5 -0

+	ret = intel_vgpu_reg_init_opregion(vgpu);
+	if (ret) {
+		gvt_vgpu_err("create OpRegion failed\n");
+		goto out;
+	}

Still need to handle error path for created vgpu.

Just checked the code, if initialize the opregion failed we should first release vfio/mdev releated work(maybe call intel_vgpu_release function) and then destroy the vgpu. Will update in the next version.

-----Original Message-----
From: Zhenyu Wang [mailto:[email protected]]
Sent: Wednesday, May 31, 2017 2:30 PM
To: Chen, Xiaoguang <[email protected]>
Cc: Tian, Kevin <[email protected]>; [email protected]; linux- [email protected]; [email protected]; [email protected]; [email protected]; Niu, Bing <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Lv, Zhiyuan <[email protected]>
Subject: Re: [PATCH v6 2/6] drm/i915/gvt: OpRegion support for GVT-g

Quoted 13 lines · Xiaoguang

Quoted 13 lines

Review static int intel_vgpu_create(struct kobject · line 555

Quoted 2 lines

(quoted diff) +0 -0

@@ -467,6 +555,15 @@ static int intel_vgpu_create(struct kobject
 *kobj,

struct mdev_device *mdev)

drivers/gpu/drm/i915/gvt/kvmgt.c static int intel_vgpu_create(struct kobject *kobj, struct mdev_device *mdev) · line 562

Quoted 8 lines

drivers/gpu/drm/i915/gvt/kvmgt.c +5 -0

 	vgpu->vdev.mdev = mdev;
 	mdev_set_drvdata(mdev, vgpu);
 
+	ret = intel_vgpu_reg_init_opregion(vgpu);
+	if (ret) {
+		gvt_vgpu_err("create OpRegion failed\n");
+		goto out;
+	}

Still need to handle error path for created vgpu.

Quoted 1 line

Just checked the code, if initialize the opregion failed we should first release

vfio/mdev releated work(maybe call intel_vgpu_release function) and then destroy the vgpu. Will update in the next version.

Quoted 1 line

Better to init opregion inside of create vgpu and do proper error handling there too.

--
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827

decode frambuffer attributes of primary, cursor and sprite plane

Signed-off-by Xiaoguang Chen <[email protected]>

---
 drivers/gpu/drm/i915/gvt/Makefile     |   3 +-
 drivers/gpu/drm/i915/gvt/display.c    |   2 +-
 drivers/gpu/drm/i915/gvt/display.h    |   2 +
 drivers/gpu/drm/i915/gvt/fb_decoder.c | 479 ++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/fb_decoder.h | 166 ++++++++++++
 drivers/gpu/drm/i915/gvt/gvt.h        |   1 +
 6 files changed, 651 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h

drivers/gpu/drm/i915/gvt/Makefile +2 -1

index b123c20..192ca26 100644
@@ -1,7 +1,8 @@
 GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
 	interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
-	execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
+	execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
+	fb_decoder.o
 
 ccflags-y				+= -I$(src) -I$(src)/$(GVT_DIR) -Wall
 i915-y					+= $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))

drivers/gpu/drm/i915/gvt/display.c +1 -1

index e0261fc..f5f63c5 100644
@@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
 	return 1;
 }
 
-static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
 {
 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 

drivers/gpu/drm/i915/gvt/display.h +2 -0

index d73de22..b46b868 100644
@@ -179,4 +179,6 @@ int intel_vgpu_init_display(struct intel_vgpu *vgpu, u64 resolution);
 void intel_vgpu_reset_display(struct intel_vgpu *vgpu);
 void intel_vgpu_clean_display(struct intel_vgpu *vgpu);
 
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
+
 #endif

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +34 -0

new file mode 100644
index 0000000..d4404fd
@@ -0,0 +1,479 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Kevin Tian <[email protected]>
+ *
+ * Contributors:
+ *    Bing Niu <[email protected]>
+ *    Xu Han <[email protected]>
+ *    Ping Gao <[email protected]>
+ *    Xiaoguang Chen <[email protected]>
+ *    Yang Liu <[email protected]>
+ *
+ */
+

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +11 -0

+struct pixel_format {
+	int	drm_format;	/* Pixel format in DRM definition */
+	int	bpp;		/* Bits per pixel, 0 indicates invalid */
+	char *desc;		/* The description */
+};
+
+/* non-supported format has bpp default to 0 */
+static struct pixel_format primary_pixel_formats[FORMAT_NUM] = {
+	[0x2] = {DRM_FORMAT_C8, 8, "8-bit Indexed"},
+	[0x5] = {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
+	[0x6] = {DRM_FORMAT_XRGB8888, 32,

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +123 -0

+
+/* non-supported format has bpp default to 0 */
+static struct pixel_format skl_pixel_formats[] = {
+	{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-V:Y2:U:Y1)"},
+	{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-Y2:V:Y1:U)"},
+	{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-U:Y2:V:Y1)"},
+	{DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-Y2:U:Y1:V)"},
+
+	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
+	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
+	{DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
+	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
+
+	{DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
+	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
+	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},
+	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
+
+	{DRM_FORMAT_XRGB161616_GVT, 64,
+		"64-bit XRGB (16:16:16:16 MSB-X:R:G:B)"},
+	{DRM_FORMAT_XBGR161616_GVT, 64,
+		"64-bit XBGR (16:16:16:16 MSB-X:B:G:R)"},
+
+	/* non-supported format has bpp default to 0 */
+	{0, 0, NULL},
+};
+
+static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
+	int yuv_order)
+{
+	int skl_pixel_formats_index = 14;
+
+	switch (format) {
+	case PLANE_CTL_FORMAT_INDEXED:
+		skl_pixel_formats_index = 4;
+		break;
+	case PLANE_CTL_FORMAT_RGB_565:
+		skl_pixel_formats_index = 5;
+		break;
+	case PLANE_CTL_FORMAT_XRGB_8888:
+		if (rgb_order)
+			skl_pixel_formats_index = alpha ? 6 : 7;
+		else
+			skl_pixel_formats_index = alpha ? 8 : 9;
+		break;
+	case PLANE_CTL_FORMAT_XRGB_2101010:
+		skl_pixel_formats_index = rgb_order ? 10 : 11;
+		break;
+
+	case PLANE_CTL_FORMAT_XRGB_16161616F:
+		skl_pixel_formats_index = rgb_order ? 12 : 13;
+		break;
+
+	case PLANE_CTL_FORMAT_YUV422:
+		skl_pixel_formats_index = yuv_order >> 16;
+		if (skl_pixel_formats_index > 3)
+			return -EINVAL;
+		break;
+
+	default:
+		break;
+	}
+
+	return skl_pixel_formats_index;
+}
+
+static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
+	u32 tiled, int stride_mask, int bpp)
+{
+	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+	u32 stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask;
+	u32 stride = stride_reg;
+
+	if (IS_SKYLAKE(dev_priv)) {
+		switch (tiled) {
+		case PLANE_CTL_TILED_LINEAR:
+			stride = stride_reg * 64;
+			break;
+		case PLANE_CTL_TILED_X:
+			stride = stride_reg * 512;
+			break;
+		case PLANE_CTL_TILED_Y:
+			stride = stride_reg * 128;
+			break;
+		case PLANE_CTL_TILED_YF:
+			if (bpp == 8)
+				stride = stride_reg * 64;
+			else if (bpp == 16 || bpp == 32 || bpp == 64)
+				stride = stride_reg * 128;
+			else
+				gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
+			break;
+		default:
+			gvt_dbg_core("skl: unsupported tile format:%x\n",
+				tiled);
+		}
+	}
+
+	return stride;
+}
+
+static int intel_vgpu_decode_primary_plane_format(struct intel_vgpu *vgpu,
+	int pipe, struct intel_vgpu_primary_plane_format *plane)
+{
+	u32	val, fmt;
+	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+	val = vgpu_vreg(vgpu, DSPCNTR(pipe));
+	plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
+	if (!plane->enabled)
+		return 0;
+
+	if (IS_SKYLAKE(dev_priv)) {
+		plane->tiled = (val & PLANE_CTL_TILED_MASK) >>
+		_PLANE_CTL_TILED_SHIFT;
+		fmt = skl_format_to_drm(
+			val & PLANE_CTL_FORMAT_MASK,
+			val & PLANE_CTL_ORDER_RGBX,
+			val & PLANE_CTL_ALPHA_MASK,
+			val & PLANE_CTL_YUV422_ORDER_MASK);
+		plane->bpp = skl_pixel_formats[fmt].bpp;
+		plane->drm_format = skl_pixel_formats[fmt].drm_format;

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +19 -0

+		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
+		return -EINVAL;
+	}
+
+	plane->hw_format = fmt;
+
+	plane->base = vgpu_vreg(vgpu, DSPSURF(pipe)) & GTT_PAGE_MASK;
+
+	plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),
+		(IS_SKYLAKE(dev_priv)) ? (_PRI_PLANE_STRIDE_MASK >> 6) :
+		_PRI_PLANE_STRIDE_MASK, plane->bpp);
+
+	plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >>
+		_PIPE_H_SRCSZ_SHIFT;
+	plane->width += 1;
+	plane->height = (vgpu_vreg(vgpu, PIPESRC(pipe)) &
+			_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
+	plane->height += 1;	/* raw height is one minus the real value */
+

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +50 -0

+struct cursor_mode_format {
+	int	drm_format;	/* Pixel format in DRM definition */
+	u8	bpp;		/* Bits per pixel; 0 indicates invalid */
+	u32	width;		/* In pixel */
+	u32	height;		/* In lines */
+	char	*desc;		/* The description */
+};
+
+/* non-supported format has bpp default to 0 */
+static struct cursor_mode_format cursor_pixel_formats[CURSOR_MODE_NUM] = {
+	[0x22]  = {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp ARGB"},
+	[0x23]  = {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp ARGB"},
+	[0x27]  = {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
+	[0x7]  = {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
+};
+
+static int intel_vgpu_decode_cursor_plane_format(struct intel_vgpu *vgpu,
+	int pipe, struct intel_vgpu_cursor_plane_format *plane)
+{
+	u32 val, mode;
+	u32 alpha_plane, alpha_force;
+	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+	val = vgpu_vreg(vgpu, CURCNTR(pipe));
+	mode = val & CURSOR_MODE;
+	plane->enabled = (mode != CURSOR_MODE_DISABLE);
+	if (!plane->enabled)
+		return 0;
+
+	if (!cursor_pixel_formats[mode].bpp) {
+		gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
+		return -EINVAL;
+	}
+	plane->mode = mode;
+	plane->bpp = cursor_pixel_formats[mode].bpp;
+	plane->drm_format = cursor_pixel_formats[mode].drm_format;
+	plane->width = cursor_pixel_formats[mode].width;
+	plane->height = cursor_pixel_formats[mode].height;
+
+	alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
+				_CURSOR_ALPHA_PLANE_SHIFT;
+	alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
+				_CURSOR_ALPHA_FORCE_SHIFT;
+	if (alpha_plane || alpha_force)
+		gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
+			alpha_plane, alpha_force);
+
+	plane->base = vgpu_vreg(vgpu, CURBASE(pipe)) & GTT_PAGE_MASK;
+
+	val = vgpu_vreg(vgpu, CURPOS(pipe));

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +40 -0

+static struct pixel_format sprite_pixel_formats[FORMAT_NUM_SRRITE] = {
+	[0x0]  = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
+	[0x1]  = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
+	[0x2]  = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
+	[0x3]  = {DRM_FORMAT_XRGB161616_GVT, 64,
+		    "RGB 64-bit 16:16:16:16 Floating Point"},
+	[0x4] = {DRM_FORMAT_AYUV, 32,
+		"YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"},
+};
+
+static int intel_vgpu_decode_sprite_plane_format(struct intel_vgpu *vgpu,
+	int pipe, struct intel_vgpu_sprite_plane_format *plane)
+{
+	u32 val, fmt;
+	u32 width;
+	u32 color_order, yuv_order;
+	int drm_format;
+
+	val = vgpu_vreg(vgpu, SPRCTL(pipe));
+	plane->enabled = !!(val & SPRITE_ENABLE);
+	if (!plane->enabled)
+		return 0;
+
+	plane->tiled = !!(val & SPRITE_TILED);
+	color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
+	yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
+				_SPRITE_YUV_ORDER_SHIFT;
+
+	fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
+	if (!sprite_pixel_formats[fmt].bpp) {
+		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
+		return -EINVAL;
+	}
+	plane->hw_format = fmt;
+	plane->bpp = sprite_pixel_formats[fmt].bpp;
+	drm_format = sprite_pixel_formats[fmt].drm_format;
+
+	/* Order of RGB values in an RGBxxx buffer may be ordered RGB or
+	 * BGR depending on the state of the color_order field
+	 */

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +23 -0

+			drm_format = DRM_FORMAT_YUYV;
+			break;
+		case	1:
+			drm_format = DRM_FORMAT_UYVY;
+			break;
+		case	2:
+			drm_format = DRM_FORMAT_YVYU;
+			break;
+		case	3:
+			drm_format = DRM_FORMAT_VYUY;
+			break;
+		default:
+			/* yuv_order has only 2 bits */
+			break;
+		}
+	}
+
+	plane->drm_format = drm_format;
+
+	plane->base = vgpu_vreg(vgpu, SPRSURF(pipe)) & GTT_PAGE_MASK;
+	plane->width = vgpu_vreg(vgpu, SPRSTRIDE(pipe)) &
+				_SPRITE_STRIDE_MASK;
+	plane->width /= plane->bpp / 8;	/* raw width in bytes */

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +75 -0

+static int intel_vgpu_decode_fb_format(struct intel_gvt *gvt, int id,
+	struct intel_vgpu_fb_format *fb)
+{
+	int i;
+	struct intel_vgpu *vgpu = NULL;
+	int ret = 0;
+	struct drm_i915_private *dev_priv = gvt->dev_priv;
+
+	if (!fb)
+		return -EINVAL;
+
+	/* TODO: use fine-grained refcnt later */
+	mutex_lock(&gvt->lock);
+
+	for_each_active_vgpu(gvt, vgpu, i)
+		if (vgpu->id == id)
+			break;
+
+	if (!vgpu) {
+		gvt_vgpu_err("Invalid vgpu ID (%d)\n", id);
+		mutex_unlock(&gvt->lock);
+		return -ENODEV;
+	}
+
+	for (i = 0; i < I915_MAX_PIPES; i++) {
+		struct intel_vgpu_pipe_format *pipe = &fb->pipes[i];
+		u32 ddi_func_ctl = vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(i));
+
+		if (!(ddi_func_ctl & TRANS_DDI_FUNC_ENABLE)) {
+			pipe->ddi_port = DDI_PORT_NONE;
+		} else {
+			u32 port = (ddi_func_ctl & TRANS_DDI_PORT_MASK) >>
+						TRANS_DDI_PORT_SHIFT;
+			if (port <= DDI_PORT_E)
+				pipe->ddi_port = port;
+			else
+				pipe->ddi_port = DDI_PORT_NONE;
+		}
+
+		ret |= intel_vgpu_decode_primary_plane_format(vgpu,
+			i, &pipe->primary);
+		ret |= intel_vgpu_decode_sprite_plane_format(vgpu,
+			i, &pipe->sprite);
+		ret |= intel_vgpu_decode_cursor_plane_format(vgpu,
+			i, &pipe->cursor);
+
+		if (ret) {
+			gvt_vgpu_err("Decode format error for pipe(%d)\n", i);
+			ret = -EINVAL;
+			break;
+		}
+	}
+
+	mutex_unlock(&gvt->lock);
+
+	return ret;
+}
+
+/**
+ * intel_vgpu_decode_plane - Decode plane based on plane id
+ * @dev: drm device
+ * @vgpu: input vgpu
+ * This function is called for decoding plane
+ *
+ * Returns:
+ * pipe on success, NULL if failed.
+ */
+struct intel_vgpu_pipe_format *intel_vgpu_decode_plane(struct drm_device *dev,
+		struct intel_vgpu *vgpu)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_vgpu_fb_format fb;
+	struct intel_vgpu_pipe_format *pipe;
+	int i;
+

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +4 -0

+
+	return pipe;
+}
+

drivers/gpu/drm/i915/gvt/fb_decoder.h new file +1 -0

new file mode 100644
index 0000000..04300af
+

-----Original Message-----
From: Zhenyu Wang [mailto:[email protected]]
Sent: Wednesday, May 31, 2017 1:12 PM
To: Chen, Xiaoguang <[email protected]>
Cc: [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Lv, Zhiyuan <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Tian, Kevin <[email protected]>
Subject: Re: [PATCH v6 3/6] drm/i915/gvt: Frame buffer decoder support for GVT- g

Quoted 21 lines · Xiaoguang Chen

decode frambuffer attributes of primary, cursor and sprite plane

Signed-off-by Xiaoguang Chen <[email protected]>

---
 drivers/gpu/drm/i915/gvt/Makefile     |   3 +-
 drivers/gpu/drm/i915/gvt/display.c    |   2 +-
 drivers/gpu/drm/i915/gvt/display.h    |   2 +
 drivers/gpu/drm/i915/gvt/fb_decoder.c | 479
++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/fb_decoder.h | 166 ++++++++++++
 drivers/gpu/drm/i915/gvt/gvt.h        |   1 +
 6 files changed, 651 insertions(+), 2 deletions(-)  create mode
100644 drivers/gpu/drm/i915/gvt/fb_decoder.c
 create mode 100644 drivers/gpu/drm/i915/gvt/fb_decoder.h

drivers/gpu/drm/i915/gvt/Makefile +0 -0

index b123c20..192ca26 100644

drivers/gpu/drm/i915/gvt/Makefile line 2

Quoted 2 lines

drivers/gpu/drm/i915/gvt/Makefile +0 -0

@@ -1,7 +1,8 @@
 GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o

firmware.o \

drivers/gpu/drm/i915/gvt/Makefile

Quoted 7 lines

drivers/gpu/drm/i915/gvt/Makefile +2 -1

 	interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
-	execlist.o scheduler.o sched_policy.o render.o cmd_parser.o
+	execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
+	fb_decoder.o
 
 ccflags-y				+= -I$(src) -I$(src)/$(GVT_DIR) -Wall
 i915-y					+= $(addprefix $(GVT_DIR)/,

$(GVT_SOURCE))

Quoted 50 lines

drivers/gpu/drm/i915/gvt/display.c +1 -1

index e0261fc..f5f63c5 100644
@@ -67,7 +67,7 @@ static int edp_pipe_is_enabled(struct intel_vgpu *vgpu)
 	return 1;
 }
 
-static int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe)
 {
 	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
 

drivers/gpu/drm/i915/gvt/display.h +0 -0

index d73de22..b46b868 100644
@@ -179,4 +179,6 @@ int intel_vgpu_init_display(struct intel_vgpu
 *vgpu, u64 resolution);  void intel_vgpu_reset_display(struct

intel_vgpu *vgpu); void intel_vgpu_clean_display(struct intel_vgpu *vgpu);

drivers/gpu/drm/i915/gvt/display.h +2 -0

+int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe);
+
 #endif

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +16 -0

new file mode 100644
index 0000000..d4404fd
@@ -0,0 +1,479 @@
+/*
+ * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person
+obtaining a
+ * copy of this software and associated documentation files (the
+"Software"),
+ * to deal in the Software without restriction, including without
+limitation
+ * the rights to use, copy, modify, merge, publish, distribute,
+sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom
+the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including

drivers/gpu/drm/i915/gvt/fb_decoder.c line 26

Quoted 10 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +10 -0

+the next
+ * paragraph) shall be included in all copies or substantial portions
+of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO

EVENT

drivers/gpu/drm/i915/gvt/fb_decoder.c line 28

Quoted 2 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +2 -0

+SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,

DAMAGES

Quoted 23 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +23 -0

+OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+DEALINGS IN THE
+ * SOFTWARE.
+ *
+ * Authors:
+ *    Kevin Tian <[email protected]>
+ *
+ * Contributors:
+ *    Bing Niu <[email protected]>
+ *    Xu Han <[email protected]>
+ *    Ping Gao <[email protected]>
+ *    Xiaoguang Chen <[email protected]>
+ *    Yang Liu <[email protected]>
+ *
+ */
+
+#include <uapi/drm/drm_fourcc.h>
+#include "i915_drv.h"
+#include "gvt.h"
+

drivers/gpu/drm/i915/gvt/fb_decoder.c line 57

Quoted 6 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +6 -0

+/* The below definitions are required by guest. */ // [63:0] x:R:G:B
+16:16:16:16 little endian #define DRM_FORMAT_XRGB161616_GVT
+fourcc_code('X', 'R', '4', '8') // [63:0] x:B:G:R 16:16:16:16 little
+endian #define DRM_FORMAT_XBGR161616_GVT  fourcc_code('X', 'B', '4',
+'8')
+

Should be added to drm_fourcc?

drivers/gpu/drm/i915/gvt/fb_decoder.c line 45

Quoted 2 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +1 -0

+#define FORMAT_NUM	16

PRIMARY_FORMAT_NUM

Quoted 14 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +14 -0

+struct pixel_format {
+	int	drm_format;	/* Pixel format in DRM definition */
+	int	bpp;		/* Bits per pixel, 0 indicates invalid */
+	char *desc;		/* The description */
+};
+
+/* non-supported format has bpp default to 0 */ static struct
+pixel_format primary_pixel_formats[FORMAT_NUM] = {
+	[0x2] = {DRM_FORMAT_C8, 8, "8-bit Indexed"},
+	[0x5] = {DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
+	[0x6] = {DRM_FORMAT_XRGB8888, 32,
+		"32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
+	[0x8] = {DRM_FORMAT_XBGR2101010, 32,
+		"32-bit RGBX (2:10:10:10 MSB-X:B:G:R)"},

drivers/gpu/drm/i915/gvt/fb_decoder.c

Quoted 6 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +6 -0

+	[0xa] = {DRM_FORMAT_XRGB2101010, 32,
+		"32-bit BGRX (2:10:10:10 MSB-X:R:G:B)"},
+	[0xc] = {DRM_FORMAT_XRGB161616_GVT, 64,
+		"64-bit RGBX Floating Point(16:16:16:16 MSB-X:B:G:R)"},
+	[0xe] = {DRM_FORMAT_XBGR8888, 32,
+		"32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"}, };

might explicitly say this is bdw_pixel_formats?

drivers/gpu/drm/i915/gvt/fb_decoder.c line 82

Quoted 5 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +4 -0

+
+/* non-supported format has bpp default to 0 */ static struct
+pixel_format skl_pixel_formats[] = {
+	{DRM_FORMAT_YUYV, 16, "16-bit packed YUYV (8:8:8:8 MSB-

V:Y2:U:Y1)"},

drivers/gpu/drm/i915/gvt/fb_decoder.c line 83

Quoted 1 line

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +1 -0

+	{DRM_FORMAT_UYVY, 16, "16-bit packed UYVY (8:8:8:8 MSB-

Y2:V:Y1:U)"},

drivers/gpu/drm/i915/gvt/fb_decoder.c line 84

Quoted 1 line

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +1 -0

+	{DRM_FORMAT_YVYU, 16, "16-bit packed YVYU (8:8:8:8 MSB-

U:Y2:V:Y1)"},

drivers/gpu/drm/i915/gvt/fb_decoder.c line 85

Quoted 1 line

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +1 -0

+	{DRM_FORMAT_VYUY, 16, "16-bit packed VYUY (8:8:8:8 MSB-

Y2:U:Y1:V)"},

drivers/gpu/drm/i915/gvt/fb_decoder.c

Quoted 9 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +9 -0

+
+	{DRM_FORMAT_C8, 8, "8-bit Indexed"},
+	{DRM_FORMAT_RGB565, 16, "16-bit BGRX (5:6:5 MSB-R:G:B)"},
+	{DRM_FORMAT_ABGR8888, 32, "32-bit RGBA (8:8:8:8 MSB-A:B:G:R)"},
+	{DRM_FORMAT_XBGR8888, 32, "32-bit RGBX (8:8:8:8 MSB-X:B:G:R)"},
+
+	{DRM_FORMAT_ARGB8888, 32, "32-bit BGRA (8:8:8:8 MSB-A:R:G:B)"},
+	{DRM_FORMAT_XRGB8888, 32, "32-bit BGRX (8:8:8:8 MSB-X:R:G:B)"},
+	{DRM_FORMAT_XBGR2101010, 32, "32-bit RGBX (2:10:10:10 MSB-

X:B:G:R)"},

Quoted 99 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +99 -0

+	{DRM_FORMAT_XRGB2101010, 32, "32-bit BGRX (2:10:10:10
+MSB-X:R:G:B)"},
+
+	{DRM_FORMAT_XRGB161616_GVT, 64,
+		"64-bit XRGB (16:16:16:16 MSB-X:R:G:B)"},
+	{DRM_FORMAT_XBGR161616_GVT, 64,
+		"64-bit XBGR (16:16:16:16 MSB-X:B:G:R)"},
+
+	/* non-supported format has bpp default to 0 */
+	{0, 0, NULL},
+};
+
+static int skl_format_to_drm(int format, bool rgb_order, bool alpha,
+	int yuv_order)
+{
+	int skl_pixel_formats_index = 14;
+
+	switch (format) {
+	case PLANE_CTL_FORMAT_INDEXED:
+		skl_pixel_formats_index = 4;
+		break;
+	case PLANE_CTL_FORMAT_RGB_565:
+		skl_pixel_formats_index = 5;
+		break;
+	case PLANE_CTL_FORMAT_XRGB_8888:
+		if (rgb_order)
+			skl_pixel_formats_index = alpha ? 6 : 7;
+		else
+			skl_pixel_formats_index = alpha ? 8 : 9;
+		break;
+	case PLANE_CTL_FORMAT_XRGB_2101010:
+		skl_pixel_formats_index = rgb_order ? 10 : 11;
+		break;
+
+	case PLANE_CTL_FORMAT_XRGB_16161616F:
+		skl_pixel_formats_index = rgb_order ? 12 : 13;
+		break;
+
+	case PLANE_CTL_FORMAT_YUV422:
+		skl_pixel_formats_index = yuv_order >> 16;
+		if (skl_pixel_formats_index > 3)
+			return -EINVAL;
+		break;
+
+	default:
+		break;
+	}
+
+	return skl_pixel_formats_index;
+}
+
+static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe,
+	u32 tiled, int stride_mask, int bpp) {
+	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+	u32 stride_reg = vgpu_vreg(vgpu, DSPSTRIDE(pipe)) & stride_mask;
+	u32 stride = stride_reg;
+
+	if (IS_SKYLAKE(dev_priv)) {
+		switch (tiled) {
+		case PLANE_CTL_TILED_LINEAR:
+			stride = stride_reg * 64;
+			break;
+		case PLANE_CTL_TILED_X:
+			stride = stride_reg * 512;
+			break;
+		case PLANE_CTL_TILED_Y:
+			stride = stride_reg * 128;
+			break;
+		case PLANE_CTL_TILED_YF:
+			if (bpp == 8)
+				stride = stride_reg * 64;
+			else if (bpp == 16 || bpp == 32 || bpp == 64)
+				stride = stride_reg * 128;
+			else
+				gvt_dbg_core("skl: unsupported bpp:%d\n", bpp);
+			break;
+		default:
+			gvt_dbg_core("skl: unsupported tile format:%x\n",
+				tiled);
+		}
+	}
+
+	return stride;
+}
+
+static int intel_vgpu_decode_primary_plane_format(struct intel_vgpu *vgpu,
+	int pipe, struct intel_vgpu_primary_plane_format *plane) {
+	u32	val, fmt;
+	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+	val = vgpu_vreg(vgpu, DSPCNTR(pipe));
+	plane->enabled = !!(val & DISPLAY_PLANE_ENABLE);
+	if (!plane->enabled)
+		return 0;
+
+	if (IS_SKYLAKE(dev_priv)) {
+		plane->tiled = (val & PLANE_CTL_TILED_MASK) >>
+		_PLANE_CTL_TILED_SHIFT;

drivers/gpu/drm/i915/gvt/fb_decoder.c

Quoted 10 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +10 -0

+		fmt = skl_format_to_drm(
+			val & PLANE_CTL_FORMAT_MASK,
+			val & PLANE_CTL_ORDER_RGBX,
+			val & PLANE_CTL_ALPHA_MASK,
+			val & PLANE_CTL_YUV422_ORDER_MASK);
+		plane->bpp = skl_pixel_formats[fmt].bpp;
+		plane->drm_format = skl_pixel_formats[fmt].drm_format;
+	} else {
+		plane->tiled = !!(val & DISPPLANE_TILED);
+		fmt = (val & DISPPLANE_PIXFORMAT_MASK) >>

_PRI_PLANE_FMT_SHIFT;

drivers/gpu/drm/i915/gvt/fb_decoder.c line 199

Quoted 7 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +7 -0

+		plane->bpp = primary_pixel_formats[fmt].bpp;
+		plane->drm_format = primary_pixel_formats[fmt].drm_format;
+	}
+
+	if ((IS_SKYLAKE(dev_priv) && !skl_pixel_formats[fmt].bpp)
+		|| (!IS_SKYLAKE(dev_priv) &&
+			!primary_pixel_formats[fmt].bpp)) {

Just if (!plane->bpp)?

Quoted 4 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +3 -0

+		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
+		return -EINVAL;
+	}

drivers/gpu/drm/i915/gvt/fb_decoder.c

Quoted 10 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +10 -0

+
+	plane->hw_format = fmt;
+
+	plane->base = vgpu_vreg(vgpu, DSPSURF(pipe)) & GTT_PAGE_MASK;
+
+	plane->stride = intel_vgpu_get_stride(vgpu, pipe, (plane->tiled << 10),
+		(IS_SKYLAKE(dev_priv)) ? (_PRI_PLANE_STRIDE_MASK >> 6) :
+		_PRI_PLANE_STRIDE_MASK, plane->bpp);
+
+	plane->width = (vgpu_vreg(vgpu, PIPESRC(pipe)) &

_PIPE_H_SRCSZ_MASK) >>

Quoted 6 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +6 -0

+		_PIPE_H_SRCSZ_SHIFT;
+	plane->width += 1;
+	plane->height = (vgpu_vreg(vgpu, PIPESRC(pipe)) &
+			_PIPE_V_SRCSZ_MASK) >> _PIPE_V_SRCSZ_SHIFT;
+	plane->height += 1;	/* raw height is one minus the real value */
+

drivers/gpu/drm/i915/gvt/fb_decoder.c line 228

Quoted 10 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +10 -0

+	val = vgpu_vreg(vgpu, DSPTILEOFF(pipe));
+	plane->x_offset = (val & _PRI_PLANE_X_OFF_MASK) >>
+		_PRI_PLANE_X_OFF_SHIFT;
+	plane->y_offset = (val & _PRI_PLANE_Y_OFF_MASK) >>
+		_PRI_PLANE_Y_OFF_SHIFT;
+
+	return 0;
+}
+
+#define CURSOR_MODE_NUM	(1 << 6)

CURSOR_FORMAT_NUM

drivers/gpu/drm/i915/gvt/fb_decoder.c

Quoted 11 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +11 -0

+struct cursor_mode_format {
+	int	drm_format;	/* Pixel format in DRM definition */
+	u8	bpp;		/* Bits per pixel; 0 indicates invalid */
+	u32	width;		/* In pixel */
+	u32	height;		/* In lines */
+	char	*desc;		/* The description */
+};
+
+/* non-supported format has bpp default to 0 */ static struct
+cursor_mode_format cursor_pixel_formats[CURSOR_MODE_NUM] = {
+	[0x22]  = {DRM_FORMAT_ARGB8888, 32, 128, 128, "128x128 32bpp

ARGB"},

drivers/gpu/drm/i915/gvt/fb_decoder.c line 251

Quoted 1 line

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +1 -0

+	[0x23]  = {DRM_FORMAT_ARGB8888, 32, 256, 256, "256x256 32bpp

ARGB"},

Quoted 27 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +27 -0

+	[0x27]  = {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"},
+	[0x7]  = {DRM_FORMAT_ARGB8888, 32, 64, 64, "64x64 32bpp ARGB"}, };
+
+static int intel_vgpu_decode_cursor_plane_format(struct intel_vgpu *vgpu,
+	int pipe, struct intel_vgpu_cursor_plane_format *plane) {
+	u32 val, mode;
+	u32 alpha_plane, alpha_force;
+	struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+	val = vgpu_vreg(vgpu, CURCNTR(pipe));
+	mode = val & CURSOR_MODE;
+	plane->enabled = (mode != CURSOR_MODE_DISABLE);
+	if (!plane->enabled)
+		return 0;
+
+	if (!cursor_pixel_formats[mode].bpp) {
+		gvt_vgpu_err("Non-supported cursor mode (0x%x)\n", mode);
+		return -EINVAL;
+	}
+	plane->mode = mode;
+	plane->bpp = cursor_pixel_formats[mode].bpp;
+	plane->drm_format = cursor_pixel_formats[mode].drm_format;
+	plane->width = cursor_pixel_formats[mode].width;
+	plane->height = cursor_pixel_formats[mode].height;
+
+	alpha_plane = (val & _CURSOR_ALPHA_PLANE_MASK) >>
+				_CURSOR_ALPHA_PLANE_SHIFT;

drivers/gpu/drm/i915/gvt/fb_decoder.c

Quoted 10 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +10 -0

+	alpha_force = (val & _CURSOR_ALPHA_FORCE_MASK) >>
+				_CURSOR_ALPHA_FORCE_SHIFT;
+	if (alpha_plane || alpha_force)
+		gvt_dbg_core("alpha_plane=0x%x, alpha_force=0x%x\n",
+			alpha_plane, alpha_force);
+
+	plane->base = vgpu_vreg(vgpu, CURBASE(pipe)) & GTT_PAGE_MASK;
+
+	val = vgpu_vreg(vgpu, CURPOS(pipe));
+	plane->x_pos = (val & _CURSOR_POS_X_MASK) >>

_CURSOR_POS_X_SHIFT;

drivers/gpu/drm/i915/gvt/fb_decoder.c line 289

Quoted 1 line

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +1 -0

+	plane->x_sign = (val & _CURSOR_SIGN_X_MASK) >>

_CURSOR_SIGN_X_SHIFT;

drivers/gpu/drm/i915/gvt/fb_decoder.c line 290

Quoted 1 line

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +1 -0

+	plane->y_pos = (val & _CURSOR_POS_Y_MASK) >>

_CURSOR_POS_Y_SHIFT;

drivers/gpu/drm/i915/gvt/fb_decoder.c line 291

Quoted 1 line

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +1 -0

+	plane->y_sign = (val & _CURSOR_SIGN_Y_MASK) >>

_CURSOR_SIGN_Y_SHIFT;

drivers/gpu/drm/i915/gvt/fb_decoder.c line 288

Quoted 6 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +6 -0

+
+	return 0;
+}
+
+#define FORMAT_NUM_SRRITE	(1 << 3)
+

SPRITE_FORMAT_NUM

Quoted 38 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +38 -0

+static struct pixel_format sprite_pixel_formats[FORMAT_NUM_SRRITE] = {
+	[0x0]  = {DRM_FORMAT_YUV422, 16, "YUV 16-bit 4:2:2 packed"},
+	[0x1]  = {DRM_FORMAT_XRGB2101010, 32, "RGB 32-bit 2:10:10:10"},
+	[0x2]  = {DRM_FORMAT_XRGB8888, 32, "RGB 32-bit 8:8:8:8"},
+	[0x3]  = {DRM_FORMAT_XRGB161616_GVT, 64,
+		    "RGB 64-bit 16:16:16:16 Floating Point"},
+	[0x4] = {DRM_FORMAT_AYUV, 32,
+		"YUV 32-bit 4:4:4 packed (8:8:8:8 MSB-X:Y:U:V)"}, };
+
+static int intel_vgpu_decode_sprite_plane_format(struct intel_vgpu *vgpu,
+	int pipe, struct intel_vgpu_sprite_plane_format *plane) {
+	u32 val, fmt;
+	u32 width;
+	u32 color_order, yuv_order;
+	int drm_format;
+
+	val = vgpu_vreg(vgpu, SPRCTL(pipe));
+	plane->enabled = !!(val & SPRITE_ENABLE);
+	if (!plane->enabled)
+		return 0;
+
+	plane->tiled = !!(val & SPRITE_TILED);
+	color_order = !!(val & SPRITE_RGB_ORDER_RGBX);
+	yuv_order = (val & SPRITE_YUV_BYTE_ORDER_MASK) >>
+				_SPRITE_YUV_ORDER_SHIFT;
+
+	fmt = (val & SPRITE_PIXFORMAT_MASK) >> _SPRITE_FMT_SHIFT;
+	if (!sprite_pixel_formats[fmt].bpp) {
+		gvt_vgpu_err("Non-supported pixel format (0x%x)\n", fmt);
+		return -EINVAL;
+	}
+	plane->hw_format = fmt;
+	plane->bpp = sprite_pixel_formats[fmt].bpp;
+	drm_format = sprite_pixel_formats[fmt].drm_format;
+
+	/* Order of RGB values in an RGBxxx buffer may be ordered RGB or
+	 * BGR depending on the state of the color_order field
+	 */

drivers/gpu/drm/i915/gvt/fb_decoder.c line 338

Quoted 10 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +10 -0

+	if (!color_order) {
+		if (drm_format == DRM_FORMAT_XRGB2101010)
+			drm_format = DRM_FORMAT_XBGR2101010;
+		else if (drm_format == DRM_FORMAT_XRGB8888)
+			drm_format = DRM_FORMAT_XBGR8888;
+	}
+
+	if (drm_format == DRM_FORMAT_YUV422) {
+		switch (yuv_order) {
+		case	0:

no extra space

Quoted 18 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +18 -0

+			drm_format = DRM_FORMAT_YUYV;
+			break;
+		case	1:
+			drm_format = DRM_FORMAT_UYVY;
+			break;
+		case	2:
+			drm_format = DRM_FORMAT_YVYU;
+			break;
+		case	3:
+			drm_format = DRM_FORMAT_VYUY;
+			break;
+		default:
+			/* yuv_order has only 2 bits */
+			break;
+		}
+	}
+
+	plane->drm_format = drm_format;

drivers/gpu/drm/i915/gvt/fb_decoder.c

Quoted 10 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +10 -0

+
+	plane->base = vgpu_vreg(vgpu, SPRSURF(pipe)) & GTT_PAGE_MASK;
+	plane->width = vgpu_vreg(vgpu, SPRSTRIDE(pipe)) &
+				_SPRITE_STRIDE_MASK;
+	plane->width /= plane->bpp / 8;	/* raw width in bytes */
+
+	val = vgpu_vreg(vgpu, SPRSIZE(pipe));
+	plane->height = (val & _SPRITE_SIZE_HEIGHT_MASK) >>
+		_SPRITE_SIZE_HEIGHT_SHIFT;
+	width = (val & _SPRITE_SIZE_WIDTH_MASK) >>

_SPRITE_SIZE_WIDTH_SHIFT;

drivers/gpu/drm/i915/gvt/fb_decoder.c line 371

Quoted 5 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +5 -0

+	plane->height += 1;	/* raw height is one minus the real value */
+	width += 1;		/* raw width is one minus the real value */
+	if (plane->width != width)
+		gvt_dbg_core("sprite_plane: plane->width=%d, width=%d\n",
+			plane->width, width);

should report error?

Quoted 59 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +58 -0

+static int intel_vgpu_decode_fb_format(struct intel_gvt *gvt, int id,
+	struct intel_vgpu_fb_format *fb)
+{
+	int i;
+	struct intel_vgpu *vgpu = NULL;
+	int ret = 0;
+	struct drm_i915_private *dev_priv = gvt->dev_priv;
+
+	if (!fb)
+		return -EINVAL;
+
+	/* TODO: use fine-grained refcnt later */
+	mutex_lock(&gvt->lock);
+
+	for_each_active_vgpu(gvt, vgpu, i)
+		if (vgpu->id == id)
+			break;
+
+	if (!vgpu) {
+		gvt_vgpu_err("Invalid vgpu ID (%d)\n", id);
+		mutex_unlock(&gvt->lock);
+		return -ENODEV;
+	}
+
+	for (i = 0; i < I915_MAX_PIPES; i++) {
+		struct intel_vgpu_pipe_format *pipe = &fb->pipes[i];
+		u32 ddi_func_ctl = vgpu_vreg(vgpu, TRANS_DDI_FUNC_CTL(i));
+
+		if (!(ddi_func_ctl & TRANS_DDI_FUNC_ENABLE)) {
+			pipe->ddi_port = DDI_PORT_NONE;
+		} else {
+			u32 port = (ddi_func_ctl & TRANS_DDI_PORT_MASK) >>
+						TRANS_DDI_PORT_SHIFT;
+			if (port <= DDI_PORT_E)
+				pipe->ddi_port = port;
+			else
+				pipe->ddi_port = DDI_PORT_NONE;
+		}
+
+		ret |= intel_vgpu_decode_primary_plane_format(vgpu,
+			i, &pipe->primary);
+		ret |= intel_vgpu_decode_sprite_plane_format(vgpu,
+			i, &pipe->sprite);
+		ret |= intel_vgpu_decode_cursor_plane_format(vgpu,
+			i, &pipe->cursor);
+
+		if (ret) {
+			gvt_vgpu_err("Decode format error for pipe(%d)\n", i);
+			ret = -EINVAL;
+			break;
+		}
+	}
+
+	mutex_unlock(&gvt->lock);
+
+	return ret;
+}
+

drivers/gpu/drm/i915/gvt/fb_decoder.c

Quoted 10 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +10 -0

+/**
+ * intel_vgpu_decode_plane - Decode plane based on plane id
+ * @dev: drm device
+ * @vgpu: input vgpu
+ * This function is called for decoding plane
+ *
+ * Returns:
+ * pipe on success, NULL if failed.
+ */
+struct intel_vgpu_pipe_format *intel_vgpu_decode_plane(struct drm_device

*dev,

Quoted 12 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +12 -0

+		struct intel_vgpu *vgpu)
+{
+	struct drm_i915_private *dev_priv = dev->dev_private;
+	struct intel_vgpu_fb_format fb;
+	struct intel_vgpu_pipe_format *pipe;
+	int i;
+
+	if (intel_vgpu_decode_fb_format(dev_priv->gvt, vgpu->id, &fb))
+		return NULL;
+
+	for (i = 0; i < I915_MAX_PIPES; i++)
+		if (pipe_is_enabled(vgpu, i))

drivers/gpu/drm/i915/gvt/fb_decoder.c line 469

Quoted 5 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +5 -0

+			break;
+	if (i >= I915_MAX_PIPES) {
+		gvt_dbg_core("No enabled pipes\n");
+		return NULL;
+	}

Looks this check should be moved in above decode_fb_format function which doesn't check if pipe is actually enabled.

drivers/gpu/drm/i915/gvt/fb_decoder.c line 475

Quoted 7 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +6 -0

+	pipe = &fb.pipes[i];
+
+	if (!pipe || !pipe->primary.enabled) {
+		gvt_dbg_core("Invalid pipe_id :%d\n", i);
+		return NULL;
+	}

And this function is to find primary plane actually? Should name it like intel_vgpu_decode_primary_plane().

Quoted 12 lines

drivers/gpu/drm/i915/gvt/fb_decoder.c new file +4 -0

+
+	return pipe;
+}
+

drivers/gpu/drm/i915/gvt/fb_decoder.h new file +1 -0

new file mode 100644
index 0000000..04300af
+

drivers/gpu/drm/i915/gvt/fb_decoder.h line 161

Quoted 10 lines

drivers/gpu/drm/i915/gvt/fb_decoder.h new file +10 -0

+struct intel_vgpu_pipe_format {
+	struct intel_vgpu_primary_plane_format	primary;
+	struct intel_vgpu_sprite_plane_format	sprite;
+	struct intel_vgpu_cursor_plane_format	cursor;
+	enum DDI_PORT ddi_port;  /* the DDI port that pipe is connected to
+*/ };
+
+struct intel_vgpu_fb_format {
+	struct intel_vgpu_pipe_format	pipes[4];
+};

Should use MAX_PIPE definition.

--
Open Source Technology Center, Intel ltd.

$gpg --keyserver wwwkeys.pgp.net --recv-keys 4D781827

-----Original Message-----
From: Gerd Hoffmann [mailto:[email protected]]
Sent: Monday, May 29, 2017 3:20 PM
To: Chen, Xiaoguang <[email protected]>; [email protected]; [email protected]; intel- [email protected]; [email protected]; [email protected]; Lv, Zhiyuan <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Tian, Kevin <[email protected]>
Subject: Re: [PATCH v6 4/6] vfio: Define vfio based vgpu's dma-buf operations

include/uapi/linux/vfio.h struct vfio_pci_hot_reset { · line 552

Quoted 7 lines

include/uapi/linux/vfio.h +7 -0

+struct vfio_vgpu_dmabuf_info {
+	__u32 argsz;
+	__u32 flags;
+	struct vfio_vgpu_plane_info plane_info;
+	__s32 fd;
+	__u32 pad;
+};

Hmm, now you have argsz and flags twice in vfio_vgpu_dmabuf_info ...

I think we should have something like this:

struct vfio_vgpu_plane_info {
        __u64 start;
        __u64 drm_format_mod;
        __u32 drm_format;
        __u32 width;
        __u32 height;
        __u32 stride;
        __u32 size;
        __u32 x_pos;

        __u32 y_pos;
       __u32 padding;
};

struct vfio_vgpu_query_plane {
	__u32 argsz;
	__u32 flags;
	struct vfio_vgpu_plane_info plane_info;
       __u32 plane_id;
       __u32 padding;
};

struct vfio_vgpu_create_dmabuf {
	__u32 argsz;
	__u32 flags;
	struct vfio_vgpu_plane_info plane_info;
       __u32 plane_id;
       __s32 fd;
};

Hi,

Quoted 44 lines

-----Original Message-----
From: Gerd Hoffmann [mailto:[email protected]]
Sent: Monday, May 29, 2017 3:20 PM
To: Chen, Xiaoguang <[email protected]>; [email protected]; [email protected]; intel- [email protected]; [email protected]; [email protected]; Lv, Zhiyuan <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Tian, Kevin <[email protected]>
Subject: Re: [PATCH v6 4/6] vfio: Define vfio based vgpu's dma-buf operations

include/uapi/linux/vfio.h struct vfio_pci_hot_reset { · line 552

Quoted 7 lines

include/uapi/linux/vfio.h +7 -0

+struct vfio_vgpu_dmabuf_info {
+	__u32 argsz;
+	__u32 flags;
+	struct vfio_vgpu_plane_info plane_info;
+	__s32 fd;
+	__u32 pad;
+};

Hmm, now you have argsz and flags twice in vfio_vgpu_dmabuf_info ...

I think we should have something like this:

struct vfio_vgpu_plane_info {
        __u64 start;
        __u64 drm_format_mod;
        __u32 drm_format;
        __u32 width;
        __u32 height;
        __u32 stride;
        __u32 size;
        __u32 x_pos;
        __u32 y_pos;
       __u32 padding;
};

struct vfio_vgpu_query_plane {
	__u32 argsz;
	__u32 flags;
	struct vfio_vgpu_plane_info plane_info;
       __u32 plane_id;
       __u32 padding;
};

Quoted 7 lines

struct vfio_vgpu_create_dmabuf {
	__u32 argsz;
	__u32 flags;
	struct vfio_vgpu_plane_info plane_info;
       __u32 plane_id;
       __s32 fd;
};

Good suggestion will apply in the next version.
Thanks for review :)

Chenxg.

-----Original Message-----
From: Kirti Wankhede [mailto:[email protected]]
Sent: Thursday, June 01, 2017 1:23 AM
To: Chen, Xiaoguang <[email protected]>; Gerd Hoffmann <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Lv, Zhiyuan <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Tian, Kevin <[email protected]>
Subject: Re: [PATCH v6 4/6] vfio: Define vfio based vgpu's dma-buf operations

Quoted 54 lines · Xiaoguang

Hi,

Quoted 52 lines

-----Original Message-----
From: Gerd Hoffmann [mailto:[email protected]]
Sent: Monday, May 29, 2017 3:20 PM
To: Chen, Xiaoguang <[email protected]>; [email protected]; [email protected]; intel- [email protected]; [email protected]; [email protected]; Lv, Zhiyuan <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Tian, Kevin <[email protected]>
Subject: Re: [PATCH v6 4/6] vfio: Define vfio based vgpu's dma-buf operations

include/uapi/linux/vfio.h struct vfio_pci_hot_reset { · line 552

Quoted 7 lines

include/uapi/linux/vfio.h +7 -0

+struct vfio_vgpu_dmabuf_info {
+	__u32 argsz;
+	__u32 flags;
+	struct vfio_vgpu_plane_info plane_info;
+	__s32 fd;
+	__u32 pad;
+};

Hmm, now you have argsz and flags twice in vfio_vgpu_dmabuf_info ...

I think we should have something like this:

struct vfio_vgpu_plane_info {
        __u64 start;
        __u64 drm_format_mod;
        __u32 drm_format;
        __u32 width;
        __u32 height;
        __u32 stride;
        __u32 size;
        __u32 x_pos;
        __u32 y_pos;
       __u32 padding;
};

struct vfio_vgpu_query_plane {
	__u32 argsz;
	__u32 flags;
	struct vfio_vgpu_plane_info plane_info;
       __u32 plane_id;
       __u32 padding;
};

struct vfio_vgpu_create_dmabuf {
	__u32 argsz;
	__u32 flags;
	struct vfio_vgpu_plane_info plane_info;
       __u32 plane_id;
       __s32 fd;
};

Quoted 3 lines

Good suggestion will apply in the next version.
Thanks for review :)

Can you define what are the expected values of 'flags' would be?

Thanks,
Kirti

Quoted 2 lines

Chenxg.

Hi Kirti,

Quoted 68 lines

-----Original Message-----
From: Kirti Wankhede [mailto:[email protected]]
Sent: Thursday, June 01, 2017 1:23 AM
To: Chen, Xiaoguang <[email protected]>; Gerd Hoffmann <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Lv, Zhiyuan <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Tian, Kevin <[email protected]>
Subject: Re: [PATCH v6 4/6] vfio: Define vfio based vgpu's dma-buf operations

Quoted 54 lines · Xiaoguang

Hi,

Quoted 52 lines

-----Original Message-----
From: Gerd Hoffmann [mailto:[email protected]]
Sent: Monday, May 29, 2017 3:20 PM
To: Chen, Xiaoguang <[email protected]>; [email protected]; [email protected]; intel- [email protected]; [email protected]; [email protected]; Lv, Zhiyuan <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Tian, Kevin <[email protected]>
Subject: Re: [PATCH v6 4/6] vfio: Define vfio based vgpu's dma-buf operations

include/uapi/linux/vfio.h struct vfio_pci_hot_reset { · line 552

Quoted 7 lines

include/uapi/linux/vfio.h +7 -0

+struct vfio_vgpu_dmabuf_info {
+	__u32 argsz;
+	__u32 flags;
+	struct vfio_vgpu_plane_info plane_info;
+	__s32 fd;
+	__u32 pad;
+};  

Hmm, now you have argsz and flags twice in vfio_vgpu_dmabuf_info ...

I think we should have something like this:

struct vfio_vgpu_plane_info {
        __u64 start;
        __u64 drm_format_mod;
        __u32 drm_format;
        __u32 width;
        __u32 height;
        __u32 stride;
        __u32 size;
        __u32 x_pos;
        __u32 y_pos;
       __u32 padding;
};

struct vfio_vgpu_query_plane {
	__u32 argsz;
	__u32 flags;
	struct vfio_vgpu_plane_info plane_info;
       __u32 plane_id;
       __u32 padding;
};

struct vfio_vgpu_create_dmabuf {
	__u32 argsz;
	__u32 flags;
	struct vfio_vgpu_plane_info plane_info;
       __u32 plane_id;
       __s32 fd;
};  

Quoted 5 lines

Quoted 3 lines

Good suggestion will apply in the next version.
Thanks for review :)

Can you define what are the expected values of 'flags' would be?

Flags is not used in this case. It is defined to follow the rules of vfio ioctls.

Quoted 75 lines · Xiaoguang

Hi Kirti,

Quoted 73 lines

-----Original Message-----
From: Kirti Wankhede [mailto:[email protected]]
Sent: Thursday, June 01, 2017 1:23 AM
To: Chen, Xiaoguang <[email protected]>; Gerd Hoffmann <[email protected]>; [email protected]; [email protected]; [email protected]; [email protected]; [email protected]; Lv, Zhiyuan <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Tian, Kevin <[email protected]>
Subject: Re: [PATCH v6 4/6] vfio: Define vfio based vgpu's dma-buf operations

Quoted 54 lines · Xiaoguang

Hi,

Quoted 45 lines

-----Original Message-----
From: Gerd Hoffmann [mailto:[email protected]]
Sent: Monday, May 29, 2017 3:20 PM
To: Chen, Xiaoguang <[email protected]>; [email protected]; [email protected]; intel- [email protected]; [email protected]; [email protected]; Lv, Zhiyuan <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Tian, Kevin <[email protected]>
Subject: Re: [PATCH v6 4/6] vfio: Define vfio based vgpu's dma-buf operations

include/uapi/linux/vfio.h struct vfio_pci_hot_reset { · line 552

Quoted 7 lines

include/uapi/linux/vfio.h +7 -0

+struct vfio_vgpu_dmabuf_info {
+	__u32 argsz;
+	__u32 flags;
+	struct vfio_vgpu_plane_info plane_info;
+	__s32 fd;
+	__u32 pad;
+};  

Hmm, now you have argsz and flags twice in vfio_vgpu_dmabuf_info ...

I think we should have something like this:

struct vfio_vgpu_plane_info {
        __u64 start;
        __u64 drm_format_mod;
        __u32 drm_format;
        __u32 width;
        __u32 height;
        __u32 stride;
        __u32 size;
        __u32 x_pos;
        __u32 y_pos;
       __u32 padding;
};

struct vfio_vgpu_query_plane {
	__u32 argsz;
	__u32 flags;
	struct vfio_vgpu_plane_info plane_info;
       __u32 plane_id;
       __u32 padding;
};

Quoted 7 lines

struct vfio_vgpu_create_dmabuf {
	__u32 argsz;
	__u32 flags;
	struct vfio_vgpu_plane_info plane_info;
       __u32 plane_id;
       __s32 fd;
};  

Quoted 3 lines

Good suggestion will apply in the next version.
Thanks for review :)

Can you define what are the expected values of 'flags' would be?

Quoted 1 line

Flags is not used in this case. It is defined to follow the rules of vfio ioctls.

An important note about flags, the vendor driver must validate it. If they don't and the user passes an arbitrary value there, then we have a backwards compatibility issue with ever attempting to use the flags field. The user passing in a flag unknown to the vendor driver should return an -EINVAL response. In this case, we haven't defined any flags, so the vendor driver needs to force the user to pass zero.

struct vfio_vgpu_surface_info {
        __u64 start;
        __u32 width;
        __u32 height;
        __u32 stride;
        __u32 size;
        __u32 x_pos;
        __u32 y_pos;
        __u32 padding;
        /* Only used when VFIO_VGPU_SURFACE_DMABUF_* flags set */ __u64 drm_format_mod;
        __u32 drm_format;

Quoted 13 lines

struct vfio_vgpu_surface_info {
        __u64 start;
        __u32 width;
        __u32 height;
        __u32 stride;
        __u32 size;
        __u32 x_pos;
        __u32 y_pos;
        __u32 padding;
        /* Only used when VFIO_VGPU_SURFACE_DMABUF_* flags set */
        __u64 drm_format_mod;
        __u32 drm_format;

Why for dmabufs only? Shouldn't the region specify the format too? Even in case you are using a fixed one (say DRM_FORMAT_XRGB8888) you can explicitly say so in drm_format (and set drm_format_mod to zero).

cheers,
Gerd

Quoted 14 lines · Gerd Hoffmann

Quoted 13 lines

struct vfio_vgpu_surface_info {
        __u64 start;
        __u32 width;
        __u32 height;
        __u32 stride;
        __u32 size;
        __u32 x_pos;
        __u32 y_pos;
        __u32 padding;
        /* Only used when VFIO_VGPU_SURFACE_DMABUF_* flags set */ __u64 drm_format_mod;
        __u32 drm_format;

Quoted 7 lines

Why for dmabufs only?  Shouldn't the region specify the format too?
Even in case you are using a fixed one (say DRM_FORMAT_XRGB8888) you
can explicitly say so in drm_format (and set drm_format_mod to zero).

Definitions for PIXMAN formats and DRM formats are different. I think we need a flag to specify the format of surface that vendor driver is going to provide, PIXMAN or DRM.

If surface is provided through region in PIXMAN format, existing functions in QEMU can be used to get format from bpp value, qemu_default_pixman_format(). Similarly, display surface can be updated
by QEMU using qemu_create_displaysurface_from() from mmaped region.

+       if (plane_id == PLANE_PRIMARY) {

-----Original Message-----
From: intel-gvt-dev [mailto:[email protected]] On Behalf Of Gerd Hoffmann
Sent: Wednesday, May 31, 2017 8:05 PM
To: Chen, Xiaoguang <[email protected]>; [email protected]; [email protected]; intel- [email protected]; [email protected]; [email protected]; Lv, Zhiyuan <[email protected]>; intel-gvt- [email protected]; Wang, Zhi A <[email protected]>; Tian, Kevin <[email protected]>
Subject: Re: [PATCH v6 5/6] drm/i915/gvt: Dmabuf support for GVT-g

Quoted 1 line · Xiaoguang Chen

+       if (plane_id == PLANE_PRIMARY) {

Should be DRM_PLANE_TYPE_PRIMARY (likewise for the cursor).

_______________________________________________
intel-gvt-dev mailing list
[email protected]
https://lists.freedesktop.org/mailman/listinfo/intel-gvt-dev

dmabuf for GVT-g can be exported to users who can use the dmabuf to show the desktop of vm which use intel vgpu.

Currently we provide query and create new dmabuf operations.

Users of dmabuf can cache some created dmabufs and related information such as the framebuffer's address, size, tiling mode, width, height etc. When refresh the screen first query the currnet vgpu's frambuffer and compare with the cached ones(address, size, tiling, width, height etc) if found one then reuse the found dmabuf to gain performance improvment.

If there is no dmabuf created yet or not found in the cached dmabufs then need to create a new dmabuf. To create a dmabuf first a gem object will be created and the backing storage of this gem object is the vgpu's framebuffer(primary/cursor).
Set caching mode, change tiling mode and set domains of this gem object is not supported.
Then associate this gem object to a dmabuf and export this dmabuf. A file descriptor will be generated for this dmabuf and this file descriptor can be sent to user space to do display.

Signed-off-by Xiaoguang Chen <[email protected]>

---
 drivers/gpu/drm/i915/gvt/Makefile      |   2 +-
 drivers/gpu/drm/i915/gvt/dmabuf.c      | 269 +++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/dmabuf.h      |  37 +++++
 drivers/gpu/drm/i915/gvt/gvt.h         |   1 +
 drivers/gpu/drm/i915/i915_gem.c        |  26 +++-
 drivers/gpu/drm/i915/i915_gem_object.h |   9 ++
 6 files changed, 342 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.c
 create mode 100644 drivers/gpu/drm/i915/gvt/dmabuf.h

drivers/gpu/drm/i915/gvt/Makefile +1 -1

index 192ca26..e480f7d 100644
@@ -2,7 +2,7 @@ GVT_DIR := gvt
 GVT_SOURCE := gvt.o aperture_gm.o handlers.o vgpu.o trace_points.o firmware.o \
 	interrupt.o gtt.o cfg_space.o opregion.o mmio.o display.o edid.o \
 	execlist.o scheduler.o sched_policy.o render.o cmd_parser.o \
-	fb_decoder.o
+	fb_decoder.o dmabuf.o
 
 ccflags-y				+= -I$(src) -I$(src)/$(GVT_DIR) -Wall
 i915-y					+= $(addprefix $(GVT_DIR)/, $(GVT_SOURCE))

drivers/gpu/drm/i915/gvt/dmabuf.c new file +46 -0

new file mode 100644
index 0000000..c831e91
@@ -0,0 +1,269 @@
+/*
+ * Copyright 2017 Intel Corporation. All rights reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice (including the next
+ * paragraph) shall be included in all copies or substantial portions of the
+ * Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
+ * DEALINGS IN THE SOFTWARE.
+ *
+ * Authors:
+ *    Zhiyuan Lv <[email protected]>
+ *
+ * Contributors:
+ *    Xiaoguang Chen <[email protected]>
+ */
+
+#include <linux/dma-buf.h>
+#include <drm/drmP.h>
+#include <linux/vfio.h>
+
+#include "i915_drv.h"
+#include "gvt.h"
+
+#define GEN8_DECODE_PTE(pte) (pte & GENMASK_ULL(63, 12))
+
+static struct sg_table *intel_vgpu_gem_get_pages(
+		struct drm_i915_gem_object *obj)
+{
+	struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
+	struct sg_table *st;
+	struct scatterlist *sg;
+	int i, ret;
+	gen8_pte_t __iomem *gtt_entries;

drivers/gpu/drm/i915/gvt/dmabuf.c new file +45 -0

+	}
+
+	ret = sg_alloc_table(st, fb_info->fb_size, GFP_KERNEL);
+	if (ret) {
+		kfree(st);
+		return ERR_PTR(ret);
+	}
+	gtt_entries = (gen8_pte_t __iomem *)dev_priv->ggtt.gsm +
+		(fb_info->fb_addr >> PAGE_SHIFT);
+	for_each_sg(st->sgl, sg, fb_info->fb_size, i) {
+		sg->offset = 0;
+		sg->length = PAGE_SIZE;
+		sg_dma_address(sg) =
+			GEN8_DECODE_PTE(readq(&gtt_entries[i]));
+		sg_dma_len(sg) = PAGE_SIZE;
+	}
+
+	return st;
+}
+
+static void intel_vgpu_gem_put_pages(struct drm_i915_gem_object *obj,
+		struct sg_table *pages)
+{
+	sg_free_table(pages);
+	kfree(pages);
+}
+
+static const struct drm_i915_gem_object_ops intel_vgpu_gem_ops = {
+	.flags = I915_GEM_OBJECT_IS_PROXY,
+	.get_pages = intel_vgpu_gem_get_pages,
+	.put_pages = intel_vgpu_gem_put_pages,
+};
+
+static struct drm_i915_gem_object *intel_vgpu_create_gem(struct drm_device *dev,
+		struct vfio_vgpu_plane_info *info)
+{
+	struct drm_i915_private *dev_priv = to_i915(dev);
+	struct drm_i915_gem_object *obj;
+
+	obj = i915_gem_object_alloc(dev_priv);
+	if (obj == NULL)
+		return NULL;
+
+	drm_gem_private_object_init(dev, &obj->base,
+		info->size << PAGE_SHIFT);

drivers/gpu/drm/i915/gvt/dmabuf.c new file +61 -0

+	if (IS_SKYLAKE(dev_priv)) {
+		unsigned int tiling_mode = 0;
+		unsigned int stride = 0;
+
+		switch (info->drm_format_mod << 10) {
+		case PLANE_CTL_TILED_LINEAR:
+			tiling_mode = I915_TILING_NONE;
+			break;
+		case PLANE_CTL_TILED_X:
+			tiling_mode = I915_TILING_X;
+			stride = info->stride;
+			break;
+		case PLANE_CTL_TILED_Y:
+			tiling_mode = I915_TILING_Y;
+			stride = info->stride;
+			break;
+		default:
+			gvt_dbg_core("not supported tiling mode\n");
+		}
+		obj->tiling_and_stride = tiling_mode | stride;
+	} else {
+		obj->tiling_and_stride = info->drm_format_mod ?
+					I915_TILING_X : 0;
+	}
+
+	return obj;
+}
 
+
+int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args)
+{
+	struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
+	struct vfio_vgpu_plane_info *info = args;
+
+	return intel_vgpu_get_plane_info(dev, vgpu, info);
+}
+
+int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args)
+{
+	struct dma_buf *dmabuf;
+	struct drm_i915_gem_object *obj;
+	struct drm_device *dev = &vgpu->gvt->dev_priv->drm;
+	struct vfio_vgpu_dmabuf_info *gvt_dmabuf = args;
+	struct intel_vgpu_fb_info *fb_info;
+	int ret;
+
+	ret = intel_vgpu_get_plane_info(dev, vgpu, &gvt_dmabuf->plane_info);
+	if (ret != 0)
+		return ret;
+
+	obj = intel_vgpu_create_gem(dev, &gvt_dmabuf->plane_info);
+	if (obj == NULL) {
+		gvt_vgpu_err("create gvt gem obj failed:%d\n", vgpu->id);
+		return -ENOMEM;
+	}
+	fb_info = kmalloc(sizeof(*fb_info), GFP_KERNEL);
+	if (!fb_info) {
+		i915_gem_object_put(obj);
+		gvt_vgpu_err("allocate intel vgpu fb info failed\n");
+		return -ENOMEM;
+	}
+	fb_info->fb_addr = gvt_dmabuf->plane_info.start;

drivers/gpu/drm/i915/gvt/dmabuf.c new file +14 -0

+		return PTR_ERR(dmabuf);
+	}
+
+	ret = dma_buf_fd(dmabuf, DRM_CLOEXEC | DRM_RDWR);
+	if (ret < 0) {
+		kfree(fb_info);
+		i915_gem_object_free(obj);
+		gvt_vgpu_err("create dma-buf fd failed ret:%d\n", ret);
+		return ret;
+	}
+	gvt_dmabuf->fd = ret;
+
+	return 0;
+}

drivers/gpu/drm/i915/i915_gem.c +0 -0

index 0c1cbe9..14be3b0 100644

drivers/gpu/drm/i915/i915_gem.c +9 -1

+	}
+
 	/* Try to flush the object off the GPU without holding the lock.
 	 * We will repeat the flush holding the lock in the normal manner
 	 * to catch cases where we are gazumped.

@@ -1677,6 +1683,12 @@ i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data,
 	if (!obj)
 		return -ENOENT;
 
+	/* proxy gem obj does not support this operation */
+	if (i915_gem_object_is_proxy(obj)) {
+		i915_gem_object_put(obj);
+		return -EPERM;
+	}
+
 	/* Pinned buffers may be scanout, so flush the cache */
 	i915_gem_object_flush_if_display(obj);
 	i915_gem_object_put(obj);

@@ -1727,7 +1739,7 @@ i915_gem_mmap_ioctl(struct drm_device *dev, void *data,
 	 */
 	if (!obj->base.filp) {
 		i915_gem_object_put(obj);
-		return -EINVAL;
+		return -EPERM;
 	}
 
 	addr = vm_mmap(obj->base.filp, 0, args->size,

drivers/gpu/drm/i915/i915_gem.c +3 -0

+		return -EPERM;
+	}
+
 	err = mutex_lock_interruptible(&obj->mm.lock);
 	if (err)
 		goto out;

User space should create the management fd for the dma-buf operation first. Then user can query the plane information and create dma-buf if necessary using the management fd.

Signed-off-by Xiaoguang Chen <[email protected]>

---
 drivers/gpu/drm/i915/gvt/dmabuf.c |  12 ++++
 drivers/gpu/drm/i915/gvt/dmabuf.h |   5 ++
 drivers/gpu/drm/i915/gvt/gvt.c    |   2 +
 drivers/gpu/drm/i915/gvt/gvt.h    |   5 ++
 drivers/gpu/drm/i915/gvt/kvmgt.c  | 144 ++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/gvt/vgpu.c   |   1 +
 6 files changed, 169 insertions(+)

drivers/gpu/drm/i915/gvt/dmabuf.c +12 -0

index c831e91..9759e9a 100644
@@ -226,6 +226,7 @@ int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args)
 	struct vfio_vgpu_dmabuf_info *gvt_dmabuf = args;
 	struct intel_vgpu_fb_info *fb_info;
 	int ret;
+	struct intel_vgpu_dmabuf_obj *dmabuf_obj;
 
 	ret = intel_vgpu_get_plane_info(dev, vgpu, &gvt_dmabuf->plane_info);
 	if (ret != 0)

@@ -263,6 +264,17 @@ int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args)
 		gvt_vgpu_err("create dma-buf fd failed ret:%d\n", ret);
 		return ret;
 	}
+	dmabuf_obj = kmalloc(sizeof(*dmabuf_obj), GFP_KERNEL);
+	if (dmabuf_obj == NULL) {
+		kfree(fb_info);
+		i915_gem_object_put(obj);
+		gvt_vgpu_err("alloc dmabuf_obj failed\n");
+		return -ENOMEM;
+	}
+	dmabuf_obj->obj = obj;
+	INIT_LIST_HEAD(&dmabuf_obj->list);
+	list_add_tail(&dmabuf_obj->list, &vgpu->dmabuf_obj_list_head);
+
 	gvt_dmabuf->fd = ret;
 
 	return 0;

drivers/gpu/drm/i915/gvt/dmabuf.h +5 -0

index 8be9979..cafa781 100644
@@ -31,6 +31,11 @@ struct intel_vgpu_fb_info {
 	uint32_t fb_size;
 };
 
+struct intel_vgpu_dmabuf_obj {
+	struct drm_i915_gem_object *obj;
+	struct list_head list;
+};
+
 int intel_vgpu_query_plane(struct intel_vgpu *vgpu, void *args);
 int intel_vgpu_create_dmabuf(struct intel_vgpu *vgpu, void *args);
 

drivers/gpu/drm/i915/gvt/gvt.c +2 -0

index 2032917..dbc3f86 100644
@@ -54,6 +54,8 @@ static const struct intel_gvt_ops intel_gvt_ops = {
 	.vgpu_reset = intel_gvt_reset_vgpu,
 	.vgpu_activate = intel_gvt_activate_vgpu,
 	.vgpu_deactivate = intel_gvt_deactivate_vgpu,
+	.vgpu_query_plane = intel_vgpu_query_plane,
+	.vgpu_create_dmabuf = intel_vgpu_create_dmabuf,
 };
 
 /**

drivers/gpu/drm/i915/gvt/gvt.h +5 -0

index 763a8c5..a855797 100644
@@ -185,8 +185,11 @@ struct intel_vgpu {
 		struct kvm *kvm;
 		struct work_struct release_work;
 		atomic_t released;
+		struct vfio_device *vfio_device;
 	} vdev;
 #endif
+	int dmabuf_mgr_fd;
+	struct list_head dmabuf_obj_list_head;
 };
 
 struct intel_gvt_gm {

@@ -467,6 +470,8 @@ struct intel_gvt_ops {
 	void (*vgpu_reset)(struct intel_vgpu *);
 	void (*vgpu_activate)(struct intel_vgpu *);
 	void (*vgpu_deactivate)(struct intel_vgpu *);
+	int (*vgpu_query_plane)(struct intel_vgpu *vgpu, void *);
+	int (*vgpu_create_dmabuf)(struct intel_vgpu *vgpu, void *);
 };
 
 

drivers/gpu/drm/i915/gvt/kvmgt.c +32 -0

index 389f072..a079080 100644
@@ -41,6 +41,7 @@
 #include <linux/kvm_host.h>
 #include <linux/vfio.h>
 #include <linux/mdev.h>
+#include <linux/anon_inodes.h>
 
 #include "i915_drv.h"
 #include "gvt.h"

@@ -524,6 +525,125 @@ static int intel_vgpu_reg_init_opregion(struct intel_vgpu *vgpu)
 	return ret;
 }
 
+static int kvmgt_get_vfio_device(struct intel_vgpu *vgpu)
+{
+	struct vfio_device *device;
+
+	device = vfio_device_get_from_dev(mdev_dev(vgpu->vdev.mdev));
+	if (device == NULL)
+		return -ENODEV;
+	vgpu->vdev.vfio_device = device;
+
+	return 0;
+}
+
+static void kvmgt_put_vfio_device(struct intel_vgpu *vgpu)
+{
+	vfio_device_put(vgpu->vdev.vfio_device);
+}
+
+static int intel_vgpu_dmabuf_mgr_fd_mmap(struct file *file,
+		struct vm_area_struct *vma)
+{
+	return -EPERM;
+}
+
+static int intel_vgpu_dmabuf_mgr_fd_release(struct inode *inode,
+		struct file *filp)
+{
+	struct intel_vgpu *vgpu = filp->private_data;
+	struct intel_vgpu_dmabuf_obj *obj;
+	struct list_head *pos;
+
+	if (WARN_ON(!vgpu->vdev.vfio_device))

drivers/gpu/drm/i915/gvt/kvmgt.c +44 -0

+	}
+	kvmgt_put_vfio_device(vgpu);
+
+	return 0;
+}
+
+static long intel_vgpu_dmabuf_mgr_fd_ioctl(struct file *filp,
+		unsigned int ioctl, unsigned long arg)
+{
+	struct intel_vgpu *vgpu = filp->private_data;
+	int minsz;
+	int ret;
+	struct fd f;
+
+	f = fdget(vgpu->dmabuf_mgr_fd);
+	if (!f.file)
+		return -EBADF;
+
+	if (ioctl == VFIO_DEVICE_QUERY_PLANE) {
+		struct vfio_vgpu_plane_info info;
+
+		minsz = offsetofend(struct vfio_vgpu_plane_info, resv);
+		if (copy_from_user(&info, (void __user *)arg, minsz)) {
+			fdput(f);
+			return -EFAULT;
+		}
+		if (info.argsz < minsz) {
+			fdput(f);
+			return -EINVAL;
+		}
+		ret = intel_gvt_ops->vgpu_query_plane(vgpu, &info);
+		if (ret != 0) {
+			fdput(f);
+			gvt_vgpu_err("query plane failed:%d\n", ret);
+			return -EINVAL;
+		}
+		fdput(f);
+		return copy_to_user((void __user *)arg, &info, minsz) ?
+								-EFAULT : 0;
+	} else if (ioctl == VFIO_DEVICE_CREATE_DMABUF) {
+		struct vfio_vgpu_dmabuf_info dmabuf;
+
+		minsz = offsetofend(struct vfio_vgpu_dmabuf_info, resv);
+		if (copy_from_user(&dmabuf, (void __user *)arg, minsz)) {