Add Intel Arria 10 SoC FPGA driver

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
CONFIG_FPGA
CONFIG_FPGA_ALTERA
CONFIG_FPGA_SOCFPGA

Signed-off-by Tien Fong Chee <[email protected]>

---
 configs/astro_mcf5373l_defconfig       | 1 +
 configs/socfpga_arria5_defconfig       | 1 +
 configs/socfpga_cyclone5_defconfig     | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig    | 1 +
 configs/socfpga_de1_soc_defconfig      | 1 +
 configs/socfpga_is1_defconfig          | 1 +
 configs/socfpga_mcvevk_defconfig       | 1 +
 configs/socfpga_sockit_defconfig       | 1 +
 configs/socfpga_socrates_defconfig     | 1 +
 configs/socfpga_sr1500_defconfig       | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +
 configs/theadorable_debug_defconfig    | 1 +
 configs/theadorable_defconfig          | 1 +
 drivers/fpga/Kconfig                   | 8 ++++++++
 include/configs/astro_mcf5373l.h       | 2 --
 include/configs/socfpga_common.h       | 3 ---
 include/configs/theadorable.h          | 2 --
 18 files changed, 22 insertions(+), 7 deletions(-)

configs/astro_mcf5373l_defconfig +0 -0

index d5e8430..80fb1fa 100644

configs/astro_mcf5373l_defconfig +0 -0

 CONFIG_MTD_NOR_FLASH=y

configs/socfpga_arria5_defconfig +1 -0

index a565384..6f2a06f 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_cyclone5_defconfig +1 -0

index 06fc82c..1047657 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de0_nano_soc_defconfig +1 -0

index 0697e2e..72a9e5d 100644
@@ -39,6 +39,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de10_nano_defconfig +1 -0

index cd64fb9..67864cf 100644
@@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de1_soc_defconfig +1 -0

index bba90be..35c4484 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_is1_defconfig +1 -0

index 058791e..ae688f8 100644
@@ -34,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_mcvevk_defconfig +1 -0

index 627b90f..c5e3b7b 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sockit_defconfig +1 -0

index bf5d63d..3ff7bb7 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_socrates_defconfig +1 -0

index 5915faf..fb9c13f 100644
@@ -41,6 +41,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sr1500_defconfig +1 -0

index 4468d3b..d90d6a1 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_vining_fpga_defconfig +1 -0

index fb9bae4..c3fbe40 100644
@@ -44,6 +44,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_LED_STATUS=y

configs/theadorable_debug_defconfig +1 -0

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

configs/theadorable_defconfig +1 -0

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_PARTITION_UUIDS is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

drivers/fpga/Kconfig +8 -0

index a760944..6b2c866 100644
@@ -13,6 +13,14 @@ config FPGA_ALTERA
 	  Enable Altera FPGA specific functions which includes bitstream
 	  (in BIT format), fpga and device validation.
 
+config FPGA_SOCFPGA
+	bool "Enable Gen5 and Arria10 common FPGA drivers"
+	select FPGA_ALTERA
+	help
+	  Say Y here to enable the Gen5 and Arria10 common FPGA driver
+
+	  This provides common functionality for Gen5 and Arria10 devices.
+
 config FPGA_CYCLON2
 	bool "Enable Altera FPGA driver for Cyclone II"
 	depends on FPGA_ALTERA

include/configs/astro_mcf5373l.h +0 -2

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
 #define	CONFIG_FPGA_XILINX
 #define	CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT		1000

include/configs/socfpga_common.h +0 -3

index da7e4ad..1b79c03 100644
@@ -107,9 +107,6 @@
  */
 #ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT		1
 #endif
 #endif

include/configs/theadorable.h +0 -2

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
 #define CONFIG_SYS_MEM_TOP_HIDE		0x80000
 
 /* FPGA programming support */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_STRATIX_V
 
 /*

Quoted 30 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
   CONFIG_FPGA
   CONFIG_FPGA_ALTERA
   CONFIG_FPGA_SOCFPGA

Signed-off-by Tien Fong Chee <[email protected]>

---
 configs/astro_mcf5373l_defconfig       | 1 + configs/socfpga_arria5_defconfig       | 1 + configs/socfpga_cyclone5_defconfig     | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig    | 1 + configs/socfpga_de1_soc_defconfig      | 1 + configs/socfpga_is1_defconfig          | 1 + configs/socfpga_mcvevk_defconfig       | 1 + configs/socfpga_sockit_defconfig       | 1 + configs/socfpga_socrates_defconfig     | 1 + configs/socfpga_sr1500_defconfig       | 1 + configs/socfpga_vining_fpga_defconfig  | 1 + configs/theadorable_debug_defconfig    | 1 + configs/theadorable_defconfig          | 1 + drivers/fpga/Kconfig                   | 8 ++++++++ include/configs/astro_mcf5373l.h       | 2 -- include/configs/socfpga_common.h       | 3 --- include/configs/theadorable.h          | 2 --

 18 files changed, 22 insertions(+), 7 deletions(-)

Quoted 10 lines

configs/astro_mcf5373l_defconfig +0 -0

index d5e8430..80fb1fa 100644
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
  # CONFIG_CMD_NFS is not set

 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y

This MCF should be in separate patch, otherwise looks OK.

Quoted 239 lines

 CONFIG_MTD_NOR_FLASH=y

configs/socfpga_arria5_defconfig +0 -0

index a565384..6f2a06f 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_cyclone5_defconfig +0 -0

index 06fc82c..1047657 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de0_nano_soc_defconfig +0 -0

index 0697e2e..72a9e5d 100644
@@ -39,6 +39,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de10_nano_defconfig +0 -0

index cd64fb9..67864cf 100644
@@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y

 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de1_soc_defconfig +0 -0

index bba90be..35c4484 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y

 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_is1_defconfig +0 -0

index 058791e..ae688f8 100644
@@ -34,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_mcvevk_defconfig +0 -0

index 627b90f..c5e3b7b 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sockit_defconfig +0 -0

index bf5d63d..3ff7bb7 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_socrates_defconfig +0 -0

index 5915faf..fb9c13f 100644
@@ -41,6 +41,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sr1500_defconfig +0 -0

index 4468d3b..d90d6a1 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_vining_fpga_defconfig +0 -0

index fb9bae4..c3fbe40 100644
@@ -44,6 +44,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y

 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_LED_STATUS=y

configs/theadorable_debug_defconfig +0 -0

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
  # CONFIG_SPL_PARTITION_UUIDS is not set

 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

configs/theadorable_defconfig +0 -0

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
  # CONFIG_PARTITION_UUIDS is not set
  # CONFIG_SPL_PARTITION_UUIDS is not set

 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

drivers/fpga/Kconfig +0 -0

index a760944..6b2c866 100644
@@ -13,6 +13,14 @@ config FPGA_ALTERA

    Enable Altera FPGA specific functions which includes bitstream
    (in BIT format), fpga and device validation.

drivers/fpga/Kconfig +5 -0

+config FPGA_SOCFPGA
+	bool "Enable Gen5 and Arria10 common FPGA drivers"
+	select FPGA_ALTERA
+	help
+	  Say Y here to enable the Gen5 and Arria10 common FPGA

driver

drivers/fpga/Kconfig +2 -0

+
+	  This provides common functionality for Gen5 and Arria10

devices.
+
 config FPGA_CYCLON2
  bool "Enable Altera FPGA driver for Cyclone II" depends on FPGA_ALTERA

include/configs/astro_mcf5373l.h +0 -0

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
  #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

 #define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT 1000

include/configs/socfpga_common.h +0 -3

index da7e4ad..1b79c03 100644
@@ -107,9 +107,6 @@
   */
  #ifdef CONFIG_TARGET_SOCFPGA_GEN5
  #ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
  #define CONFIG_FPGA_COUNT		1
  #endif
  #endif

include/configs/theadorable.h +0 -0

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
  #define CONFIG_SYS_MEM_TOP_HIDE		0x80000

 /* FPGA programming support */

include/configs/theadorable.h +0 -2

-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA

 #define CONFIG_FPGA_STRATIX_V

 /*

Quoted 31 lines · Marek Vasut

Quoted 30 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
CONFIG_FPGA
CONFIG_FPGA_ALTERA
CONFIG_FPGA_SOCFPGA

Signed-off-by Tien Fong Chee <[email protected]>

---
 configs/astro_mcf5373l_defconfig       | 1 +
 configs/socfpga_arria5_defconfig       | 1 +
 configs/socfpga_cyclone5_defconfig     | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig    | 1 +
 configs/socfpga_de1_soc_defconfig      | 1 +
 configs/socfpga_is1_defconfig          | 1 +
 configs/socfpga_mcvevk_defconfig       | 1 +
 configs/socfpga_sockit_defconfig       | 1 +
 configs/socfpga_socrates_defconfig     | 1 +
 configs/socfpga_sr1500_defconfig       | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +
 configs/theadorable_debug_defconfig    | 1 +
 configs/theadorable_defconfig          | 1 +
 drivers/fpga/Kconfig                   | 8 ++++++++
 include/configs/astro_mcf5373l.h       | 2 --
 include/configs/socfpga_common.h       | 3 ---
 include/configs/theadorable.h          | 2 --
 18 files changed, 22 insertions(+), 7 deletions(-)

Quoted 12 lines

configs/astro_mcf5373l_defconfig CONFIG_CMD_I2C=y · line 13

Quoted 10 lines

configs/astro_mcf5373l_defconfig +1 -0

index d5e8430..80fb1fa 100644
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y

This MCF should be in separate patch, otherwise looks OK.

Sorry, i am still not catching your point. Why MCF should be in separate patch, because CONFIG_FPGA_ALTERA? If so, that means all defconfigs which contain CONFIG_FPGA_ALTERA should be in separate patch?

Quoted 239 lines

Quoted 239 lines

configs/astro_mcf5373l_defconfig +0 -0

 CONFIG_MTD_NOR_FLASH=y

configs/socfpga_arria5_defconfig +1 -0

index a565384..6f2a06f 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_cyclone5_defconfig +1 -0

index 06fc82c..1047657 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de0_nano_soc_defconfig +1 -0

index 0697e2e..72a9e5d 100644
@@ -39,6 +39,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de10_nano_defconfig +1 -0

index cd64fb9..67864cf 100644
@@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de1_soc_defconfig +1 -0

index bba90be..35c4484 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_is1_defconfig +1 -0

index 058791e..ae688f8 100644
@@ -34,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_mcvevk_defconfig +1 -0

index 627b90f..c5e3b7b 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sockit_defconfig +1 -0

index bf5d63d..3ff7bb7 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_socrates_defconfig +1 -0

index 5915faf..fb9c13f 100644
@@ -41,6 +41,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sr1500_defconfig +1 -0

index 4468d3b..d90d6a1 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_vining_fpga_defconfig +1 -0

index fb9bae4..c3fbe40 100644
@@ -44,6 +44,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_LED_STATUS=y

configs/theadorable_debug_defconfig +1 -0

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

configs/theadorable_defconfig +1 -0

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_PARTITION_UUIDS is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

drivers/fpga/Kconfig +0 -0

index a760944..6b2c866 100644
@@ -13,6 +13,14 @@ config FPGA_ALTERA
 	  Enable Altera FPGA specific functions which includes

bitstream

drivers/fpga/Kconfig +5 -0

 	  (in BIT format), fpga and device validation.
 
+config FPGA_SOCFPGA
+	bool "Enable Gen5 and Arria10 common FPGA drivers"
+	select FPGA_ALTERA
+	help
+	  Say Y here to enable the Gen5 and Arria10 common FPGA

driver

drivers/fpga/Kconfig +2 -0

+
+	  This provides common functionality for Gen5 and Arria10

devices.

drivers/fpga/Kconfig +1 -0

+
 config FPGA_CYCLON2
 	bool "Enable Altera FPGA driver for Cyclone II"
 	depends on FPGA_ALTERA

include/configs/astro_mcf5373l.h +0 -2

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
 #define	CONFIG_FPGA_XILINX
 #define	CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT		1000

include/configs/socfpga_common.h +0 -3

index da7e4ad..1b79c03 100644
@@ -107,9 +107,6 @@
  */
 #ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT		1
 #endif
 #endif

include/configs/theadorable.h +0 -2

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
 #define CONFIG_SYS_MEM_TOP_HIDE		0x80000
 
 /* FPGA programming support */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_STRATIX_V
 
 /*

Quoted 47 lines · Tien Fong

Quoted 45 lines · Marek Vasut

Quoted 38 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
   CONFIG_FPGA
   CONFIG_FPGA_ALTERA
   CONFIG_FPGA_SOCFPGA

Signed-off-by Tien Fong Chee <[email protected]>

---
 configs/astro_mcf5373l_defconfig       | 1 + configs/socfpga_arria5_defconfig       | 1 + configs/socfpga_cyclone5_defconfig     | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig    | 1 + configs/socfpga_de1_soc_defconfig      | 1 + configs/socfpga_is1_defconfig          | 1 + configs/socfpga_mcvevk_defconfig       | 1 + configs/socfpga_sockit_defconfig       | 1 + configs/socfpga_socrates_defconfig     | 1 + configs/socfpga_sr1500_defconfig       | 1 + configs/socfpga_vining_fpga_defconfig  | 1 + configs/theadorable_debug_defconfig    | 1 + configs/theadorable_defconfig          | 1 + drivers/fpga/Kconfig                   | 8 ++++++++ include/configs/astro_mcf5373l.h       | 2 -- include/configs/socfpga_common.h       | 3 --- include/configs/theadorable.h          | 2 --

 18 files changed, 22 insertions(+), 7 deletions(-)

configs/astro_mcf5373l_defconfig +0 -0

index d5e8430..80fb1fa 100644
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
  # CONFIG_CMD_NFS is not set

Quoted 3 lines

 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y

This MCF should be in separate patch, otherwise looks OK.

Quoted 5 lines

Sorry, i am still not catching your point. Why MCF should be in separate patch, because CONFIG_FPGA_ALTERA? If so, that means all defconfigs which contain CONFIG_FPGA_ALTERA should be in separate
patch?

Yes. It's only this one which contains FPGA_ALTERA , no ?

Quoted 244 lines

Quoted 244 lines

Quoted 244 lines

 CONFIG_MTD_NOR_FLASH=y

configs/socfpga_arria5_defconfig +0 -0

index a565384..6f2a06f 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_cyclone5_defconfig +0 -0

index 06fc82c..1047657 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de0_nano_soc_defconfig +0 -0

index 0697e2e..72a9e5d 100644
@@ -39,6 +39,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de10_nano_defconfig +0 -0

index cd64fb9..67864cf 100644
@@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y

 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de1_soc_defconfig +0 -0

index bba90be..35c4484 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y

 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_is1_defconfig +0 -0

index 058791e..ae688f8 100644
@@ -34,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_mcvevk_defconfig +0 -0

index 627b90f..c5e3b7b 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sockit_defconfig +0 -0

index bf5d63d..3ff7bb7 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_socrates_defconfig +0 -0

index 5915faf..fb9c13f 100644
@@ -41,6 +41,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sr1500_defconfig +0 -0

index 4468d3b..d90d6a1 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_vining_fpga_defconfig +0 -0

index fb9bae4..c3fbe40 100644
@@ -44,6 +44,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y

 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_LED_STATUS=y

configs/theadorable_debug_defconfig +0 -0

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
  # CONFIG_SPL_PARTITION_UUIDS is not set

 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

configs/theadorable_defconfig +0 -0

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
  # CONFIG_PARTITION_UUIDS is not set
  # CONFIG_SPL_PARTITION_UUIDS is not set

 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

drivers/fpga/Kconfig +0 -0

index a760944..6b2c866 100644
@@ -13,6 +13,14 @@ config FPGA_ALTERA

    Enable Altera FPGA specific functions which includes bitstream
    (in BIT format), fpga and device validation.

drivers/fpga/Kconfig +5 -0

+config FPGA_SOCFPGA
+	bool "Enable Gen5 and Arria10 common FPGA drivers"
+	select FPGA_ALTERA
+	help
+	  Say Y here to enable the Gen5 and Arria10 common

FPGA
driver

drivers/fpga/Kconfig +2 -0

+
+	  This provides common functionality for Gen5 and

Arria10
devices.
+
 config FPGA_CYCLON2
  bool "Enable Altera FPGA driver for Cyclone II" depends on FPGA_ALTERA

include/configs/astro_mcf5373l.h +0 -0

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
  #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

 #define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT 1000

include/configs/socfpga_common.h +0 -3

index da7e4ad..1b79c03 100644
@@ -107,9 +107,6 @@
   */
  #ifdef CONFIG_TARGET_SOCFPGA_GEN5
  #ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
  #define CONFIG_FPGA_COUNT		1
  #endif
  #endif

include/configs/theadorable.h +0 -0

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
  #define CONFIG_SYS_MEM_TOP_HIDE		0x80000

 /* FPGA programming support */

include/configs/theadorable.h +0 -2

-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA

 #define CONFIG_FPGA_STRATIX_V

 /*

Quoted 53 lines · Marek Vasut

Quoted 52 lines · Tien Fong

Quoted 33 lines · Marek Vasut

Quoted 31 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
CONFIG_FPGA
CONFIG_FPGA_ALTERA
CONFIG_FPGA_SOCFPGA

Signed-off-by Tien Fong Chee <[email protected]>

---
 configs/astro_mcf5373l_defconfig       | 1 +
 configs/socfpga_arria5_defconfig       | 1 +
 configs/socfpga_cyclone5_defconfig     | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig    | 1 +
 configs/socfpga_de1_soc_defconfig      | 1 +
 configs/socfpga_is1_defconfig          | 1 +
 configs/socfpga_mcvevk_defconfig       | 1 +
 configs/socfpga_sockit_defconfig       | 1 +
 configs/socfpga_socrates_defconfig     | 1 +
 configs/socfpga_sr1500_defconfig       | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +
 configs/theadorable_debug_defconfig    | 1 +
 configs/theadorable_defconfig          | 1 +
 drivers/fpga/Kconfig                   | 8 ++++++++
 include/configs/astro_mcf5373l.h       | 2 --
 include/configs/socfpga_common.h       | 3 ---
 include/configs/theadorable.h          | 2 --
 18 files changed, 22 insertions(+), 7 deletions(-)

Quoted 12 lines

configs/astro_mcf5373l_defconfig CONFIG_CMD_I2C=y · line 13

Quoted 10 lines

configs/astro_mcf5373l_defconfig +1 -0

index d5e8430..80fb1fa 100644
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y

This MCF should be in separate patch, otherwise looks OK.

Sorry, i am still not catching your point. Why MCF should be in separate patch, because CONFIG_FPGA_ALTERA? If so, that means all defconfigs which contain CONFIG_FPGA_ALTERA should be in separate
patch?

Quoted 2 lines

Yes. It's only this one which contains FPGA_ALTERA , no ?

no, a few contain FPGA_ALTERA such
as theadorable_defconfig, theadorable_debug_defconfig...

Quoted 244 lines

Quoted 244 lines

Quoted 244 lines

Quoted 244 lines

configs/astro_mcf5373l_defconfig +0 -0

 CONFIG_MTD_NOR_FLASH=y

configs/socfpga_arria5_defconfig +1 -0

index a565384..6f2a06f 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_cyclone5_defconfig +1 -0

index 06fc82c..1047657 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de0_nano_soc_defconfig +1 -0

index 0697e2e..72a9e5d 100644
@@ -39,6 +39,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de10_nano_defconfig +1 -0

index cd64fb9..67864cf 100644
@@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de1_soc_defconfig +1 -0

index bba90be..35c4484 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_is1_defconfig +1 -0

index 058791e..ae688f8 100644
@@ -34,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_mcvevk_defconfig +1 -0

index 627b90f..c5e3b7b 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sockit_defconfig +1 -0

index bf5d63d..3ff7bb7 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_socrates_defconfig +1 -0

index 5915faf..fb9c13f 100644
@@ -41,6 +41,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sr1500_defconfig +1 -0

index 4468d3b..d90d6a1 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_vining_fpga_defconfig +1 -0

index fb9bae4..c3fbe40 100644
@@ -44,6 +44,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_LED_STATUS=y

configs/theadorable_debug_defconfig +1 -0

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

configs/theadorable_defconfig +1 -0

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_PARTITION_UUIDS is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

drivers/fpga/Kconfig +0 -0

index a760944..6b2c866 100644
@@ -13,6 +13,14 @@ config FPGA_ALTERA
 	  Enable Altera FPGA specific functions which includes

bitstream

drivers/fpga/Kconfig +5 -0

 	  (in BIT format), fpga and device validation.
 
+config FPGA_SOCFPGA
+	bool "Enable Gen5 and Arria10 common FPGA drivers"
+	select FPGA_ALTERA
+	help
+	  Say Y here to enable the Gen5 and Arria10 common

FPGA
driver

drivers/fpga/Kconfig +2 -0

+
+	  This provides common functionality for Gen5 and

Arria10
devices.

drivers/fpga/Kconfig +1 -0

+
 config FPGA_CYCLON2
 	bool "Enable Altera FPGA driver for Cyclone II"
 	depends on FPGA_ALTERA

include/configs/astro_mcf5373l.h +0 -2

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
 #define	CONFIG_FPGA_XILINX
 #define	CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT		1000

include/configs/socfpga_common.h +0 -3

index da7e4ad..1b79c03 100644
@@ -107,9 +107,6 @@
  */
 #ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT		1
 #endif
 #endif

include/configs/theadorable.h +0 -2

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
 #define CONFIG_SYS_MEM_TOP_HIDE		0x80000
 
 /* FPGA programming support */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_STRATIX_V
 
 /*

Quoted 59 lines · Tien Fong

Quoted 57 lines · Marek Vasut

Quoted 55 lines · Tien Fong

Quoted 35 lines · Marek Vasut

Quoted 32 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
   CONFIG_FPGA
   CONFIG_FPGA_ALTERA
   CONFIG_FPGA_SOCFPGA

Signed-off-by Tien Fong Chee <[email protected]>

---
 configs/astro_mcf5373l_defconfig       | 1 + configs/socfpga_arria5_defconfig       | 1 + configs/socfpga_cyclone5_defconfig     | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig    | 1 + configs/socfpga_de1_soc_defconfig      | 1 + configs/socfpga_is1_defconfig          | 1 + configs/socfpga_mcvevk_defconfig       | 1 + configs/socfpga_sockit_defconfig       | 1 + configs/socfpga_socrates_defconfig     | 1 + configs/socfpga_sr1500_defconfig       | 1 + configs/socfpga_vining_fpga_defconfig  | 1 + configs/theadorable_debug_defconfig    | 1 + configs/theadorable_defconfig          | 1 + drivers/fpga/Kconfig                   | 8 ++++++++ include/configs/astro_mcf5373l.h       | 2 -- include/configs/socfpga_common.h       | 3 --- include/configs/theadorable.h          | 2 --

 18 files changed, 22 insertions(+), 7 deletions(-)

Quoted 12 lines

Quoted 10 lines

configs/astro_mcf5373l_defconfig +0 -0

index d5e8430..80fb1fa 100644
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
  # CONFIG_CMD_NFS is not set

 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y

This MCF should be in separate patch, otherwise looks OK.

Sorry, i am still not catching your point. Why MCF should be in separate patch, because CONFIG_FPGA_ALTERA? If so, that means all defconfigs which contain CONFIG_FPGA_ALTERA should be in separate
patch?

Quoted 4 lines

Quoted 2 lines

Yes. It's only this one which contains FPGA_ALTERA , no ?

no, a few contain FPGA_ALTERA such
as theadorable_defconfig, theadorable_debug_defconfig...

Then split them please.

Quoted 251 lines

Quoted 251 lines

Quoted 251 lines

Quoted 251 lines

Quoted 251 lines

 CONFIG_MTD_NOR_FLASH=y

configs/socfpga_arria5_defconfig +0 -0

index a565384..6f2a06f 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_cyclone5_defconfig +0 -0

index 06fc82c..1047657 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de0_nano_soc_defconfig +0 -0

index 0697e2e..72a9e5d 100644
@@ -39,6 +39,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de10_nano_defconfig +0 -0

index cd64fb9..67864cf 100644
@@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y

 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_de1_soc_defconfig +0 -0

index bba90be..35c4484 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y

 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_is1_defconfig +0 -0

index 058791e..ae688f8 100644
@@ -34,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_mcvevk_defconfig +0 -0

index 627b90f..c5e3b7b 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sockit_defconfig +0 -0

index bf5d63d..3ff7bb7 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_socrates_defconfig +0 -0

index 5915faf..fb9c13f 100644
@@ -41,6 +41,7 @@ CONFIG_CMD_UBI=y

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_sr1500_defconfig +0 -0

index 4468d3b..d90d6a1 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y

 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

configs/socfpga_vining_fpga_defconfig +0 -0

index fb9bae4..c3fbe40 100644
@@ -44,6 +44,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y

 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_LED_STATUS=y

configs/theadorable_debug_defconfig +0 -0

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
  # CONFIG_SPL_PARTITION_UUIDS is not set

 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

configs/theadorable_defconfig +0 -0

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
  # CONFIG_PARTITION_UUIDS is not set
  # CONFIG_SPL_PARTITION_UUIDS is not set

 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

drivers/fpga/Kconfig +0 -0

index a760944..6b2c866 100644
@@ -13,6 +13,14 @@ config FPGA_ALTERA

    Enable Altera FPGA specific functions which includes
bitstream
    (in BIT format), fpga and device validation.

drivers/fpga/Kconfig +5 -0

+config FPGA_SOCFPGA
+	bool "Enable Gen5 and Arria10 common FPGA drivers"
+	select FPGA_ALTERA
+	help
+	  Say Y here to enable the Gen5 and Arria10 common

FPGA
driver

drivers/fpga/Kconfig +2 -0

+
+	  This provides common functionality for Gen5 and

Arria10
devices.
+
 config FPGA_CYCLON2
  bool "Enable Altera FPGA driver for Cyclone II" depends on FPGA_ALTERA

include/configs/astro_mcf5373l.h +0 -0

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
  #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSI

ZE

 #define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT 1000

include/configs/socfpga_common.h +0 -3

index da7e4ad..1b79c03 100644
@@ -107,9 +107,6 @@
   */
  #ifdef CONFIG_TARGET_SOCFPGA_GEN5
  #ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
  #define CONFIG_FPGA_COUNT		1
  #endif
  #endif

include/configs/theadorable.h +0 -0

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
  #define CONFIG_SYS_MEM_TOP_HIDE		0x80000

 /* FPGA programming support */

include/configs/theadorable.h +0 -2

-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA

 #define CONFIG_FPGA_STRATIX_V

 /*

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on SPL

Signed-off-by Tien Fong Chee <[email protected]>

---
 configs/socfpga_arria5_defconfig       | 1 +
 configs/socfpga_cyclone5_defconfig     | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig    | 1 +
 configs/socfpga_de1_soc_defconfig      | 1 +
 configs/socfpga_is1_defconfig          | 1 +
 configs/socfpga_mcvevk_defconfig       | 1 +
 configs/socfpga_sockit_defconfig       | 1 +
 configs/socfpga_socrates_defconfig     | 1 +
 configs/socfpga_sr1500_defconfig       | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +
 11 files changed, 11 insertions(+)

configs/socfpga_arria5_defconfig +1 -0

index 6f2a06f..4b1e252 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_cyclone5_defconfig +1 -0

index 1047657..fe7ac08 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de0_nano_soc_defconfig +1 -0

index 72a9e5d..d86a9d6 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de10_nano_defconfig +1 -0

index 67864cf..ac8ca70 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de1_soc_defconfig +1 -0

index 35c4484..cc0a35d 100644
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y

configs/socfpga_is1_defconfig +1 -0

index ae688f8..ccfed7a 100644
@@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_mcvevk_defconfig +1 -0

index c5e3b7b..9bcb47d 100644
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_sockit_defconfig +1 -0

index 3ff7bb7..ef54e1f 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_socrates_defconfig +1 -0

index fb9c13f..78daf26 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_sr1500_defconfig +1 -0

index d90d6a1..4a12379 100644
@@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_vining_fpga_defconfig +1 -0

index c3fbe40..3fc37dc 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

Quoted 4 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on SPL

Why would we want that on Gen5 ? I believe this is only needed on Gen10.

Quoted 160 lines

Signed-off-by Tien Fong Chee <[email protected]>

---
 configs/socfpga_arria5_defconfig       | 1 +
 configs/socfpga_cyclone5_defconfig     | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig    | 1 +
 configs/socfpga_de1_soc_defconfig      | 1 +
 configs/socfpga_is1_defconfig          | 1 +
 configs/socfpga_mcvevk_defconfig       | 1 +
 configs/socfpga_sockit_defconfig       | 1 +
 configs/socfpga_socrates_defconfig     | 1 +
 configs/socfpga_sr1500_defconfig       | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +

 11 files changed, 11 insertions(+)

configs/socfpga_arria5_defconfig +0 -0

index 6f2a06f..4b1e252 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_cyclone5_defconfig +0 -0

index 1047657..fe7ac08 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de0_nano_soc_defconfig +0 -0

index 72a9e5d..d86a9d6 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de10_nano_defconfig +0 -0

index 67864cf..ac8ca70 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de1_soc_defconfig +0 -0

index 35c4484..cc0a35d 100644
@@ -16,6 +16,7 @@ CONFIG_SPL=y
  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set

 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y

configs/socfpga_is1_defconfig +0 -0

index ae688f8..ccfed7a 100644
@@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y
  # CONFIG_DISPLAY_BOARDINFO is not set

 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_mcvevk_defconfig +0 -0

index c5e3b7b..9bcb47d 100644
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_sockit_defconfig +0 -0

index 3ff7bb7..ef54e1f 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_socrates_defconfig +0 -0

index fb9c13f..78daf26 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_sr1500_defconfig +0 -0

index d90d6a1..4a12379 100644
@@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_F=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_vining_fpga_defconfig +0 -0

index c3fbe40..3fc37dc 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

Quoted 4 lines · Marek Vasut

Quoted 3 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

Quoted 4 lines

Quoted 1 line

This patch is for enabling FPGA driver support on SPL

Why would we want that on Gen5 ? I believe this is only needed on Gen10.

I already moved the fpga_manager driver into drivers/fpga/ on patch 6, and fpga_manager drivers are required on SPL. Actually fpga_manager driver should be part of the drivers/fpga.

Quoted 160 lines

Quoted 160 lines

Signed-off-by Tien Fong Chee <[email protected]>

---
 configs/socfpga_arria5_defconfig       | 1 +
 configs/socfpga_cyclone5_defconfig     | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig    | 1 +
 configs/socfpga_de1_soc_defconfig      | 1 +
 configs/socfpga_is1_defconfig          | 1 +
 configs/socfpga_mcvevk_defconfig       | 1 +
 configs/socfpga_sockit_defconfig       | 1 +
 configs/socfpga_socrates_defconfig     | 1 +
 configs/socfpga_sr1500_defconfig       | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +
 11 files changed, 11 insertions(+)

configs/socfpga_arria5_defconfig +1 -0

index 6f2a06f..4b1e252 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_cyclone5_defconfig +1 -0

index 1047657..fe7ac08 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de0_nano_soc_defconfig +1 -0

index 72a9e5d..d86a9d6 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de10_nano_defconfig +1 -0

index 67864cf..ac8ca70 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de1_soc_defconfig +1 -0

index 35c4484..cc0a35d 100644
@@ -16,6 +16,7 @@ CONFIG_SPL=y
 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y

configs/socfpga_is1_defconfig +1 -0

index ae688f8..ccfed7a 100644
@@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_mcvevk_defconfig +1 -0

index c5e3b7b..9bcb47d 100644
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_sockit_defconfig +1 -0

index 3ff7bb7..ef54e1f 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_socrates_defconfig +1 -0

index fb9c13f..78daf26 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_sr1500_defconfig +1 -0

index d90d6a1..4a12379 100644
@@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_vining_fpga_defconfig +1 -0

index c3fbe40..3fc37dc 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y
 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

Quoted 8 lines · Tien Fong

Quoted 6 lines · Marek Vasut

Quoted 4 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

Quoted 8 lines

Quoted 4 lines

Quoted 1 line

This patch is for enabling FPGA driver support on SPL

Why would we want that on Gen5 ? I believe this is only needed on Gen10.

I already moved the fpga_manager driver into drivers/fpga/ on patch 6,
and fpga_manager drivers are required on SPL. Actually fpga_manager driver should be part of the drivers/fpga.

I think I miss some fundamental piece of information . Why would I need
anything from the FPGA framework in SPL on Gen5 ? It is not needed thus
far. Is it because you shuffled some of the code around or what ?

Quoted 163 lines

Quoted 163 lines

Quoted 163 lines

Signed-off-by Tien Fong Chee <[email protected]>

---
 configs/socfpga_arria5_defconfig       | 1 +
 configs/socfpga_cyclone5_defconfig     | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig    | 1 +
 configs/socfpga_de1_soc_defconfig      | 1 +
 configs/socfpga_is1_defconfig          | 1 +
 configs/socfpga_mcvevk_defconfig       | 1 +
 configs/socfpga_sockit_defconfig       | 1 +
 configs/socfpga_socrates_defconfig     | 1 +
 configs/socfpga_sr1500_defconfig       | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +

 11 files changed, 11 insertions(+)

configs/socfpga_arria5_defconfig +0 -0

index 6f2a06f..4b1e252 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_cyclone5_defconfig +0 -0

index 1047657..fe7ac08 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de0_nano_soc_defconfig +0 -0

index 72a9e5d..d86a9d6 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de10_nano_defconfig +0 -0

index 67864cf..ac8ca70 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_de1_soc_defconfig +0 -0

index 35c4484..cc0a35d 100644
@@ -16,6 +16,7 @@ CONFIG_SPL=y
  # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set

 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y

configs/socfpga_is1_defconfig +0 -0

index ae688f8..ccfed7a 100644
@@ -12,6 +12,7 @@ CONFIG_VERSION_VARIABLE=y
  # CONFIG_DISPLAY_BOARDINFO is not set

 CONFIG_SPL=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_mcvevk_defconfig +0 -0

index c5e3b7b..9bcb47d 100644
@@ -13,6 +13,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_sockit_defconfig +0 -0

index 3ff7bb7..ef54e1f 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_socrates_defconfig +0 -0

index fb9c13f..78daf26 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_sr1500_defconfig +0 -0

index d90d6a1..4a12379 100644
@@ -16,6 +16,7 @@ CONFIG_BOARD_EARLY_INIT_F=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

configs/socfpga_vining_fpga_defconfig +0 -0

index c3fbe40..3fc37dc 100644
@@ -14,6 +14,7 @@ CONFIG_VERSION_VARIABLE=y

 CONFIG_SPL=y
 CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set

Quoted 17 lines · Marek Vasut

Quoted 16 lines · Tien Fong

Quoted 10 lines · Marek Vasut

Quoted 5 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on SPL

Why would we want that on Gen5 ? I believe this is only needed on Gen10.

I already moved the fpga_manager driver into drivers/fpga/ on patch 6,
and fpga_manager drivers are required on SPL. Actually fpga_manager driver should be part of the drivers/fpga.

Quoted 6 lines

I think I miss some fundamental piece of information . Why would I need
anything from the FPGA framework in SPL on Gen5 ? It is not needed thus
far. Is it because you shuffled some of the code around or what ?

Because we need to know some status and mode type from FPGA even we did not program FPGA in SPL.

Quoted 34 lines · Tien Fong

Quoted 32 lines · Marek Vasut

Quoted 16 lines · Tien Fong

Quoted 6 lines · Marek Vasut

Quoted 3 lines · tien.fong.chee at intel.com

Quoted 7 lines

Quoted 3 lines

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on SPL

Why would we want that on Gen5 ? I believe this is only needed on
Gen10.

Quoted 6 lines

I already moved the fpga_manager driver into drivers/fpga/ on patch
6,
and fpga_manager drivers are required on SPL. Actually fpga_manager
driver should be part of the drivers/fpga.

I think I miss some fundamental piece of information . Why would I
need
anything from the FPGA framework in SPL on Gen5 ? It is not needed
thus
far. Is it because you shuffled some of the code around or what ?

Quoted 3 lines

Because we need to know some status and mode type from FPGA even we did
not program FPGA in SPL.

But we didn't have this option enabled before and everything worked on
gen5, why do we need it now ?

Quoted 38 lines · Marek Vasut

Quoted 37 lines · Tien Fong

Quoted 24 lines · Marek Vasut

Quoted 16 lines · Tien Fong

Quoted 6 lines · Marek Vasut

Quoted 3 lines · tien.fong.chee at intel.com

Quoted 7 lines

Quoted 3 lines

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on SPL

Why would we want that on Gen5 ? I believe this is only needed on
Gen10.

Quoted 6 lines

I already moved the fpga_manager driver into drivers/fpga/ on patch
6,
and fpga_manager drivers are required on SPL. Actually fpga_manager
driver should be part of the drivers/fpga.

Quoted 8 lines

I think I miss some fundamental piece of information . Why would I
need
anything from the FPGA framework in SPL on Gen5 ? It is not needed
thus
far. Is it because you shuffled some of the code around or what ?

Because we need to know some status and mode type from FPGA even we did
not program FPGA in SPL.

Quoted 4 lines

But we didn't have this option enabled before and everything worked on
gen5, why do we need it now ?

Because i already move them into fpga driver, because those functions should be part of fpga driver. So, this moving happen in patch 6.

Quoted 55 lines · Tien Fong

Quoted 53 lines · Marek Vasut

Quoted 42 lines · Tien Fong

Quoted 29 lines · Marek Vasut

Quoted 19 lines · Tien Fong

Quoted 8 lines · Marek Vasut

Quoted 4 lines · tien.fong.chee at intel.com

Quoted 7 lines

Quoted 3 lines

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on SPL

Why would we want that on Gen5 ? I believe this is only needed on
Gen10.

Quoted 7 lines

I already moved the fpga_manager driver into drivers/fpga/ on
patch
6,
and fpga_manager drivers are required on SPL. Actually fpga_manager
driver should be part of the drivers/fpga.

Quoted 10 lines

I think I miss some fundamental piece of information . Why would
I
need
anything from the FPGA framework in SPL on Gen5 ? It is not needed
thus
far. Is it because you shuffled some of the code around or what ?

Quoted 4 lines

Because we need to know some status and mode type from FPGA even we
did
not program FPGA in SPL.

But we didn't have this option enabled before and everything worked
on
gen5, why do we need it now ?

Quoted 3 lines

Because i already move them into fpga driver, because those functions
should be part of fpga driver. So, this moving happen in patch 6.

I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA framework ? Does the size of the Gen5 SPL change before and after this
patchset ? If you did not check, please do.

Quoted 59 lines · Marek Vasut

Quoted 58 lines · Tien Fong

Quoted 44 lines · Marek Vasut

Quoted 42 lines · Tien Fong

Quoted 39 lines · Marek Vasut

Quoted 19 lines · Tien Fong

Quoted 8 lines · Marek Vasut

Quoted 4 lines · tien.fong.chee at intel.com

Quoted 7 lines

Quoted 3 lines

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on SPL

Why would we want that on Gen5 ? I believe this is only needed on
Gen10.

Quoted 7 lines

I already moved the fpga_manager driver into drivers/fpga/ on
patch
6,
and fpga_manager drivers are required on SPL. Actually fpga_manager
driver should be part of the drivers/fpga.

I think I miss some fundamental piece of information . Why would
I
need
anything from the FPGA framework in SPL on Gen5 ? It is not needed
thus
far. Is it because you shuffled some of the code around or what ?

Quoted 9 lines

Quoted 4 lines

Because we need to know some status and mode type from FPGA even we
did
not program FPGA in SPL.

But we didn't have this option enabled before and everything worked
on
gen5, why do we need it now ?

Because i already move them into fpga driver, because those functions
should be part of fpga driver. So, this moving happen in patch 6.

Quoted 4 lines

I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA framework ? Does the size of the Gen5 SPL change before and after this
patchset ? If you did not check, please do.

Yeah, i confirm FPGA driver is availabled in SPL. A bit change in size, 1~2K more. I did the test on our devkits also.

Quoted 81 lines · Tien Fong

Quoted 79 lines · Marek Vasut

Quoted 69 lines · Tien Fong

Quoted 57 lines · Marek Vasut

Quoted 54 lines · Tien Fong

Quoted 50 lines · Marek Vasut

Quoted 25 lines · Tien Fong

Quoted 11 lines · Marek Vasut

Quoted 5 lines · tien.fong.chee at intel.com

Quoted 9 lines

Quoted 4 lines

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on
SPL

Why would we want that on Gen5 ? I believe this is only
needed on
Gen10.

Quoted 8 lines

I already moved the fpga_manager driver into drivers/fpga/
on
patch
6,
and fpga_manager drivers are required on SPL. Actually fpga_manager
driver should be part of the drivers/fpga.

I think I miss some fundamental piece of information . Why
would
I
need
anything from the FPGA framework in SPL on Gen5 ? It is not
needed
thus
far. Is it because you shuffled some of the code around or
what ?

Quoted 9 lines

Quoted 4 lines

Because we need to know some status and mode type from FPGA even we
did
not program FPGA in SPL.

But we didn't have this option enabled before and everything worked
on
gen5, why do we need it now ?

Quoted 4 lines

Because i already move them into fpga driver, because those functions
should be part of fpga driver. So, this moving happen in patch 6.

I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA framework ? Does the size of the Gen5 SPL change before and after this
patchset ? If you did not check, please do.

Quoted 3 lines

Yeah, i confirm FPGA driver is availabled in SPL. A bit change in size,
1~2K more. I did the test on our devkits also.

OK, so that's not acceptable because we're already very close to the size limit of the SPL.

Quoted 100 lines · Marek Vasut

Quoted 98 lines · Tien Fong

Quoted 87 lines · Marek Vasut

Quoted 79 lines · Tien Fong

Quoted 69 lines · Marek Vasut

Quoted 60 lines · Tien Fong

Quoted 42 lines · Marek Vasut

Quoted 28 lines · Tien Fong

Quoted 13 lines · Marek Vasut

Quoted 6 lines · tien.fong.chee at intel.com

Quoted 9 lines

Quoted 4 lines

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on
SPL

Why would we want that on Gen5 ? I believe this is only
needed on
Gen10.

Quoted 9 lines

I already moved the fpga_manager driver into
drivers/fpga/
on
patch
6,
and fpga_manager drivers are required on SPL.
Actually
fpga_manager
driver should be part of the drivers/fpga.

Quoted 13 lines

I think I miss some fundamental piece of information . Why
would
I
need
anything from the FPGA framework in SPL on Gen5 ? It is not
needed
thus
far. Is it because you shuffled some of the code around or
what ?

Quoted 5 lines

Because we need to know some status and mode type from FPGA
even we
did
not program FPGA in SPL.

Quoted 6 lines

But we didn't have this option enabled before and
everything
worked
on
gen5, why do we need it now ?

Quoted 5 lines

Because i already move them into fpga driver, because those functions
should be part of fpga driver. So, this moving happen in patch
6.

Quoted 5 lines

I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA framework ? Does the size of the Gen5 SPL change before and after
this
patchset ? If you did not check, please do.

Yeah, i confirm FPGA driver is availabled in SPL. A bit change in size,
1~2K more. I did the test on our devkits also.

Quoted 4 lines

OK, so that's not acceptable because we're already very close to the
size limit of the SPL.

Any safety guideline?
I checked the spl.map, we still have 10K left after calculation including bss size.

Thanks.

Quoted 105 lines · Tien Fong

Quoted 104 lines · Marek Vasut

Quoted 90 lines · Tien Fong

Quoted 87 lines · Marek Vasut

Quoted 84 lines · Tien Fong

Quoted 69 lines · Marek Vasut

Quoted 60 lines · Tien Fong

Quoted 42 lines · Marek Vasut

Quoted 28 lines · Tien Fong

Quoted 13 lines · Marek Vasut

Quoted 6 lines · tien.fong.chee at intel.com

Quoted 9 lines

Quoted 4 lines

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on
SPL

Why would we want that on Gen5 ? I believe this is only
needed on
Gen10.

Quoted 9 lines

I already moved the fpga_manager driver into
drivers/fpga/
on
patch
6,
and fpga_manager drivers are required on SPL.
Actually
fpga_manager
driver should be part of the drivers/fpga.

Quoted 13 lines

I think I miss some fundamental piece of information . Why
would
I
need
anything from the FPGA framework in SPL on Gen5 ? It is not
needed
thus
far. Is it because you shuffled some of the code around or
what ?

Quoted 5 lines

Because we need to know some status and mode type from FPGA
even we
did
not program FPGA in SPL.

Quoted 6 lines

But we didn't have this option enabled before and
everything
worked
on
gen5, why do we need it now ?

Because i already move them into fpga driver, because those functions
should be part of fpga driver. So, this moving happen in patch
6.

Quoted 8 lines

Quoted 5 lines

I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA framework ? Does the size of the Gen5 SPL change before and after
this
patchset ? If you did not check, please do.

Yeah, i confirm FPGA driver is availabled in SPL. A bit change in size,
1~2K more. I did the test on our devkits also.

OK, so that's not acceptable because we're already very close to the
size limit of the SPL.

Quoted 4 lines

Any safety guideline?
I checked the spl.map, we still have 10K left after calculation including bss size.

I compiled all Intel fpga related defconfigs, and we have 9K free based on total 64K memory size. SO building PFGA driver would contribute around 1~2K only to SPL size. Do you have concern with that?

If you have concern, i would remove patch 6, keep fpga_manager intact.

Quoted 1 line

Thanks.

Quoted 131 lines · Tien Fong

Quoted 129 lines · Tien Fong

Quoted 127 lines · Marek Vasut

Quoted 115 lines · Tien Fong

Quoted 105 lines · Marek Vasut

Quoted 95 lines · Tien Fong

Quoted 84 lines · Marek Vasut

Quoted 73 lines · Tien Fong

Quoted 51 lines · Marek Vasut

Quoted 36 lines · Tien Fong

Quoted 19 lines · Marek Vasut

Quoted 10 lines · tien.fong.chee at intel.co m

From: Tien Fong Chee <[email protected]
m>

Quoted 9 lines

Quoted 3 lines

This patch is for enabling FPGA driver
support on
SPL

Why would we want that on Gen5 ? I believe this
is
only
needed on
Gen10.

Quoted 9 lines

I already moved the fpga_manager driver into
drivers/fpga/
on
patch
6,
and fpga_manager drivers are required on SPL.
Actually
fpga_manager
driver should be part of the drivers/fpga.

Quoted 16 lines

I think I miss some fundamental piece of
information .
Why
would
I
need
anything from the FPGA framework in SPL on Gen5 ?
It is
not
needed
thus
far. Is it because you shuffled some of the code
around
or
what ?

Quoted 6 lines

Because we need to know some status and mode type
from
FPGA
even we
did
not program FPGA in SPL.

Quoted 6 lines

But we didn't have this option enabled before and
everything
worked
on
gen5, why do we need it now ?

Quoted 6 lines

Because i already move them into fpga driver, because those
functions
should be part of fpga driver. So, this moving happen in patch
6.

Quoted 6 lines

I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA
framework ? Does the size of the Gen5 SPL change before and after
this
patchset ? If you did not check, please do.

Quoted 4 lines

Yeah, i confirm FPGA driver is availabled in SPL. A bit change in
size,
1~2K more. I did the test on our devkits also.

OK, so that's not acceptable because we're already very close to
the
size limit of the SPL.

Quoted 8 lines

Quoted 4 lines

Any safety guideline?
I checked the spl.map, we still have 10K left after calculation including bss size.

I compiled all Intel fpga related defconfigs, and we have 9K free based
on total 64K memory size. SO building PFGA driver would contribute around 1~2K only to SPL size. Do you have concern with that?

Yes

Quoted 3 lines

If you have concern, i would remove patch 6, keep fpga_manager intact.

Can't you rework things such that they don't add useless code into the
SPL instead ?

Quoted 3 lines

Quoted 3 lines

Thanks.

Quoted 13 lines

Quoted 8 lines

Quoted 4 lines

Any safety guideline?
I checked the spl.map, we still have 10K left after calculation including bss size.

I compiled all Intel fpga related defconfigs, and we have 9K free based
on total 64K memory size. SO building PFGA driver would contribute around 1~2K only to SPL size. Do you have concern with that?

Yes

Quoted 3 lines

If you have concern, i would remove patch 6, keep fpga_manager intact.

Quoted 4 lines

Can't you rework things such that they don't add useless code into the
SPL instead ?

I checked the codes yesterday, mostly are bridge, and HPS-FPGA interface configuration in SPL. So, i think we can try to remove them as they are not required in SPL, but i need more time to test it out and ensure this change doesn't break anything.

To avoid impact the progress of submitting the rest of patchset as they are still pending until this patchset is accepted , so i suggest we can do it in later. So, i will keep fpga_manager in there.

sounds good to you?

Quoted 3 lines

Quoted 3 lines

Quoted 3 lines

Thanks.

On 06/08/2017 05:40 AM, Chee, Tien Fong wrote:
[...]

Quoted 26 lines

Quoted 19 lines

Quoted 9 lines

Quoted 9 lines

Any safety guideline?
I checked the spl.map, we still have 10K left after calculation
including bss size.

Quoted 6 lines

I compiled all Intel fpga related defconfigs, and we have 9K free
based
on total 64K memory size. SO building PFGA driver would contribute
around 1~2K only to SPL size. Do you have concern with that?

Yes

Quoted 2 lines

Quoted 7 lines

Quoted 2 lines

If you have concern, i would remove patch 6, keep fpga_manager intact.

Can't you rework things such that they don't add useless code into
the
SPL instead ?

Quoted 6 lines

I checked the codes yesterday, mostly are bridge, and HPS-FPGA interface configuration in SPL. So, i think we can try to remove them
as they are not required in SPL, but i need more time to test it out
and ensure this change doesn't break anything.

That's fine, we're past RC1 anyway.

Quoted 7 lines

To avoid impact the progress of submitting the rest of patchset as they
are still pending until this patchset is accepted , so i suggest we can
do it in later. So, i will keep fpga_manager in there.

Quoted 1 line

sounds good to you?

You have about two months till the next MW opens , so if you want to flesh this out, please do.

Quoted 7 lines

Quoted 7 lines

Quoted 7 lines

Quoted 7 lines

Thanks.

Quoted 43 lines · Marek Vasut

On 06/08/2017 05:40 AM, Chee, Tien Fong wrote:
[...]

Quoted 26 lines

Quoted 19 lines

Quoted 9 lines

Quoted 9 lines

Any safety guideline?
I checked the spl.map, we still have 10K left after calculation
including bss size.

Quoted 6 lines

I compiled all Intel fpga related defconfigs, and we have 9K free
based
on total 64K memory size. SO building PFGA driver would contribute
around 1~2K only to SPL size. Do you have concern with that?

Yes

Quoted 2 lines

Quoted 7 lines

Quoted 2 lines

If you have concern, i would remove patch 6, keep fpga_manager intact.

Can't you rework things such that they don't add useless code into
the
SPL instead ?

Quoted 6 lines

I checked the codes yesterday, mostly are bridge, and HPS-FPGA interface configuration in SPL. So, i think we can try to remove them
as they are not required in SPL, but i need more time to test it out
and ensure this change doesn't break anything.

That's fine, we're past RC1 anyway.

Quoted 7 lines

To avoid impact the progress of submitting the rest of patchset as they
are still pending until this patchset is accepted , so i suggest we can
do it in later. So, i will keep fpga_manager in there.

Quoted 4 lines

Quoted 1 line

sounds good to you?

You have about two months till the next MW opens , so if you want to flesh this out, please do.

Sure, this changes will be in separate patchset, as this is for codes cleaning up and refactoring on gen5.

So, how about the Add Arria 10 FPGA driver v10 patchset overall? Anything else i miss?

I didn't really look since we still have a discussion open on V8 . There is no point in sending new versions while discussion is still open. Also, I'd like some review from Ley/Dinh

Quoted 2 lines · Marek Vasut

Quoted 4 lines

I didn't really look since we still have a discussion open on V8 . There
is no point in sending new versions while discussion is still open. Also, I'd like some review from Ley/Dinh

I've reviewed v6 and gave my Reviewed-by. Now I see there's a v10. Should I be reviewing v10 or wait for a new version?

Dinh

Quoted 15 lines · Dinh Nguyen

Quoted 9 lines · Marek Vasut

I didn't really look since we still have a discussion open on V8 .
There
is no point in sending new versions while discussion is still open.
Also, I'd like some review from Ley/Dinh

I've reviewed v6 and gave my Reviewed-by. Now I see there's a v10. Should I be reviewing v10 or wait for a new version?

Quoted 1 line

Dinh

If Marek agree with my planning, code cleaning for gen5 in different patchset. v10 is updated based on Mareks' comments on v9, then v10 should be the final version.

Thanks.

Quoted 21 lines · Tien Fong

Quoted 12 lines · Dinh Nguyen

Quoted 9 lines · Marek Vasut

I didn't really look since we still have a discussion open on V8 .
There
is no point in sending new versions while discussion is still open.
Also, I'd like some review from Ley/Dinh

Quoted 4 lines

I've reviewed v6 and gave my Reviewed-by. Now I see there's a v10. Should I be reviewing v10 or wait for a new version?

Dinh

If Marek agree with my planning, code cleaning for gen5 in different patchset. v10 is updated based on Mareks' comments on v9, then v10 should be the final version.

Quoted 1 line

Thanks.

Hi Marek,

I think Dinh is still waiting answer from you.

Could you please to
advice?

Quoted 34 lines · Tien Fong

Quoted 31 lines · Tien Fong

Quoted 17 lines · Dinh Nguyen

Quoted 5 lines · Marek Vasut

Quoted 7 lines

I didn't really look since we still have a discussion open on V8
.
There
is no point in sending new versions while discussion is still open.
Also, I'd like some review from Ley/Dinh

Quoted 5 lines

I've reviewed v6 and gave my Reviewed-by. Now I see there's a v10.
Should I be reviewing v10 or wait for a new version?

Dinh

If Marek agree with my planning, code cleaning for gen5 in different
patchset. v10 is updated based on Mareks' comments on v9, then v10
should be the final version.

Quoted 4 lines

Quoted 1 line

Thanks.

Hi Marek,

I think Dinh is still waiting answer from you.

Thanks for reminding me daily. I'm actually on vacation, so sorry for the delayed reply.

Quoted 5 lines

Could you please to
advice?

Actually I lost track of what's going on here, we're still having discussion on V8 and I already have V10 in my mailbox. I have two suggestions:
1) Slow down, bombarding people with new versions of patches every day
   does not help at all. Give people some space to review the patchset,
   discuss and let the discussion settle, then submit a new set. That can take a week or more, so let's establish a rule that you will not
   submit more than one version of the patchset each week unless explicitly asked. OK ?

2) I'd like AB/RB from Dinh on this set, yes.

Quoted 30 lines · Tien Fong

Quoted 28 lines · Tien Fong

Quoted 15 lines · Dinh Nguyen

Quoted 11 lines · Marek Vasut

I didn't really look since we still have a discussion open on V8
.
There
is no point in sending new versions while discussion is still open.
Also, I'd like some review from Ley/Dinh

Quoted 5 lines

I've reviewed v6 and gave my Reviewed-by. Now I see there's a v10.
Should I be reviewing v10 or wait for a new version?

Dinh

If Marek agree with my planning, code cleaning for gen5 in different
patchset. v10 is updated based on Mareks' comments on v9, then v10
should be the final version.

Quoted 4 lines

Quoted 1 line

Thanks.

Hi Marek,

I think Dinh is still waiting answer from you.

Thanks for reminding me daily. I'm actually on vacation, so sorry for the delayed reply.

Quoted 3 lines

Could you please to
advice?

Actually I lost track of what's going on here, we're still having discussion on V8 and I already have V10 in my mailbox. I have two suggestions:
1) Slow down, bombarding people with new versions of patches every day
   does not help at all. Give people some space to review the patchset,
   discuss and let the discussion settle, then submit a new set. That can take a week or more, so let's establish a rule that you will not
   submit more than one version of the patchset each week unless explicitly asked. OK ?
2) I'd like AB/RB from Dinh on this set, yes.

Quoted 31 lines · Marek Vasut

Quoted 30 lines · Tien Fong

Quoted 28 lines · Tien Fong

Quoted 15 lines · Dinh Nguyen

Quoted 11 lines · Marek Vasut

I didn't really look since we still have a discussion open on V8
.
There
is no point in sending new versions while discussion is still open.
Also, I'd like some review from Ley/Dinh

Quoted 5 lines

I've reviewed v6 and gave my Reviewed-by. Now I see there's a v10.
Should I be reviewing v10 or wait for a new version?

Dinh

If Marek agree with my planning, code cleaning for gen5 in different
patchset. v10 is updated based on Mareks' comments on v9, then v10
should be the final version.

Quoted 6 lines

Quoted 4 lines

Quoted 1 line

Thanks.

Hi Marek,

I think Dinh is still waiting answer from you.

Thanks for reminding me daily. I'm actually on vacation, so sorry for the delayed reply.

Quoted 4 lines

Quoted 4 lines

Could you please to
advice?

Quoted 4 lines

Actually I lost track of what's going on here, we're still having discussion on V8 and I already have V10 in my mailbox. I have two suggestions:
1) Slow down, bombarding people with new versions of patches every

Quoted 8 lines

day
does not help at all. Give people some space to review the
patchset,
discuss and let the discussion settle, then submit a new set. That can take a week or more, so let's establish a rule that you will
not
submit more than one version of the patchset each week unless explicitly asked. OK ?

Quoted 2 lines

2) I'd like AB/RB from Dinh on this set, yes.

Hi Dinh,

Could you help to review?

Quoted 85 lines · Marek Vasut

Quoted 84 lines · Tien Fong

Quoted 71 lines · Marek Vasut

Quoted 69 lines · Tien Fong

Quoted 66 lines · Marek Vasut

Quoted 54 lines · Tien Fong

Quoted 37 lines · Marek Vasut

Quoted 25 lines · Tien Fong

Quoted 11 lines · Marek Vasut

Quoted 5 lines · tien.fong.chee at intel.com

Quoted 9 lines

Quoted 4 lines

From: Tien Fong Chee <[email protected]>

This patch is for enabling FPGA driver support on
SPL

Why would we want that on Gen5 ? I believe this is only
needed on
Gen10.

Quoted 8 lines

I already moved the fpga_manager driver into drivers/fpga/
on
patch
6,
and fpga_manager drivers are required on SPL. Actually fpga_manager
driver should be part of the drivers/fpga.

Quoted 13 lines

I think I miss some fundamental piece of information . Why
would
I
need
anything from the FPGA framework in SPL on Gen5 ? It is not
needed
thus
far. Is it because you shuffled some of the code around or
what ?

Quoted 4 lines

Because we need to know some status and mode type from FPGA even we
did
not program FPGA in SPL.

But we didn't have this option enabled before and everything worked
on
gen5, why do we need it now ?

Quoted 8 lines

Quoted 4 lines

Because i already move them into fpga driver, because those functions
should be part of fpga driver. So, this moving happen in patch 6.

I see. Does enabling the FPGA_SPL stuff pull in any of the FPGA framework ? Does the size of the Gen5 SPL change before and after this
patchset ? If you did not check, please do.

Yeah, i confirm FPGA driver is availabled in SPL. A bit change in size,
1~2K more. I did the test on our devkits also.

Quoted 3 lines

OK, so that's not acceptable because we're already very close to the size limit of the SPL.

Any safety guideline?
I checked the spl.map, we still have 10K left after calculation including bss size.

From: Tien Fong Chee <[email protected]>

Enable FPGA driver build for SPL because FPGA driver is needed for SPL to configure and getting DDR up before loading U-boot into DDR and booting from there.

FPGA driver build on SPL must be enabled 1st before applying next patch to avoid build failed, because fpga_manager which would be moved to drivers/fpga by next patch are required in SPL.

Signed-off-by Tien Fong Chee <[email protected]>

---
 drivers/Makefile | 1 +
 1 file changed, 1 insertion(+)

drivers/Makefile +1 -0

index 64c39d3..4478212 100644
@@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 endif
 
 ifdef CONFIG_TPL_BUILD

Quoted 8 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

Enable FPGA driver build for SPL because FPGA driver is needed for SPL
to configure and getting DDR up before loading U-boot into DDR and booting from there.

Quoted 6 lines

FPGA driver build on SPL must be enabled 1st before applying next patch to
avoid build failed, because fpga_manager which would be moved to drivers/fpga by next patch are required in SPL.

Signed-off-by Tien Fong Chee <[email protected]>

You should probably swap this and 4/5 ?

Quoted 18 lines

---
 drivers/Makefile | 1 +

 1 file changed, 1 insertion(+)

drivers/Makefile +0 -0

index 64c39d3..4478212 100644
@@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/

 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 endif

 ifdef CONFIG_TPL_BUILD

Quoted 14 lines · Marek Vasut

Quoted 13 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

Enable FPGA driver build for SPL because FPGA driver is needed for SPL
to configure and getting DDR up before loading U-boot into DDR and booting from there.

FPGA driver build on SPL must be enabled 1st before applying next patch to
avoid build failed, because fpga_manager which would be moved to drivers/fpga by next patch are required in SPL.

Quoted 3 lines

Quoted 1 line

Signed-off-by Tien Fong Chee <[email protected]>

You should probably swap this and 4/5 ?

I have no strong opinion about this swapping. Don't you think that it's much more sensible having enabling FPGA support on SPL(configuration 1st), then only enable the build?

Quoted 18 lines

Quoted 18 lines

---
 drivers/Makefile | 1 +
 1 file changed, 1 insertion(+)

drivers/Makefile +1 -0

index 64c39d3..4478212 100644
@@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 endif
 
 ifdef CONFIG_TPL_BUILD

Quoted 25 lines · Tien Fong

Quoted 23 lines · Marek Vasut

Quoted 11 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

Enable FPGA driver build for SPL because FPGA driver is needed for
SPL
to configure and getting DDR up before loading U-boot into DDR and
booting from there.

Quoted 8 lines

FPGA driver build on SPL must be enabled 1st before applying next
patch to
avoid build failed, because fpga_manager which would be moved to
drivers/fpga by next patch are required in SPL.

Signed-off-by Tien Fong Chee <[email protected]>

You should probably swap this and 4/5 ?

Quoted 5 lines

I have no strong opinion about this swapping. Don't you think that it's
much more sensible having enabling FPGA support on SPL(configuration
1st), then only enable the build?

No, we add all the fixes first, then code and then enable it in configuration.

Quoted 21 lines

Quoted 21 lines

Quoted 21 lines

---
 drivers/Makefile | 1 +

 1 file changed, 1 insertion(+)

drivers/Makefile +0 -0

index 64c39d3..4478212 100644
@@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/

 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 endif

 ifdef CONFIG_TPL_BUILD