Lattice MachXO2 Slave SPI FPGA Manager support

This patch adds support to the FPGA manager for programming MachXO2 device’s internal flash memory, via slave SPI.

Signed-off-by Paolo Pisati <[email protected]>

---
 drivers/fpga/Kconfig       |   7 ++
 drivers/fpga/Makefile      |   1 +
 drivers/fpga/machxo2-spi.c | 277 +++++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 285 insertions(+)
 create mode 100644 drivers/fpga/machxo2-spi.c

drivers/fpga/Kconfig +7 -0

index c81cb7d..cce135b 100644
@@ -26,6 +26,13 @@ config FPGA_MGR_ICE40_SPI
        help
          FPGA manager driver support for Lattice iCE40 FPGAs over SPI.
 
+config FPGA_MGR_MACHXO2_SPI
+       tristate "Lattice MachXO2 SPI"
+       depends on SPI
+       help
+        FPGA manager driver support for Lattice MachXO2 configuration
+        over slave SPI interface.
+
 config FPGA_MGR_SOCFPGA
        tristate "Altera SOCFPGA FPGA Manager"
        depends on ARCH_SOCFPGA || COMPILE_TEST

drivers/fpga/Makefile +1 -0

index c6f5d74..cdab1fe 100644
@@ -7,6 +7,7 @@ obj-$(CONFIG_FPGA)                      += fpga-mgr.o
 
 # FPGA Manager Drivers
 obj-$(CONFIG_FPGA_MGR_ICE40_SPI)       += ice40-spi.o
+obj-$(CONFIG_FPGA_MGR_MACHXO2_SPI)     += machxo2-spi.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA)         += socfpga.o
 obj-$(CONFIG_FPGA_MGR_SOCFPGA_A10)     += socfpga-a10.o
 obj-$(CONFIG_FPGA_MGR_TS73XX)          += ts73xx-fpga.o

drivers/fpga/machxo2-spi.c new file +168 -0

new file mode 100644
index 0000000..ea8793c
@@ -0,0 +1,277 @@
+/**
+ * Lattice MachXO2 Slave SPI Driver
+ *
+ * Copyright (C) 2017 Paolo Pisati <[email protected]>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * Manage Lattice FPGA firmware that is loaded over SPI using
+ * the slave serial configuration interface.
+ */
+
+#include <linux/delay.h>
+#include <linux/fpga/fpga-mgr.h>
+#include <linux/gpio/consumer.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/spi/spi.h>
+
+/* MachXO2 Programming Guide - sysCONFIG Programming Commands */
+
+#define ISC_DISABLE            0x00000026
+#define ISC_ENABLE             0x000008c6
+#define ISC_ERASE              0x0000040e
+#define ISC_NOOP               0xffffffff
+#define ISC_PROGRAMDONE                0x0000005e
+#define LSC_CHECKBUSY          0x000000f0
+#define LSC_INITADDRESS                0x00000046
+#define LSC_PROGINCRNV         0x01000070
+#define LSC_REFRESH            0x00000079
+
+#define BUSYFLAG               BIT(7)
+
+/*
+ * Max CCLK in Slave SPI mode according to 'MachXO2 Family Data
+ * Sheet' sysCONFIG Port Timing Specifications (3-36)
+ */
+#define MACHXO2_MAX_SPEED      66000000
+
+#define MACHXO2_LOW_DELAY      5       /* us */
+#define MACHXO2_HIGH_DELAY     200     /* us */
+#define MACHXO2_REFRESH                4800    /* us */
+
+#define MACHXO2_OP_SIZE                sizeof(u32)
+#define MACHXO2_PAGE_SIZE      16
+#define MACHXO2_BUF_SIZE       (MACHXO2_OP_SIZE + MACHXO2_PAGE_SIZE)
+
+static int wait_until_not_busy(struct spi_device *spi)
+{
+       struct spi_message msg;
+       struct spi_transfer rx, tx;
+       u32 checkbusy = LSC_CHECKBUSY;
+       u8 busy;
+       int ret;
+
+       do {
+               memset(&rx, 0, sizeof(rx));
+               memset(&tx, 0, sizeof(tx));
+               tx.tx_buf = &checkbusy;
+               tx.len = MACHXO2_OP_SIZE;
+               rx.rx_buf = &busy;
+               rx.len = sizeof(busy);
+               spi_message_init(&msg);
+               spi_message_add_tail(&tx, &msg);
+               spi_message_add_tail(&rx, &msg);
+               ret = spi_sync(spi, &msg);
+               if (ret)
+                       return ret;
+       } while (busy & BUSYFLAG);
+
+       return 0;
+}
+
+static enum fpga_mgr_states machxo2_spi_state(struct fpga_manager *mgr)
+{
+       return FPGA_MGR_STATE_UNKNOWN;
+}
+
+static int machxo2_write_init(struct fpga_manager *mgr,
+                             struct fpga_image_info *info,
+                             const char *buf, size_t count)
+{
+       struct spi_device *spi = mgr->priv;
+       struct spi_message msg;
+       struct spi_transfer tx[5];
+       u32 disable = ISC_DISABLE;
+       u32 bypass = ISC_NOOP;
+       u32 enable = ISC_ENABLE;
+       u32 erase = ISC_ERASE;
+       u32 initaddr = LSC_INITADDRESS;
+       int ret;
+
+       if ((info->flags & FPGA_MGR_PARTIAL_RECONFIG)) {
+               dev_err(&mgr->dev,
+                       "Partial reconfiguration is not supported\n");
+               return -ENOTSUPP;
+       }
+
+       memset(tx, 0, sizeof(tx));
+       spi_message_init(&msg);
+       tx[0].tx_buf = &disable;
+       tx[0].len = MACHXO2_OP_SIZE - 1;
+       spi_message_add_tail(&tx[0], &msg);
+
+       tx[1].tx_buf = &bypass;
+       tx[1].len = MACHXO2_OP_SIZE;
+       spi_message_add_tail(&tx[1], &msg);
+       ret = spi_sync(spi, &msg);
+       if (ret)
+               goto fail;
+
+       ret = wait_until_not_busy(spi);
+       if (ret)
+               goto fail;
+
+       spi_message_init(&msg);
+       tx[2].tx_buf = &enable;
+       tx[2].len = MACHXO2_OP_SIZE;
+       tx[2].delay_usecs = MACHXO2_LOW_DELAY;
+       spi_message_add_tail(&tx[2], &msg);
+
+       tx[3].tx_buf = &erase;
+       tx[3].len = MACHXO2_OP_SIZE;
+       spi_message_add_tail(&tx[3], &msg);
+       ret = spi_sync(spi, &msg);
+       if (ret)
+               goto fail;
+
+       ret = wait_until_not_busy(spi);
+       if (ret)
+               goto fail;
+
+       spi_message_init(&msg);
+       tx[4].tx_buf = &initaddr;
+       tx[4].len = MACHXO2_OP_SIZE;
+       spi_message_add_tail(&tx[4], &msg);
+       ret = spi_sync(spi, &msg);
+       if (ret)
+               goto fail;
+
+       return 0;
+
+fail:
+       dev_err(&mgr->dev, "Error during FPGA init.\n");
+       return ret;
+}
+
+static int machxo2_write(struct fpga_manager *mgr, const char *buf,
+                        size_t count)
+{
+       struct spi_device *spi = mgr->priv;
+       struct spi_message msg;
+       struct spi_transfer tx;
+       u32 progincr = LSC_PROGINCRNV;
+       u8 payload[MACHXO2_BUF_SIZE];
+       int i, ret;
+
+       if (count % MACHXO2_PAGE_SIZE != 0) {
+               dev_err(&mgr->dev, "Malformed payload.\n");
+               return -EINVAL;
+       }
+
+       memcpy(payload, &progincr, MACHXO2_OP_SIZE);
+       for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) {
+               memcpy(&payload[MACHXO2_OP_SIZE], &buf[i], MACHXO2_PAGE_SIZE);
+               memset(&tx, 0, sizeof(tx));
+               spi_message_init(&msg);

drivers/fpga/machxo2-spi.c new file +99 -1

+
+       return 0;
+}
+
+static int machxo2_write_complete(struct fpga_manager *mgr,
+                                 struct fpga_image_info *info)
+{
+       struct spi_device *spi = mgr->priv;
+       struct spi_message msg;
+       struct spi_transfer tx[2];
+       u32 progdone = ISC_PROGRAMDONE;
+       u32 refresh = LSC_REFRESH;
+       int ret;
+
+       memset(tx, 0, sizeof(tx));
+       spi_message_init(&msg);
+       tx[0].tx_buf = &progdone;
+       tx[0].len = MACHXO2_OP_SIZE;
+       spi_message_add_tail(&tx[0], &msg);
+       ret = spi_sync(spi, &msg);
+       if (ret)
+               goto fail;
+
+       ret = wait_until_not_busy(spi);
+       if (ret)
+               goto fail;
+
+       spi_message_init(&msg);
+       tx[1].tx_buf = &refresh;
+       tx[1].len = MACHXO2_OP_SIZE - 1;
+       tx[1].delay_usecs = MACHXO2_REFRESH;
+       spi_message_add_tail(&tx[1], &msg);
+       ret = spi_sync(spi, &msg);
+       if (ret)
+               goto fail;
+
+       return 0;
+
+fail:
+       dev_err(&mgr->dev, "Refresh failed.\n");
+       return ret;
+}
+
+static const struct fpga_manager_ops machxo2_ops = {
+       .state = machxo2_spi_state,
+       .write_init = machxo2_write_init,
+       .write = machxo2_write,
+       .write_complete = machxo2_write_complete,
+};
+
+static int machxo2_spi_probe(struct spi_device *spi)
+{
+       struct device *dev = &spi->dev;
+
+       if (spi->max_speed_hz > MACHXO2_MAX_SPEED) {
+               dev_err(dev, "Speed is too high\n");
+               return -EINVAL;
+       }
+
+       return fpga_mgr_register(dev, "Lattice MachXO2 SPI FPGA Manager",
+                                &machxo2_ops, spi);
+}
+
+static int machxo2_spi_remove(struct spi_device *spi)
+{
+       struct device *dev = &spi->dev;
+
+       fpga_mgr_unregister(dev);
+
+       return 0;
+}
+
+static const struct of_device_id of_match[] = {
+       { .compatible = "lattice,machxo2-slave-spi", },
+       {}
+};
+MODULE_DEVICE_TABLE(of, of_match);
+
+static const struct spi_device_id lattice_ids[] = {
+       { "machxo2-slave-spi", 0 },
+       { },
+};
+MODULE_DEVICE_TABLE(spi, lattice_ids);
+
+static struct spi_driver machxo2_spi_driver = {
+       .driver = {
+               .name = "machxo2-slave-spi",
+               .of_match_table = of_match_ptr(of_match),
+       },
+       .probe = machxo2_spi_probe,
+       .remove = machxo2_spi_remove,
+       .id_table = lattice_ids,
+};
+
+module_spi_driver(machxo2_spi_driver)
+
+MODULE_AUTHOR("Paolo Pisati <[email protected]>");
+MODULE_DESCRIPTION("Load Lattice FPGA firmware over SPI");
+MODULE_LICENSE("GPL v2");
--

2.7.4

Quoted 26 lines

drivers/fpga/machxo2-spi.c new file +26 -0

+static int machxo2_write(struct fpga_manager *mgr, const char *buf,
+                        size_t count)
+{
+       struct spi_device *spi = mgr->priv;
+       struct spi_message msg;
+       struct spi_transfer tx;
+       u32 progincr = LSC_PROGINCRNV;
+       u8 payload[MACHXO2_BUF_SIZE];
+       int i, ret;
+
+       if (count % MACHXO2_PAGE_SIZE != 0) {
+               dev_err(&mgr->dev, "Malformed payload.\n");
+               return -EINVAL;
+       }
+
+       memcpy(payload, &progincr, MACHXO2_OP_SIZE);
+       for (i = 0; i < count; i += MACHXO2_PAGE_SIZE) {
+               memcpy(&payload[MACHXO2_OP_SIZE], &buf[i], MACHXO2_PAGE_SIZE);
+               memset(&tx, 0, sizeof(tx));
+               spi_message_init(&msg);
+               tx.tx_buf = payload;
+               tx.len = MACHXO2_BUF_SIZE;
+               tx.delay_usecs = MACHXO2_HIGH_DELAY;
+               spi_message_add_tail(&tx, &msg);
+               ret = spi_sync(spi, &msg);
+               if (ret) {

drivers/fpga/machxo2-spi.c line 178

Quoted 4 lines

drivers/fpga/machxo2-spi.c new file +4 -0

+                       dev_err(&mgr->dev, "Error loading the bitstream.\n");
+                       return ret;
+               }
+       }

Can't you chain them together and submit it as one? Instead of calling spi_sync in a loop?
You don't seem to wait for _wait_until_not_busy, so wouldn't that work?