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powerpc: Only do ERAT invalidate on radix context switch on P9 DD1

PATCH Applied Benjamin Herrenschmidt 2 participants 2 messages Jun 25, 2017 – Jun 29, 2017 PowerPC

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Benjamin Herrenschmidt

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PATCH 1/1 powerpc: Only do ERAT invalidate on radix context switch on P9 DD1

From: Michael Neuling <[email protected]>

On P9 (Nimbus) DD2 and later, in radix mode, the move to the PID register will implicitly invalidate the user space ERAT entries and leave the kernel ones alone. Thus the only thing needed is an isync() to synchronize this with subsequent uaccess's

Signed-off-by Michael Neuling <[email protected]>
Signed-off-by Benjamin Herrenschmidt <[email protected]>
arch/powerpc/mm/mmu_context_book3s64.c +10 -5
index a3edf813d4..71de2c6d88 100644
@@ -235,10 +235,15 @@ void destroy_context(struct mm_struct *mm)
 #ifdef CONFIG_PPC_RADIX_MMU
 void radix__switch_mmu_context(struct mm_struct *prev, struct mm_struct *next)
 {
-	asm volatile("isync": : :"memory");
-	mtspr(SPRN_PID, next->context.id);
-	asm volatile("isync \n"
-		     PPC_SLBIA(0x7)
-		     : : :"memory");
+
+	if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
+		isync();
+		mtspr(SPRN_PID, next->context.id);
+		isync();
+		asm volatile(PPC_INVALIDATE_ERAT : : :"memory");
+	} else {
+		mtspr(SPRN_PID, next->context.id);
+		isync();
+	}
 }
 #endif
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Quoted 9 lines · Benjamin Herrenschmidt

From: Michael Neuling <[email protected]>

On P9 (Nimbus) DD2 and later, in radix mode, the move to the PID register will implicitly invalidate the user space ERAT entries and leave the kernel ones alone. Thus the only thing needed is an isync() to synchronize this with subsequent uaccess's

Signed-off-by Michael Neuling <[email protected]>
Signed-off-by Benjamin Herrenschmidt <[email protected]>

Applied to powerpc next, thanks.

https://git.kernel.org/powerpc/c/74e27c6af56fe6898c3c8c45159574

cheers