Patch "clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset" has been added to the 4.9-stable tree

This is a note to let you know that I've just added the patch titled

clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
clk-sunxi-ng-a31-correct-lcd1-ch1-clock-register-offset.patch
and it can be found in the queue-4.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

From: Chen-Yu Tsai <[email protected]>
Date: Wed, 3 May 2017 11:13:46 +0800
Subject: clk: sunxi-ng: a31: Correct lcd1-ch1 clock register offset

From: Chen-Yu Tsai <[email protected]>

commit 38b8f823864707eb1cf331d2247608c419ed388c upstream.

The register offset for the lcd1-ch1 clock was incorrectly pointing to the lcd0-ch1 clock. This resulted in the lcd0-ch1 clock being disabled when the clk core disables unused clocks. This then stops the simplefb HDMI output path.

---
 drivers/clk/sunxi-ng/ccu-sun6i-a31.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

@@ -556,7 +556,7 @@ static SUNXI_CCU_M_WITH_MUX_GATE(lcd0_ch
 				 0x12c, 0, 4, 24, 3, BIT(31),
 				 CLK_SET_RATE_PARENT);
 static SUNXI_CCU_M_WITH_MUX_GATE(lcd1_ch1_clk, "lcd1-ch1", lcd_ch1_parents,
-				 0x12c, 0, 4, 24, 3, BIT(31),
+				 0x130, 0, 4, 24, 3, BIT(31),
 				 CLK_SET_RATE_PARENT);
 
 static const char * const csi_sclk_parents[] = { "pll-video0", "pll-video1",

Patches currently in stable-queue which might be from [email protected] are

queue-4.9/clk-sunxi-ng-a31-correct-lcd1-ch1-clock-register-offset.patch