Add Intel Arria 10 SoC FPGA driver

From: Tien Fong Chee <[email protected]>

Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver intact. All the changes are still keeping in driver/fpga/ and no functional change. Subsequent patch would move FPGA manager driver from arch/arm into driver/fpga/.

Signed-off-by Tien Fong Chee <[email protected]>

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

---
 arch/arm/mach-socfpga/Makefile                     |   2 +-
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  68 +-----
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 +++---
 drivers/fpga/Makefile                              |   1 +
 drivers/fpga/socfpga.c                             | 241 +--------------------
 drivers/fpga/{socfpga.c => socfpga_gen5.c}         |  54 +----
 6 files changed, 49 insertions(+), 386 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)

drivers/fpga/socfpga.c +0 -9

 static struct socfpga_fpga_manager *fpgamgr_regs =
 	(struct socfpga_fpga_manager *)SOCFPGA_FPGAMGRREGS_ADDRESS;
-static struct socfpga_system_manager *sysmgr_regs =
-	(struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
 
-/* Set CD ratio */
-static void fpgamgr_set_cd_ratio(unsigned long ratio)
-{
-	clrsetbits_le32(&fpgamgr_regs->ctrl,
-			0x3 << FPGAMGRREGS_CTRL_CDRATIO_LSB,
-			(ratio & 0x3) << FPGAMGRREGS_CTRL_CDRATIO_LSB);
-}

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
CONFIG_FPGA
CONFIG_FPGA_ALTERA

Signed-off-by Tien Fong Chee <[email protected]>

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

---
 configs/astro_mcf5373l_defconfig    | 1 +
 configs/theadorable_debug_defconfig | 1 +
 configs/theadorable_defconfig       | 1 +
 include/configs/astro_mcf5373l.h    | 2 --
 include/configs/theadorable.h       | 2 --
 5 files changed, 3 insertions(+), 4 deletions(-)

configs/astro_mcf5373l_defconfig +1 -0

index d5e8430..80fb1fa 100644
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_MTD_NOR_FLASH=y

configs/theadorable_debug_defconfig +1 -0

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

configs/theadorable_defconfig +1 -0

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_PARTITION_UUIDS is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

include/configs/astro_mcf5373l.h +0 -2

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
 #define	CONFIG_FPGA_XILINX
 #define	CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT		1000

include/configs/theadorable.h +0 -2

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
 #define CONFIG_SYS_MEM_TOP_HIDE		0x80000
 
 /* FPGA programming support */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_STRATIX_V
 
 /*

Quoted 7 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
   CONFIG_FPGA
   CONFIG_FPGA_ALTERA

Quoted 3 lines

Signed-off-by Tien Fong Chee <[email protected]>

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

Did you run make savedefconfig on all these boards or did you just put
the CONFIG_FPGA_ALTERA=y into their defconfigs ?

Quoted 77 lines

---
 configs/astro_mcf5373l_defconfig    | 1 +
 configs/theadorable_debug_defconfig | 1 +
 configs/theadorable_defconfig       | 1 +
 include/configs/astro_mcf5373l.h    | 2 --
 include/configs/theadorable.h       | 2 --

 5 files changed, 3 insertions(+), 4 deletions(-)

configs/astro_mcf5373l_defconfig +0 -0

index d5e8430..80fb1fa 100644
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
  # CONFIG_CMD_NFS is not set

 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_MTD_NOR_FLASH=y

configs/theadorable_debug_defconfig +0 -0

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
  # CONFIG_SPL_PARTITION_UUIDS is not set

 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

configs/theadorable_defconfig +0 -0

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
  # CONFIG_PARTITION_UUIDS is not set
  # CONFIG_SPL_PARTITION_UUIDS is not set

 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

include/configs/astro_mcf5373l.h +0 -0

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
  #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

 #define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT 1000

include/configs/theadorable.h +0 -0

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
  #define CONFIG_SYS_MEM_TOP_HIDE		0x80000

 /* FPGA programming support */

include/configs/theadorable.h +0 -2

-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA

 #define CONFIG_FPGA_STRATIX_V

 /*

Quoted 11 lines · Marek Vasut

Quoted 10 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
CONFIG_FPGA
CONFIG_FPGA_ALTERA

Signed-off-by Tien Fong Chee <[email protected]>

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

Quoted 4 lines

Did you run make savedefconfig on all these boards or did you just put
the CONFIG_FPGA_ALTERA=y into their defconfigs ?

I'm not only run make defconfig. I also running compilation on all effeted defconfigs.

Quoted 77 lines

Quoted 77 lines

---
 configs/astro_mcf5373l_defconfig    | 1 +
 configs/theadorable_debug_defconfig | 1 +
 configs/theadorable_defconfig       | 1 +
 include/configs/astro_mcf5373l.h    | 2 --
 include/configs/theadorable.h       | 2 --
 5 files changed, 3 insertions(+), 4 deletions(-)

configs/astro_mcf5373l_defconfig +1 -0

index d5e8430..80fb1fa 100644
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_MTD_NOR_FLASH=y

configs/theadorable_debug_defconfig +1 -0

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

configs/theadorable_defconfig +1 -0

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_PARTITION_UUIDS is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

include/configs/astro_mcf5373l.h +0 -2

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
 #define	CONFIG_FPGA_XILINX
 #define	CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT		1000

include/configs/theadorable.h +0 -2

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
 #define CONFIG_SYS_MEM_TOP_HIDE		0x80000
 
 /* FPGA programming support */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_STRATIX_V
 
 /*

Quoted 20 lines · Tien Fong

Quoted 18 lines · Marek Vasut

Quoted 11 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
   CONFIG_FPGA
   CONFIG_FPGA_ALTERA

Signed-off-by Tien Fong Chee <[email protected]>

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

Did you run make savedefconfig on all these boards or did you just
put
the CONFIG_FPGA_ALTERA=y into their defconfigs ?

Quoted 2 lines

I'm not only run make defconfig. I also running compilation on all effeted defconfigs.

That doesn't answer my question. Did you do something like make savedefconfig
cp defconfig configs/foo_defconfig
?

Quoted 80 lines

Quoted 80 lines

Quoted 80 lines

---
 configs/astro_mcf5373l_defconfig    | 1 +
 configs/theadorable_debug_defconfig | 1 +
 configs/theadorable_defconfig       | 1 +
 include/configs/astro_mcf5373l.h    | 2 --
 include/configs/theadorable.h       | 2 --

 5 files changed, 3 insertions(+), 4 deletions(-)

configs/astro_mcf5373l_defconfig +0 -0

index d5e8430..80fb1fa 100644
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
  # CONFIG_CMD_NFS is not set

 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_MTD_NOR_FLASH=y

configs/theadorable_debug_defconfig +0 -0

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
  # CONFIG_SPL_PARTITION_UUIDS is not set

 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

configs/theadorable_defconfig +0 -0

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
  # CONFIG_PARTITION_UUIDS is not set
  # CONFIG_SPL_PARTITION_UUIDS is not set

 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

include/configs/astro_mcf5373l.h +0 -0

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
  #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

 #define CONFIG_FPGA_COUNT 1
-#define CONFIG_FPGA
 #define CONFIG_FPGA_XILINX
 #define CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT 1000

include/configs/theadorable.h +0 -0

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
  #define CONFIG_SYS_MEM_TOP_HIDE		0x80000

 /* FPGA programming support */

include/configs/theadorable.h +0 -2

-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA

 #define CONFIG_FPGA_STRATIX_V

 /*

From: Tien Fong Chee <[email protected]>

Enable FPGA driver build for SPL because FPGA driver is needed for SPL to configure and getting DDR up before loading U-boot into DDR and booting from there.

Signed-off-by Tien Fong Chee <[email protected]>

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

---
 drivers/Makefile | 1 +
 1 file changed, 1 insertion(+)

drivers/Makefile +1 -0

index 64c39d3..4478212 100644
@@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 endif
 
 ifdef CONFIG_TPL_BUILD

Quoted 7 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

Enable FPGA driver build for SPL because FPGA driver is needed for SPL
to configure and getting DDR up before loading U-boot into DDR and booting from there.

It is only needed for that on Arria 10 , not elsewhere.

Quoted 21 lines

Signed-off-by Tien Fong Chee <[email protected]>

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

---
 drivers/Makefile | 1 +

 1 file changed, 1 insertion(+)

drivers/Makefile +0 -0

index 64c39d3..4478212 100644
@@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/

 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 endif

 ifdef CONFIG_TPL_BUILD

From: Tien Fong Chee <[email protected]>

Add FPGA driver support for Arria 10.

Signed-off-by Tien Fong Chee <[email protected]>

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

configs/socfpga_arria10_defconfig +2 -0

@@ -6,6 +6,7 @@ CONFIG_IDENT_STRING="socfpga_arria10"
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
 CONFIG_SPL=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y

@@ -22,6 +23,7 @@ CONFIG_DOS_PARTITION=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y

drivers/fpga/Makefile +1 -0

index b65e5ba..08c9ff8 100644
@@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
 obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
 obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
 endif

drivers/fpga/socfpga_arria10.c new file +82 -0

new file mode 100644
index 0000000..5c717a8
@@ -0,0 +1,479 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/misc.h>
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+
+#define CFGWDTH_32	1
+#define MIN_BITSTREAM_SIZECHECK	230
+#define ENCRYPTION_OFFSET	69
+#define COMPRESSION_OFFSET	229
+#define FPGA_TIMEOUT_MSEC	1000  /* timeout in ms */
+#define FPGA_TIMEOUT_CNT	0x1000000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_fpga_manager *fpga_manager_base =
+		(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+static const struct socfpga_system_manager *system_manager_base =
+		(void *)SOCFPGA_SYSMGR_ADDRESS;
+
+static void fpgamgr_set_cd_ratio(unsigned long ratio);
+
+static uint32_t fpgamgr_get_msel(void)
+{
+	u32 reg;
+
+	reg = readl(&fpga_manager_base->imgcfg_stat);
+	reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
+
+	return reg;
+}
+
+static void fpgamgr_set_cfgwdth(int width)
+{
+	if (width)
+		setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+			ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+	else
+		clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+			ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK);
+}
+
+int is_fpgamgr_user_mode(void)
+{
+	return (readl(&fpga_manager_base->imgcfg_stat) &
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) != 0;
+}
+
+static int wait_for_user_mode(void)
+{
+	return wait_for_bit(__func__,
+		&fpga_manager_base->imgcfg_stat,
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
+		1, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int is_fpgamgr_early_user_mode(void)
+{
+	return (readl(&fpga_manager_base->imgcfg_stat) &
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK) != 0;
+}
+
+int fpgamgr_wait_early_user_mode(void)
+{
+	u32 sync_data = 0xffffffff;
+	u32 i = 0;
+	unsigned start = get_timer(0);
+	unsigned long cd_ratio;

drivers/fpga/socfpga_arria10.c new file +47 -0

+		if (get_timer(start) > FPGA_TIMEOUT_MSEC)
+			return -ETIMEDOUT;
+		fpgamgr_program_write((const long unsigned int *)&sync_data,
+				sizeof(sync_data));
+		udelay(FPGA_TIMEOUT_MSEC);
+		i++;
+	}
+
+	debug("Additional %i sync word needed\n", i);
+
+	/* restoring original CDRATIO */
+	fpgamgr_set_cd_ratio(cd_ratio);
+
+	return 0;
+}
+
+/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted */
+static int wait_for_nconfig_pin_and_nstatus_pin(void)
+{
+	unsigned long mask = ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |
+				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK;
+
+	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop until de-asserted,
+	 * timeout at 1000ms
+	 */
+	return wait_for_bit(__func__,
+			    &fpga_manager_base->imgcfg_stat,
+			    mask,
+			    false, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int wait_for_f2s_nstatus_pin(unsigned long value)
+{
+	/* Poll until f2s to specific value, timeout at 1000ms */
+	return wait_for_bit(__func__,
+			    &fpga_manager_base->imgcfg_stat,
+			    ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PIN_SET_MSK,
+			    value, FPGA_TIMEOUT_MSEC, false);
+}
+
+/* set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+	clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+		ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+
+	setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,

drivers/fpga/socfpga_arria10.c new file +74 -0

+		printf("Fail: read msel=%d\n", msel);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * Write cdratio and cdwidth based on whether the bitstream is compressed
+ * and/or encoded
+ */
+static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,
+				       size_t rbf_size)
+{
+	unsigned int cd_ratio;
+	bool encrypt, compress;
+
+	/*
+         * According to the bitstream specification,
+	 * both encryption and compression status are
+         * in location before offset 230 of the buffer.
+         */
+	if (rbf_size < MIN_BITSTREAM_SIZECHECK)
+		return -EINVAL;
+
+	encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
+	encrypt = encrypt != 0;
+
+	compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
+	compress = !compress;
+
+	debug("header word %d = %08x\n", 69, rbf_data[69]);
+	debug("header word %d = %08x\n", 229, rbf_data[229]);
+	debug("read from rbf header: encrypt=%d compress=%d\n", encrypt, compress);
+
+	/*
+	 * from the register map description of cdratio in imgcfg_ctrl_02:
+	 *  Normal Configuration    : 32bit Passive Parallel
+	 *  Partial Reconfiguration : 16bit Passive Parallel
+	 */
+
+	/*
+	 * cd ratio is dependent on cfg width and whether the bitstream
+	 * is encrypted and/or compressed.
+	 *
+	 * | width | encr. | compr. | cd ratio |
+	 * |  16   |   0   |   0    |     1    |
+	 * |  16   |   0   |   1    |     4    |
+	 * |  16   |   1   |   0    |     2    |
+	 * |  16   |   1   |   1    |     4    |
+	 * |  32   |   0   |   0    |     1    |
+	 * |  32   |   0   |   1    |     8    |
+	 * |  32   |   1   |   0    |     4    |
+	 * |  32   |   1   |   1    |     8    |
+	 */
+	if (!compress && !encrypt) {
+		cd_ratio = CDRATIO_x1;
+	} else {
+		if (compress)
+			cd_ratio = CDRATIO_x4;
+		else
+			cd_ratio = CDRATIO_x2;
+
+		/* if 32 bit, double the cd ratio (so register
+		   field setting is incremented) */
+		if (cfg_width == CFGWDTH_32)
+			cd_ratio += 1;
+	}
+
+	fpgamgr_set_cfgwdth(cfg_width);
+	fpgamgr_set_cd_ratio(cd_ratio);
+
+	return 0;
+}

include/configs/socfpga_common.h +0 -0

 /*
  * L4 OSC1 Timer 0
  */

Quoted 8 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

Add FPGA driver support for Arria 10.

Signed-off-by Tien Fong Chee <[email protected]>

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

[...]

Quoted 1 line

configs/socfpga_arria10_defconfig

Quoted 5 lines

configs/socfpga_arria10_defconfig +0 -0

index 46bda47..53ab66f 100644

defconfig stuff should be in separate patch.

Quoted 120 lines

configs/socfpga_arria10_defconfig +0 -0

@@ -6,6 +6,7 @@ CONFIG_IDENT_STRING="socfpga_arria10"

 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" CONFIG_SPL=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y

configs/socfpga_arria10_defconfig +0 -0

@@ -22,6 +23,7 @@ CONFIG_DOS_PARTITION=y
  # CONFIG_SPL_DOS_PARTITION is not set

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y

drivers/fpga/Makefile +0 -0

index b65e5ba..08c9ff8 100644
@@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o

 obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o endif

drivers/fpga/socfpga_arria10.c new file +51 -0

new file mode 100644
index 0000000..5c717a8
@@ -0,0 +1,479 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/misc.h>
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+
+#define CFGWDTH_32	1
+#define MIN_BITSTREAM_SIZECHECK	230
+#define ENCRYPTION_OFFSET	69
+#define COMPRESSION_OFFSET	229
+#define FPGA_TIMEOUT_MSEC	1000  /* timeout in ms */
+#define FPGA_TIMEOUT_CNT	0x1000000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_fpga_manager *fpga_manager_base =
+		(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+static const struct socfpga_system_manager *system_manager_base =
+		(void *)SOCFPGA_SYSMGR_ADDRESS;
+
+static void fpgamgr_set_cd_ratio(unsigned long ratio);
+
+static uint32_t fpgamgr_get_msel(void)
+{
+	u32 reg;
+
+	reg = readl(&fpga_manager_base->imgcfg_stat);
+	reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
+
+	return reg;
+}
+
+static void fpgamgr_set_cfgwdth(int width)
+{
+	if (width)
+		setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+			ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK

);

drivers/fpga/socfpga_arria10.c new file +3 -0

+	else
+		clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+			ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK

);

drivers/fpga/socfpga_arria10.c new file +6 -0

+}
+
+int is_fpgamgr_user_mode(void)
+{
+	return (readl(&fpga_manager_base->imgcfg_stat) &
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=

0;

drivers/fpga/socfpga_arria10.c new file +14 -0

+}
+
+static int wait_for_user_mode(void)
+{
+	return wait_for_bit(__func__,
+		&fpga_manager_base->imgcfg_stat,
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
+		1, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int is_fpgamgr_early_user_mode(void)
+{
+	return (readl(&fpga_manager_base->imgcfg_stat) &
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK

) != 0;

drivers/fpga/socfpga_arria10.c new file +8 -0

+}
+
+int fpgamgr_wait_early_user_mode(void)
+{
+	u32 sync_data = 0xffffffff;
+	u32 i = 0;
+	unsigned start = get_timer(0);
+	unsigned long cd_ratio;

drivers/fpga/socfpga_arria10.c line 92

Quoted 10 lines

drivers/fpga/socfpga_arria10.c new file +10 -0

+
+	/* Getting existing CDRATIO */
+	cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &
+		ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
+		ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
+
+	/* Using CDRATIO_X1 for better compatibility */
+	fpgamgr_set_cd_ratio(CDRATIO_x1);
+
+	while (!(is_fpgamgr_early_user_mode())) {

The parens around is_fpga.... are superfluous, drop them.

Quoted 60 lines

drivers/fpga/socfpga_arria10.c new file +3 -0

+		if (get_timer(start) > FPGA_TIMEOUT_MSEC)
+			return -ETIMEDOUT;
+		fpgamgr_program_write((const long unsigned int

*)&sync_data,

drivers/fpga/socfpga_arria10.c new file +14 -0

+				sizeof(sync_data));
+		udelay(FPGA_TIMEOUT_MSEC);
+		i++;
+	}
+
+	debug("Additional %i sync word needed\n", i);
+
+	/* restoring original CDRATIO */
+	fpgamgr_set_cd_ratio(cd_ratio);
+
+	return 0;
+}
+
+/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-

asserted */

drivers/fpga/socfpga_arria10.c new file +3 -0

+static int wait_for_nconfig_pin_and_nstatus_pin(void)
+{
+	unsigned long mask =

ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |

drivers/fpga/socfpga_arria10.c new file +1 -0

+				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU

S_PIN_SET_MSK;

drivers/fpga/socfpga_arria10.c new file +2 -0

+
+	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop

until de-asserted,

drivers/fpga/socfpga_arria10.c new file +14 -0

+	 * timeout at 1000ms
+	 */
+	return wait_for_bit(__func__,
+			    &fpga_manager_base->imgcfg_stat,
+			    mask,
+			    false, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int wait_for_f2s_nstatus_pin(unsigned long value)
+{
+	/* Poll until f2s to specific value, timeout at 1000ms */
+	return wait_for_bit(__func__,
+			    &fpga_manager_base->imgcfg_stat,
+			    ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PI

N_SET_MSK,

drivers/fpga/socfpga_arria10.c new file +15 -0

+			    value, FPGA_TIMEOUT_MSEC, false);
+}
+
+/* set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+	clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+		ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+
+	setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+		(ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
+		ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+}
+
+/* get the MSEL value, verify we are set for FPP configuration

mode */

drivers/fpga/socfpga_arria10.c line 149

Quoted 5 lines

drivers/fpga/socfpga_arria10.c new file +5 -0

+static int fpgamgr_verify_msel(void)
+{
+	u32 msel = fpgamgr_get_msel();
+
+	if ((msel != 0) && (msel != 1)) {

You mean if (msel & ~BIT(0)) ?

Quoted 80 lines

drivers/fpga/socfpga_arria10.c new file +9 -0

+		printf("Fail: read msel=%d\n", msel);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * Write cdratio and cdwidth based on whether the bitstream is

compressed
+ * and/or encoded
+ */
+static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,

drivers/fpga/socfpga_arria10.c new file +22 -0

+				       size_t rbf_size)
+{
+	unsigned int cd_ratio;
+	bool encrypt, compress;
+
+	/*
+         * According to the bitstream specification,
+	 * both encryption and compression status are
+         * in location before offset 230 of the buffer.
+         */
+	if (rbf_size < MIN_BITSTREAM_SIZECHECK)
+		return -EINVAL;
+
+	encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
+	encrypt = encrypt != 0;
+
+	compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
+	compress = !compress;
+
+	debug("header word %d = %08x\n", 69, rbf_data[69]);
+	debug("header word %d = %08x\n", 229, rbf_data[229]);
+	debug("read from rbf header: encrypt=%d compress=%d\n",

encrypt, compress);

drivers/fpga/socfpga_arria10.c new file +3 -0

+
+	/*
+	 * from the register map description of cdratio in

imgcfg_ctrl_02:

drivers/fpga/socfpga_arria10.c new file +6 -0

+	 *  Normal Configuration    : 32bit Passive Parallel
+	 *  Partial Reconfiguration : 16bit Passive Parallel
+	 */
+
+	/*
+	 * cd ratio is dependent on cfg width and whether the

bitstream

drivers/fpga/socfpga_arria10.c new file +31 -0

+	 * is encrypted and/or compressed.
+	 *
+	 * | width | encr. | compr. | cd ratio |
+	 * |  16   |   0   |   0    |     1    |
+	 * |  16   |   0   |   1    |     4    |
+	 * |  16   |   1   |   0    |     2    |
+	 * |  16   |   1   |   1    |     4    |
+	 * |  32   |   0   |   0    |     1    |
+	 * |  32   |   0   |   1    |     8    |
+	 * |  32   |   1   |   0    |     4    |
+	 * |  32   |   1   |   1    |     8    |
+	 */
+	if (!compress && !encrypt) {
+		cd_ratio = CDRATIO_x1;
+	} else {
+		if (compress)
+			cd_ratio = CDRATIO_x4;
+		else
+			cd_ratio = CDRATIO_x2;
+
+		/* if 32 bit, double the cd ratio (so register
+		   field setting is incremented) */
+		if (cfg_width == CFGWDTH_32)
+			cd_ratio += 1;
+	}
+
+	fpgamgr_set_cfgwdth(cfg_width);
+	fpgamgr_set_cd_ratio(cd_ratio);
+
+	return 0;
+}

[...]

Quoted 1 line

Quoted 6 lines

include/configs/socfpga_common.h +0 -0

index 1b79c03..edd973a 100644

include/configs/socfpga_common.h line 112

Quoted 8 lines

include/configs/socfpga_common.h +0 -2

@@ -105,11 +105,10 @@
  /*
   * FPGA Driver
   */
-#ifdef CONFIG_TARGET_SOCFPGA_GEN5
  #ifdef CONFIG_CMD_FPGA
  #define CONFIG_FPGA_COUNT		1
  #endif
-#endif

Should be in separate patch, cf above.

Quoted 5 lines

include/configs/socfpga_common.h +0 -0

  /*
   * L4 OSC1 Timer 0
   */

Quoted 8 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

Add FPGA driver support for Arria 10.

Signed-off-by Tien Fong Chee <[email protected]>

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

[...]

Quoted 1 line

configs/socfpga_arria10_defconfig

Quoted 5 lines

configs/socfpga_arria10_defconfig +0 -0

index 46bda47..53ab66f 100644

defconfig stuff should be in separate patch.

Quoted 123 lines

configs/socfpga_arria10_defconfig +0 -0

@@ -6,6 +6,7 @@ CONFIG_IDENT_STRING="socfpga_arria10"

 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" CONFIG_SPL=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y

configs/socfpga_arria10_defconfig +0 -0

@@ -22,6 +23,7 @@ CONFIG_DOS_PARTITION=y
  # CONFIG_SPL_DOS_PARTITION is not set

 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y

drivers/fpga/Makefile +0 -0

index b65e5ba..08c9ff8 100644
@@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o

 obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o endif

drivers/fpga/socfpga_arria10.c new file +51 -0

new file mode 100644
index 0000000..5c717a8
@@ -0,0 +1,479 @@
+/*
+ * Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <asm/io.h>
+#include <asm/arch/fpga_manager.h>
+#include <asm/arch/reset_manager.h>
+#include <asm/arch/system_manager.h>
+#include <asm/arch/sdram.h>
+#include <asm/arch/misc.h>
+#include <altera.h>
+#include <common.h>
+#include <errno.h>
+#include <wait_bit.h>
+#include <watchdog.h>
+
+#define CFGWDTH_32	1
+#define MIN_BITSTREAM_SIZECHECK	230
+#define ENCRYPTION_OFFSET	69
+#define COMPRESSION_OFFSET	229
+#define FPGA_TIMEOUT_MSEC	1000  /* timeout in ms */
+#define FPGA_TIMEOUT_CNT	0x1000000
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_fpga_manager *fpga_manager_base =
+		(void *)SOCFPGA_FPGAMGRREGS_ADDRESS;
+
+static const struct socfpga_system_manager *system_manager_base =
+		(void *)SOCFPGA_SYSMGR_ADDRESS;
+
+static void fpgamgr_set_cd_ratio(unsigned long ratio);
+
+static uint32_t fpgamgr_get_msel(void)
+{
+	u32 reg;
+
+	reg = readl(&fpga_manager_base->imgcfg_stat);
+	reg = (reg & ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL_SET_MSD) >>
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_MSEL0_LSB;
+
+	return reg;
+}
+
+static void fpgamgr_set_cfgwdth(int width)
+{
+	if (width)
+		setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+			ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK

);

drivers/fpga/socfpga_arria10.c new file +3 -0

+	else
+		clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+			ALT_FPGAMGR_IMGCFG_CTL_02_CFGWIDTH_SET_MSK

);

drivers/fpga/socfpga_arria10.c new file +6 -0

+}
+
+int is_fpgamgr_user_mode(void)
+{
+	return (readl(&fpga_manager_base->imgcfg_stat) &
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK) !=

0;

drivers/fpga/socfpga_arria10.c new file +14 -0

+}
+
+static int wait_for_user_mode(void)
+{
+	return wait_for_bit(__func__,
+		&fpga_manager_base->imgcfg_stat,
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK,
+		1, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int is_fpgamgr_early_user_mode(void)
+{
+	return (readl(&fpga_manager_base->imgcfg_stat) &
+		ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK

) != 0;

drivers/fpga/socfpga_arria10.c new file +11 -0

+}
+
+int fpgamgr_wait_early_user_mode(void)
+{
+	u32 sync_data = 0xffffffff;
+	u32 i = 0;
+	unsigned start = get_timer(0);
+	unsigned long cd_ratio;
+
+	/* Getting existing CDRATIO */
+	cd_ratio = (readl(&fpga_manager_base->imgcfg_ctrl_02) &

drivers/fpga/socfpga_arria10.c line 92

Quoted 7 lines

drivers/fpga/socfpga_arria10.c new file +7 -0

+		ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK) >>
+		ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB;
+
+	/* Using CDRATIO_X1 for better compatibility */
+	fpgamgr_set_cd_ratio(CDRATIO_x1);
+
+	while (!(is_fpgamgr_early_user_mode())) {

The parens around is_fpga.... are superfluous, drop them.

Quoted 58 lines

drivers/fpga/socfpga_arria10.c new file +3 -0

+		if (get_timer(start) > FPGA_TIMEOUT_MSEC)
+			return -ETIMEDOUT;
+		fpgamgr_program_write((const long unsigned int

*)&sync_data,

drivers/fpga/socfpga_arria10.c new file +14 -0

+				sizeof(sync_data));
+		udelay(FPGA_TIMEOUT_MSEC);
+		i++;
+	}
+
+	debug("Additional %i sync word needed\n", i);
+
+	/* restoring original CDRATIO */
+	fpgamgr_set_cd_ratio(cd_ratio);
+
+	return 0;
+}
+
+/* Read f2s_nconfig_pin and f2s_nstatus_pin; loop until de-

asserted */

drivers/fpga/socfpga_arria10.c new file +3 -0

+static int wait_for_nconfig_pin_and_nstatus_pin(void)
+{
+	unsigned long mask =

ALT_FPGAMGR_IMGCFG_STAT_F2S_NCONFIG_PIN_SET_MSK |

drivers/fpga/socfpga_arria10.c new file +1 -0

+				ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATU

S_PIN_SET_MSK;

drivers/fpga/socfpga_arria10.c new file +2 -0

+
+	/* Poll until f2s_nconfig_pin and f2s_nstatus_pin; loop

until de-asserted,

drivers/fpga/socfpga_arria10.c new file +14 -0

+	 * timeout at 1000ms
+	 */
+	return wait_for_bit(__func__,
+			    &fpga_manager_base->imgcfg_stat,
+			    mask,
+			    false, FPGA_TIMEOUT_MSEC, false);
+}
+
+static int wait_for_f2s_nstatus_pin(unsigned long value)
+{
+	/* Poll until f2s to specific value, timeout at 1000ms */
+	return wait_for_bit(__func__,
+			    &fpga_manager_base->imgcfg_stat,
+			    ALT_FPGAMGR_IMGCFG_STAT_F2S_NSTATUS_PI

N_SET_MSK,

drivers/fpga/socfpga_arria10.c new file +14 -0

+			    value, FPGA_TIMEOUT_MSEC, false);
+}
+
+/* set CD ratio */
+static void fpgamgr_set_cd_ratio(unsigned long ratio)
+{
+	clrbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+		ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+
+	setbits_le32(&fpga_manager_base->imgcfg_ctrl_02,
+		(ratio << ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_LSB) &
+		ALT_FPGAMGR_IMGCFG_CTL_02_CDRATIO_SET_MSK);
+}
+

drivers/fpga/socfpga_arria10.c line 149

Quoted 7 lines

+/* get the MSEL value, verify we are set for FPP configuration mode */

drivers/fpga/socfpga_arria10.c new file +5 -0

+static int fpgamgr_verify_msel(void)
+{
+	u32 msel = fpgamgr_get_msel();
+
+	if ((msel != 0) && (msel != 1)) {

You mean if (msel & ~BIT(0)) ?

Quoted 80 lines

drivers/fpga/socfpga_arria10.c new file +9 -0

+		printf("Fail: read msel=%d\n", msel);
+		return -EPERM;
+	}
+
+	return 0;
+}
+
+/*
+ * Write cdratio and cdwidth based on whether the bitstream is

compressed
+ * and/or encoded
+ */
+static int fpgamgr_set_cdratio_cdwidth(unsigned int cfg_width, u32 *rbf_data,

drivers/fpga/socfpga_arria10.c new file +22 -0

+				       size_t rbf_size)
+{
+	unsigned int cd_ratio;
+	bool encrypt, compress;
+
+	/*
+         * According to the bitstream specification,
+	 * both encryption and compression status are
+         * in location before offset 230 of the buffer.
+         */
+	if (rbf_size < MIN_BITSTREAM_SIZECHECK)
+		return -EINVAL;
+
+	encrypt = (rbf_data[ENCRYPTION_OFFSET] >> 2) & 3;
+	encrypt = encrypt != 0;
+
+	compress = (rbf_data[COMPRESSION_OFFSET] >> 1) & 1;
+	compress = !compress;
+
+	debug("header word %d = %08x\n", 69, rbf_data[69]);
+	debug("header word %d = %08x\n", 229, rbf_data[229]);
+	debug("read from rbf header: encrypt=%d compress=%d\n",

encrypt, compress);

drivers/fpga/socfpga_arria10.c new file +3 -0

+
+	/*
+	 * from the register map description of cdratio in

imgcfg_ctrl_02:

drivers/fpga/socfpga_arria10.c new file +6 -0

+	 *  Normal Configuration    : 32bit Passive Parallel
+	 *  Partial Reconfiguration : 16bit Passive Parallel
+	 */
+
+	/*
+	 * cd ratio is dependent on cfg width and whether the

bitstream

drivers/fpga/socfpga_arria10.c new file +31 -0

+	 * is encrypted and/or compressed.
+	 *
+	 * | width | encr. | compr. | cd ratio |
+	 * |  16   |   0   |   0    |     1    |
+	 * |  16   |   0   |   1    |     4    |
+	 * |  16   |   1   |   0    |     2    |
+	 * |  16   |   1   |   1    |     4    |
+	 * |  32   |   0   |   0    |     1    |
+	 * |  32   |   0   |   1    |     8    |
+	 * |  32   |   1   |   0    |     4    |
+	 * |  32   |   1   |   1    |     8    |
+	 */
+	if (!compress && !encrypt) {
+		cd_ratio = CDRATIO_x1;
+	} else {
+		if (compress)
+			cd_ratio = CDRATIO_x4;
+		else
+			cd_ratio = CDRATIO_x2;
+
+		/* if 32 bit, double the cd ratio (so register
+		   field setting is incremented) */
+		if (cfg_width == CFGWDTH_32)
+			cd_ratio += 1;
+	}
+
+	fpgamgr_set_cfgwdth(cfg_width);
+	fpgamgr_set_cd_ratio(cd_ratio);
+
+	return 0;
+}

[...]

Quoted 1 line

Quoted 6 lines

include/configs/socfpga_common.h +0 -0

index 1b79c03..edd973a 100644

include/configs/socfpga_common.h line 112

Quoted 8 lines

include/configs/socfpga_common.h +0 -2

@@ -105,11 +105,10 @@
  /*
   * FPGA Driver
   */
-#ifdef CONFIG_TARGET_SOCFPGA_GEN5
  #ifdef CONFIG_CMD_FPGA
  #define CONFIG_FPGA_COUNT		1
  #endif
-#endif

Should be in separate patch, cf above.

Quoted 5 lines

include/configs/socfpga_common.h +0 -0

  /*
   * L4 OSC1 Timer 0
   */

From: Tien Fong Chee <[email protected]>

This is the 11th version of patchset to adds support for Intel Arria 10 SoC FPGA
driver. This version mainly resolved comments from Dinh in [v10]. This series is
working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-socf
pga.git

[v10]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252583.ht ml

v10 -> v11 changes:
-----------------
- Changed the commit header of patch 3 and patch 4 to "kconfig:", previously was
  "arm: socfpga:".
- Cleaned up commit old message on patch 5.

Patchset history
----------------
[v1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg247788.htm l
[v2]: https://www.mail-archive.com/u-boot at lists.denx.de/msg248541.htm l
[v3]: https://www.mail-archive.com/u-boot at lists.denx.de/msg249160.htm l
[v4]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250149.htm l
[v5]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250517.htm l
[v6]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250687.htm l
[v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg251213.htm l
[v8]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252196.htm l
[v9]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252422.htm l

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

Tien Fong Chee (6):
  arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
  arm: socfpga: Restructure FPGA driver in the preparation to support A10
  kconfig: Convert FPGA and FPGA_ALTERA configuration to Kconfig
  kconfig: Convert FPGA_SOCFPGA configuration to Kconfig
  drivers: Enable FPGA driver build on SPL
  arm: socfpga: Add FPGA driver support for Arria 10

 arch/arm/mach-socfpga/Makefile                     |   2 +- arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  70 +-- .../include/mach/fpga_manager_arria10.h            | 100 +++++ .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 ++- .../include/mach/reset_manager_arria10.h           |   2 +- arch/arm/mach-socfpga/reset_manager_arria10.c      |   4 +- configs/astro_mcf5373l_defconfig                   |   1 + configs/socfpga_arria10_defconfig                  |   2 + configs/socfpga_arria5_defconfig                   |   1 + configs/socfpga_cyclone5_defconfig                 |   1 + configs/socfpga_de0_nano_soc_defconfig             |   1 + configs/socfpga_de10_nano_defconfig                |   1 + configs/socfpga_de1_soc_defconfig                  |   1 + configs/socfpga_is1_defconfig                      |   1 + configs/socfpga_mcvevk_defconfig                   |   1 + configs/socfpga_sockit_defconfig                   |   1 + configs/socfpga_socrates_defconfig                 |   1 + configs/socfpga_sr1500_defconfig                   |   1 + configs/socfpga_vining_fpga_defconfig              |   1 + configs/theadorable_debug_defconfig                |   1 + configs/theadorable_defconfig                      |   1 + drivers/Makefile                                   |   1 + drivers/fpga/Kconfig                               |   8 + drivers/fpga/Makefile                              |   2 + drivers/fpga/socfpga.c                             | 241 +---------- drivers/fpga/socfpga_arria10.c                     | 479
+++++++++++++++++++++
 drivers/fpga/{socfpga.c => socfpga_gen5.c}         |  54 +-- include/configs/astro_mcf5373l.h                   |   2 - include/configs/socfpga_common.h                   |   6 +- include/configs/theadorable.h                      |   2 -

 30 files changed, 660 insertions(+), 398 deletions(-)

 create mode 100644 arch/arm/mach- socfpga/include/mach/fpga_manager_arria10.h
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
 create mode 100644 drivers/fpga/socfpga_arria10.c copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)

Quoted 40 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This is the 11th version of patchset to adds support for Intel Arria 10 SoC FPGA
driver. This version mainly resolved comments from Dinh in [v10]. This series is
working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-socf
pga.git

[v10]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252583.ht ml

v10 -> v11 changes:
-----------------
- Changed the commit header of patch 3 and patch 4 to "kconfig:", previously was
"arm: socfpga:".
- Cleaned up commit old message on patch 5.

Patchset history
----------------
[v1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg247788.htm l
[v2]: https://www.mail-archive.com/u-boot at lists.denx.de/msg248541.htm l
[v3]: https://www.mail-archive.com/u-boot at lists.denx.de/msg249160.htm l
[v4]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250149.htm l
[v5]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250517.htm l
[v6]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250687.htm l
[v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg251213.htm l
[v8]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252196.htm l
[v9]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252422.htm l

Quoted 3 lines

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

Dear all reviewers,

Any comment on this patchset?

Quoted 55 lines · Tien Fong

Quoted 53 lines · tien.fong.chee at intel.com

From: Tien Fong Chee <[email protected]>

This is the 11th version of patchset to adds support for Intel Arria
10 SoC FPGA
driver. This version mainly resolved comments from Dinh in [v10]. This series is
working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-
socf
pga.git

[v10]: https://www.mail-archive.com/u-boot at lists.denx.de/msg25258 3.ht
ml

v10 -> v11 changes:
-----------------
- Changed the commit header of patch 3 and patch 4 to "kconfig:", previously was
  "arm: socfpga:".
- Cleaned up commit old message on patch 5.

Patchset history
----------------
[v1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg247788 .htm
l
[v2]: https://www.mail-archive.com/u-boot at lists.denx.de/msg248541 .htm
l
[v3]: https://www.mail-archive.com/u-boot at lists.denx.de/msg249160 .htm
l
[v4]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250149 .htm
l
[v5]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250517 .htm
l
[v6]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250687 .htm
l
[v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg251213 .htm
l
[v8]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252196 .htm
l
[v9]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252422 .htm
l

Quoted 6 lines

Quoted 3 lines

Reviewed-by Ley Foon Tan <[email protected]>

Reviewed-by Dinh Nguyen <[email protected]>

Dear all reviewers,

Any comment on this patchset?

Unless Dinh has comments, one more iteration should do.