armv8:fsl-layerscape: Consolidate registers space defination for CCI-400 bus

PATCH Superseded Ashish Kumar 1 participant 3 messages Jul 20, 2017 Arm (32-bit)

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Ashish Kumar

author

2017-07-20 05:52 UTC #0 lore raw

PATCH v3 1/3 armv8:fsl-layerscape: Consolidate registers space defination for CCI-400 bus

CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters.

This patch add new CONFIG defination "SYS_FSL_HAS_CCI400" and moves existing register space definaton of CCI-400 bus from immap_lsch2 to fsl_immap, so that it can be used for both chasis 2 and chasis 3.

"CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET is introduced in Kconfig

Signed-off-by Ashish Kumar <[email protected]>

Signed-off-by Prabhakar Kushwaha <[email protected]>

---
v3:
This is v3 for https://patchwork.ozlabs.org/patch/731464/

 README                                             |  9 ++++
 arch/arm/cpu/armv8/fsl-layerscape/Kconfig          | 13 ++++++
 arch/arm/cpu/armv8/fsl-layerscape/cpu.c            |  1 +
 arch/arm/cpu/armv8/fsl-layerscape/soc.c            | 10 +++--
 .../include/asm/arch-fsl-layerscape/immap_lsch2.h  | 49 ---------------------
 board/freescale/ls1012afrdm/ls1012afrdm.c          |  4 +-
 board/freescale/ls1012aqds/ls1012aqds.c            |  4 +-
 board/freescale/ls1012ardb/ls1012ardb.c            |  3 +-
 board/freescale/ls1021aqds/ls1021aqds.c            |  9 ++--
 include/fsl_immap.h                                | 51 ++++++++++++++++++++++
 10 files changed, 94 insertions(+), 59 deletions(-)

README +9 -0

index c73f6dd..165f403 100644
@@ -312,6 +312,15 @@ Many of the options are named exactly as the corresponding Linux
 kernel configuration options. The intention is to make it easier to
 build a config tool - later.
 
+- ARM Platform Bus Type(CCI):
+		CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which
+		provides full cache coherency between two clusters of multi-core
+		CPUs and I/O coherency for devices and I/O masters
+
+		CONFIG_SYS_FSL_HAS_CCI400
+
+		Defined For SoC that has cache coherent interconnect
+		CCN-400
 
 The following options need to be configured:

arch/arm/cpu/armv8/fsl-layerscape/Kconfig +13 -0

index 5825f9b..1132969 100644
@@ -84,6 +84,7 @@ config ARCH_LS2080A
 
 config FSL_LSCH2
 	bool
+	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_HAS_SEC
 	select SYS_FSL_SEC_COMPAT_5
 	select SYS_FSL_SEC_BE

@@ -247,6 +248,15 @@ config QSPI_AHB_INIT
 	  But some QSPI flash size up to 64MBytes, so initialize the QSPI AHB
 	  bus for those flashes to support the full QSPI flash size.
 
+config SYS_CCI400_OFFSET
+	hex "Offset for CCI400 base"
+	depends on SYS_FSL_HAS_CCI400
+	default 0x3090000 if ARCH_LS1088A
+	default 0x180000 if FSL_LSCH2
+	help
+	  Offset for CCI400 base
+	  CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
 config SYS_FSL_IFC_BANK_COUNT
 	int "Maximum banks of Integrated flash controller"
 	depends on ARCH_LS1043A || ARCH_LS1046A || ARCH_LS2080A

@@ -254,6 +264,9 @@ config SYS_FSL_IFC_BANK_COUNT
 	default 4 if ARCH_LS1046A
 	default 8 if ARCH_LS2080A
 
+config SYS_FSL_HAS_CCI400
+	bool
+
 config SYS_FSL_HAS_DP_DDR
 	bool

arch/arm/cpu/armv8/fsl-layerscape/cpu.c +1 -0

index c6fede3..f38e388 100644
@@ -214,6 +214,7 @@ static inline void final_mmu_setup(void)
 		}
 	}
 #endif
+#include <fsl_immap.h>
 
 	/* Reset the fill ptr */
 	gd->arch.tlb_fillptr = tlb_addr_save;

arch/arm/cpu/armv8/fsl-layerscape/soc.c +7 -3

index aee1ffa..ddb7d82 100644
@@ -5,6 +5,7 @@
  */
 
 #include <common.h>
+#include <fsl_immap.h>
 #include <fsl_ifc.h>
 #include <ahci.h>
 #include <scsi.h>

@@ -285,7 +286,8 @@ static void erratum_a008850_early(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 	/* part 1 of 2 */
-	struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+						CONFIG_SYS_CCI400_OFFSET);
 	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 
 	/* Skip if running at lower exception level */

@@ -304,7 +306,8 @@ void erratum_a008850_post(void)
 {
 #ifdef CONFIG_SYS_FSL_ERRATUM_A008850
 	/* part 2 of 2 */
-	struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+						CONFIG_SYS_CCI400_OFFSET);
 	struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR;
 	u32 tmp;

@@ -439,7 +442,8 @@ int setup_chip_volt(void)
 
 void fsl_lsch2_early_init_f(void)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+					CONFIG_SYS_CCI400_OFFSET);
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS

arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +0 ~~-49~~

61 lines not on this page · raw message

board/freescale/ls1012afrdm/ls1012afrdm.c +3 -1

index 25d22d2..9afd1c4 100644
@@ -71,7 +71,9 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+					CONFIG_SYS_CCI400_OFFSET);
+
 	/*
 	 * Set CCI-400 control override register to enable barrier
 	 * transaction

board/freescale/ls1012aqds/ls1012aqds.c +2 -2

index 97ab340..406194d 100644
@@ -106,8 +106,8 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)
-				   CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+				   CONFIG_SYS_CCI400_OFFSET);
 
 	/* Set CCI-400 control override register to enable barrier
 	 * transaction */

board/freescale/ls1012ardb/ls1012ardb.c +2 -1

index a21e4c4..c6c1c71 100644
@@ -104,7 +104,8 @@ int board_early_init_f(void)
 
 int board_init(void)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+					CONFIG_SYS_CCI400_OFFSET);
 	/*
 	 * Set CCI-400 control override register to enable barrier
 	 * transaction

board/freescale/ls1021aqds/ls1021aqds.c +6 -3

index d81d8ab..8b3f4ad 100644
@@ -204,7 +204,8 @@ int board_early_init_f(void)
 #ifdef CONFIG_SPL_BUILD
 void board_init_f(ulong dummy)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+					CONFIG_SYS_CCI400_OFFSET);
 	unsigned int major;
 
 #ifdef CONFIG_NAND_BOOT

@@ -425,7 +426,8 @@ int misc_init_r(void)
 
 int board_init(void)
 {
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+					CONFIG_SYS_CCI400_OFFSET);
 	unsigned int major;
 
 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315

@@ -460,7 +462,8 @@ int board_init(void)
 #if defined(CONFIG_DEEP_SLEEP)
 void board_sleep_prepare(void)
 {
-	struct ccsr_cci400 __iomem *cci = (void *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR +
+						CONFIG_SYS_CCI400_OFFSET);
 	unsigned int major;
 
 	major = get_soc_major_rev();

include/fsl_immap.h +51 -0

55 lines not on this page · raw message

Signature · 1 line

2.7.4

Ashish Kumar

author

2017-07-20 05:52 UTC #1 lore raw

PATCH v3 2/3 armv7: Consolidate registers space defination for CCI-400 bus

CoreLink Cache Coherent Interconnect (CCI) is ARM BUS which provides full cache coherency between two clusters of multi-core CPUs and I/O coherency for devices and I/O masters.

This patch add new CONFIG defination "FSL_SYS_HAS_CCI400" and removes register space definaton of CCI-400 bus from immap_ls102xa to fsl_immap, since same is defined there already

"CONFIG_SYS_CCI400_ADDR" is depricated and new SYS_CCI400_OFFSET is introduced in Kconfig

Signed-off-by Ashish Kumar <[email protected]>

---
v3:
This is v3 for https://patchwork.ozlabs.org/patch/731464/

 arch/arm/cpu/armv7/ls102xa/Kconfig                | 12 ++++++
 arch/arm/cpu/armv7/ls102xa/soc.c                  |  3 +-
 arch/arm/include/asm/arch-ls102xa/config.h        |  1 -
 arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h | 49 +----------------------
 4 files changed, 16 insertions(+), 49 deletions(-)

arch/arm/cpu/armv7/ls102xa/Kconfig +12 -0

index 6a013b2..61dd522 100644
@@ -5,6 +5,7 @@ config ARCH_LS1021A
 	select SYS_FSL_ERRATUM_A009663
 	select SYS_FSL_ERRATUM_A009942
 	select SYS_FSL_ERRATUM_A010315
+	select SYS_FSL_HAS_CCI400
 	select SYS_FSL_SRDS_1
 	select SYS_HAS_SERDES
 	select SYS_FSL_DDR_BE if SYS_FSL_DDR

@@ -48,9 +49,20 @@ config SECURE_BOOT
 		Enable Freescale Secure Boot feature. Normally selected
 		by defconfig. If unsure, do not change.
 
+config SYS_CCI400_OFFSET
+	hex "Offset for CCI400 base"
+	depends on SYS_FSL_HAS_CCI400
+	default 0x180000
+	help
+	  Offset for CCI400 base.
+	  CCI400 base addr = CCSRBAR + CCI400_OFFSET
+
 config SYS_FSL_ERRATUM_A010315
 	bool "Workaround for PCIe erratum A010315"
 
+config SYS_FSL_HAS_CCI400
+	bool
+
 config SYS_FSL_SRDS_1
 	bool

arch/arm/cpu/armv7/ls102xa/soc.c +2 -1

index b84a1a6..c043b82 100644
@@ -80,7 +80,8 @@ void erratum_a010315(void)
 int arch_soc_init(void)
 {
 	struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
-	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
+	struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR +
+					CONFIG_SYS_CCI400_OFFSET);
 	unsigned int major;
 
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS

arch/arm/include/asm/arch-ls102xa/config.h +0 -1

index fc954c5..ff0fc47 100644
@@ -20,7 +20,6 @@
 
 #define SYS_FSL_GIC_ADDR			(CONFIG_SYS_IMMR + 0x00400000)
 #define CONFIG_SYS_FSL_DDR_ADDR			(CONFIG_SYS_IMMR + 0x00080000)
-#define CONFIG_SYS_CCI400_ADDR			(CONFIG_SYS_IMMR + 0x00180000)
 #define CONFIG_SYS_FSL_CSU_ADDR                 (CONFIG_SYS_IMMR + 0x00510000)
 #define CONFIG_SYS_IFC_ADDR			(CONFIG_SYS_IMMR + 0x00530000)
 #define CONFIG_SYS_FSL_ESDHC_ADDR		(CONFIG_SYS_IMMR + 0x00560000)

arch/arm/include/asm/arch-ls102xa/immap_ls102xa.h +2 ~~-47~~

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Signature · 1 line

2.7.4

Ashish Kumar

author

2017-07-20 05:52 UTC #2 lore raw

PATCH v3 3/3 whitelist: Remove "CONFIG_SYS_CCI400_ADDR" from whitelist

In reply to Ashish Kumar

This config is depricated and new config SYS_CCI400_OFFSET is introduced in Kconfig

Signed-off-by Ashish Kumar <[email protected]>

---
v3:
This is v3 for https://patchwork.ozlabs.org/patch/731464/

 scripts/config_whitelist.txt | 1 -
 1 file changed, 1 deletion(-)

scripts/config_whitelist.txt +0 -1

index e261d02..c29f8f3 100644
@@ -2516,7 +2516,6 @@ CONFIG_SYS_CACHE_STASHING
 CONFIG_SYS_CADMUS_BASE_REG
 CONFIG_SYS_CBSIZE
 CONFIG_SYS_CCCR
-CONFIG_SYS_CCI400_ADDR
 CONFIG_SYS_CCSRBAR
 CONFIG_SYS_CCSRBAR_PHYS
 CONFIG_SYS_CCSRBAR_PHYS_HIGH

Signature · 1 line

2.7.4