Add Intel Arria 10 SoC FPGA driver

From: Tien Fong Chee <[email protected]>

This is the 12th version of patchset to adds support for Intel Arria 10 SoC FPGA driver. This version mainly resolved comments from Marek in [v11]. This series is working on top of u-boot-socfpga.git - http://git.denx.de/u-boot-socfpga.git

[v11]: https://www.mail-archive.com/u-boot at lists.denx.de/msg255643.html

v11 -> v12 changes:
-----------------
- Changed the commit messages of patch 5.
- Separate patch for defconfig, header changes and minor code clean up.

Patchset history
----------------
[v1]: https://www.mail-archive.com/u-boot at lists.denx.de/msg247788.html [v2]: https://www.mail-archive.com/u-boot at lists.denx.de/msg248541.html [v3]: https://www.mail-archive.com/u-boot at lists.denx.de/msg249160.html [v4]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250149.html [v5]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250517.html [v6]: https://www.mail-archive.com/u-boot at lists.denx.de/msg250687.html [v7]: https://www.mail-archive.com/u-boot at lists.denx.de/msg251213.html [v8]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252196.html [v9]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252422.html [v10]: https://www.mail-archive.com/u-boot at lists.denx.de/msg252583.html

Tien Fong Chee (8):
arm: socfpga: Remove unused passing parameter of socfpga_bridges_reset
arm: socfpga: Restructure FPGA driver in the preparation to support

    A10

kconfig: Convert FPGA and FPGA_ALTERA configuration to Kconfig
kconfig: Convert FPGA_SOCFPGA configuration to Kconfig
drivers: Enable FPGA driver build on SPL
configs: Add FPGA driver config for Arria 10
arm: socfpga: Add FPGA driver support for Arria 10
arm: socfpga: Enable all FPGA config support for Arria 10

 arch/arm/mach-socfpga/Makefile                     |   2 +-
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  70 +--
 .../include/mach/fpga_manager_arria10.h            | 100 +++++
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 ++-
 .../include/mach/reset_manager_arria10.h           |   2 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c      |   4 +-
 configs/astro_mcf5373l_defconfig                   |   1 +
 configs/socfpga_arria10_defconfig                  |   2 +
 configs/socfpga_arria5_defconfig                   |   1 +
 configs/socfpga_cyclone5_defconfig                 |   1 +
 configs/socfpga_de0_nano_soc_defconfig             |   1 +
 configs/socfpga_de10_nano_defconfig                |   1 +
 configs/socfpga_de1_soc_defconfig                  |   1 +
 configs/socfpga_is1_defconfig                      |   1 +
 configs/socfpga_mcvevk_defconfig                   |   1 +
 configs/socfpga_sockit_defconfig                   |   1 +
 configs/socfpga_socrates_defconfig                 |   1 +
 configs/socfpga_sr1500_defconfig                   |   1 +
 configs/socfpga_vining_fpga_defconfig              |   1 +
 configs/theadorable_debug_defconfig                |   1 +
 configs/theadorable_defconfig                      |   1 +
 drivers/Makefile                                   |   1 +
 drivers/fpga/Kconfig                               |   8 +
 drivers/fpga/Makefile                              |   2 +
 drivers/fpga/socfpga.c                             | 235 +---------
 drivers/fpga/socfpga_arria10.c                     | 479 +++++++++++++++++++++
 drivers/fpga/{socfpga.c => socfpga_gen5.c}         |  54 +--
 include/configs/astro_mcf5373l.h                   |   2 -
 include/configs/socfpga_common.h                   |   6 +-
 include/configs/theadorable.h                      |   2 -
 30 files changed, 658 insertions(+), 394 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
 create mode 100644 drivers/fpga/socfpga_arria10.c
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)

2.2.0

From: Tien Fong Chee <[email protected]>

Remove parameter from socfpga_bridges_reset(), and keeping this function for single purpose which is just triggering reset on bridges. socfpga_reset_deassert_bridges_handoff() can be called for releasing reset on any bridges based on the bridge setting defined in fdt.

---
 arch/arm/mach-socfpga/include/mach/reset_manager_arria10.h | 2 +-
 arch/arm/mach-socfpga/reset_manager_arria10.c              | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

index 7922db8..b6d7f4f 100644
@@ -17,7 +17,7 @@ int socfpga_reset_deassert_bridges_handoff(void);
 void socfpga_reset_assert_fpga_connected_peripherals(void);
 void socfpga_reset_deassert_osc1wd0(void);
 void socfpga_reset_uart(int assert);
-int socfpga_bridges_reset(int enable);
+int socfpga_bridges_reset(void);
 
 struct socfpga_reset_manager {
 	u32	stat;

index d8c858c..66f1ec2 100644
@@ -318,13 +318,13 @@ void socfpga_per_reset_all(void)
 }
 
 #if defined(CONFIG_SOCFPGA_VIRTUAL_TARGET)
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
 {
 	/* For SoCFPGA-VT, this is NOP. */
 	return 0;
 }
 #else
-int socfpga_bridges_reset(int enable)
+int socfpga_bridges_reset(void)
 {
 	int ret;
 

2.2.0

From: Tien Fong Chee <[email protected]>

Move FPGA driver which is Gen5 specific code into Gen5 driver file and keeping common FPGA driver intact. All the changes are still keeping in driver/fpga/ and no functional change. Subsequent patch would move FPGA manager driver from arch/arm into driver/fpga/.

---
 arch/arm/mach-socfpga/Makefile                     |   2 +-
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |  68 ++----
 .../mach/{fpga_manager.h => fpga_manager_gen5.h}   |  69 +++---
 drivers/fpga/Makefile                              |   1 +
 drivers/fpga/socfpga.c                             | 235 +--------------------
 drivers/fpga/{socfpga.c => socfpga_gen5.c}         |  54 +----
 6 files changed, 47 insertions(+), 382 deletions(-)
 copy arch/arm/mach-socfpga/include/mach/{fpga_manager.h => fpga_manager_gen5.h} (57%)
 copy drivers/fpga/{socfpga.c => socfpga_gen5.c} (83%)

index 41b779c..286bfef 100644
@@ -9,7 +9,6 @@
 
 obj-y	+= board.o
 obj-y	+= clock_manager.o
-obj-y	+= fpga_manager.o
 obj-y	+= misc.o
 obj-y	+= reset_manager.o
 obj-y	+= timer.o

@@ -21,6 +20,7 @@ obj-y	+= reset_manager_gen5.o
 obj-y	+= scan_manager.o
 obj-y	+= system_manager_gen5.o
 obj-y	+= wrap_pll_config.o
+obj-y	+= fpga_manager.o
 endif
 
 ifdef CONFIG_TARGET_SOCFPGA_ARRIA10

index 777706f..b65e5ba 100644
@@ -20,4 +20,5 @@ obj-$(CONFIG_FPGA_CYCLON2) += cyclon2.o
 obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
 obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
 obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
+obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
 endif

2.2.0

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
CONFIG_FPGA
CONFIG_FPGA_ALTERA

---
 configs/astro_mcf5373l_defconfig    | 1 +
 configs/theadorable_debug_defconfig | 1 +
 configs/theadorable_defconfig       | 1 +
 include/configs/astro_mcf5373l.h    | 2 --
 include/configs/theadorable.h       | 2 --
 5 files changed, 3 insertions(+), 4 deletions(-)

index d5e8430..80fb1fa 100644
@@ -10,4 +10,5 @@ CONFIG_CMD_I2C=y
 # CONFIG_CMD_NFS is not set
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_DATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_MTD_NOR_FLASH=y

index 2164237..e07b7b6 100644
@@ -43,6 +43,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

index d5eef70..3d2977c 100644
@@ -37,6 +37,7 @@ CONFIG_EFI_PARTITION=y
 # CONFIG_PARTITION_UUIDS is not set
 # CONFIG_SPL_PARTITION_UUIDS is not set
 CONFIG_SPL_OF_TRANSLATE=y
+CONFIG_FPGA_ALTERA=y
 CONFIG_DM_GPIO=y
 # CONFIG_MMC is not set
 CONFIG_SPI_FLASH=y

index 8899579..f4acea1 100644
@@ -201,10 +201,8 @@
 #define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
 
 #define CONFIG_FPGA_COUNT	1
-#define CONFIG_FPGA
 #define	CONFIG_FPGA_XILINX
 #define	CONFIG_FPGA_SPARTAN3
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_CYCLON2
 #define CONFIG_SYS_FPGA_PROG_FEEDBACK
 #define CONFIG_SYS_FPGA_WAIT		1000

index 2a671e8..5459f4f 100644
@@ -89,8 +89,6 @@
 #define CONFIG_SYS_MEM_TOP_HIDE		0x80000
 
 /* FPGA programming support */
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
 #define CONFIG_FPGA_STRATIX_V
 
 /*

2.2.0

From: Tien Fong Chee <[email protected]>

This converts the following to Kconfig:
CONFIG_FPGA_SOCFPGA

---
 configs/socfpga_arria5_defconfig       | 1 +
 configs/socfpga_cyclone5_defconfig     | 1 +
 configs/socfpga_de0_nano_soc_defconfig | 1 +
 configs/socfpga_de10_nano_defconfig    | 1 +
 configs/socfpga_de1_soc_defconfig      | 1 +
 configs/socfpga_is1_defconfig          | 1 +
 configs/socfpga_mcvevk_defconfig       | 1 +
 configs/socfpga_sockit_defconfig       | 1 +
 configs/socfpga_socrates_defconfig     | 1 +
 configs/socfpga_sr1500_defconfig       | 1 +
 configs/socfpga_vining_fpga_defconfig  | 1 +
 drivers/fpga/Kconfig                   | 8 ++++++++
 include/configs/socfpga_common.h       | 3 ---
 13 files changed, 19 insertions(+), 3 deletions(-)

index a565384..6f2a06f 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

index 06fc82c..1047657 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

index 0697e2e..72a9e5d 100644
@@ -39,6 +39,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

index cd64fb9..67864cf 100644
@@ -37,6 +37,7 @@ CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

index bba90be..35c4484 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_EXT4_WRITE=y
 CONFIG_CMD_FAT=y
 CONFIG_CMD_FS_GENERIC=y
 CONFIG_SPL_DM=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

index 058791e..ae688f8 100644
@@ -34,6 +34,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

index 627b90f..c5e3b7b 100644
@@ -38,6 +38,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

index bf5d63d..3ff7bb7 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

index 5915faf..fb9c13f 100644
@@ -41,6 +41,7 @@ CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

index 4468d3b..d90d6a1 100644
@@ -40,6 +40,7 @@ CONFIG_CMD_FS_GENERIC=y
 CONFIG_CMD_UBI=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_SYS_I2C_DW=y

index fb9bae4..c3fbe40 100644
@@ -44,6 +44,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_LED_STATUS=y

index a760944..6b2c866 100644
@@ -13,6 +13,14 @@ config FPGA_ALTERA
 	  Enable Altera FPGA specific functions which includes bitstream
 	  (in BIT format), fpga and device validation.
 
+config FPGA_SOCFPGA
+	bool "Enable Gen5 and Arria10 common FPGA drivers"
+	select FPGA_ALTERA
+	help
+	  Say Y here to enable the Gen5 and Arria10 common FPGA driver
+
+	  This provides common functionality for Gen5 and Arria10 devices.
+
 config FPGA_CYCLON2
 	bool "Enable Altera FPGA driver for Cyclone II"
 	depends on FPGA_ALTERA

index da7e4ad..1b79c03 100644
@@ -107,9 +107,6 @@
  */
 #ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_CMD_FPGA
-#define CONFIG_FPGA
-#define CONFIG_FPGA_ALTERA
-#define CONFIG_FPGA_SOCFPGA
 #define CONFIG_FPGA_COUNT		1
 #endif
 #endif

2.2.0

From: Tien Fong Chee <[email protected]>

Enable FPGA driver build for Arria 10 SPL because FPGA driver is needed by Arria 10 SPL to configure and getting DDR up before loading U-boot into DDR and booting from there.

---
 drivers/Makefile | 1 +
 1 file changed, 1 insertion(+)

index 64c39d3..4478212 100644
@@ -48,6 +48,7 @@ obj-$(CONFIG_OMAP_USB_PHY) += usb/phy/
 obj-$(CONFIG_SPL_SATA_SUPPORT) += block/
 obj-$(CONFIG_SPL_USB_HOST_SUPPORT) += block/
 obj-$(CONFIG_SPL_MMC_SUPPORT) += block/
+obj-$(CONFIG_SPL_FPGA_SUPPORT) += fpga/
 endif
 
 ifdef CONFIG_TPL_BUILD

2.2.0

From: Tien Fong Chee <[email protected]>

Add FPGA driver config for Arria 10.

---
 configs/socfpga_arria10_defconfig | 2 ++
 1 file changed, 2 insertions(+)

index 46bda47..53ab66f 100644
@@ -6,6 +6,7 @@ CONFIG_IDENT_STRING="socfpga_arria10"
 CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc"
 CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb"
 CONFIG_SPL=y
+CONFIG_SPL_FPGA_SUPPORT=y
 CONFIG_CMD_BOOTZ=y
 # CONFIG_CMD_IMLS is not set
 CONFIG_CMD_ASKENV=y

@@ -22,6 +23,7 @@ CONFIG_DOS_PARTITION=y
 # CONFIG_SPL_DOS_PARTITION is not set
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_FPGA_SOCFPGA=y
 CONFIG_DM_GPIO=y
 CONFIG_DWAPB_GPIO=y
 CONFIG_DM_MMC=y

2.2.0

From: Tien Fong Chee <[email protected]>

Add FPGA driver support for Arria 10.

---
 arch/arm/mach-socfpga/include/mach/fpga_manager.h  |   2 +
 .../include/mach/fpga_manager_arria10.h            | 100 +++++
 drivers/fpga/Makefile                              |   1 +
 drivers/fpga/socfpga_arria10.c                     | 479 +++++++++++++++++++++
 4 files changed, 582 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
 create mode 100644 drivers/fpga/socfpga_arria10.c

index b046c2c..a21c716 100644
@@ -12,6 +12,8 @@
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
 #include <asm/arch/fpga_manager_gen5.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#include <asm/arch/fpga_manager_arria10.h>
 #endif
 
 /* FPGA CD Ratio Value */

index b65e5ba..08c9ff8 100644
@@ -21,4 +21,5 @@ obj-$(CONFIG_FPGA_STRATIX_II) += stratixII.o
 obj-$(CONFIG_FPGA_STRATIX_V) += stratixv.o
 obj-$(CONFIG_FPGA_SOCFPGA) += socfpga.o
 obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += socfpga_gen5.o
+obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += socfpga_arria10.o
 endif

2.2.0

From: Tien Fong Chee <[email protected]>

Enable all FPGA config support for Arria 10.

---
 include/configs/socfpga_common.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

index 1b79c03..edd973a 100644
@@ -105,11 +105,10 @@
 /*
  * FPGA Driver
  */
-#ifdef CONFIG_TARGET_SOCFPGA_GEN5
 #ifdef CONFIG_CMD_FPGA
 #define CONFIG_FPGA_COUNT		1
 #endif
-#endif
+
 /*
  * L4 OSC1 Timer 0
  */

2.2.0

Sigh, this no longer applies on top of u-boot/master ; can you rebase and repost please ? I also updated u-boot-socfpga/master to match that.

Best regards,
Marek Vasut

Sure. So repost with same version 12?

Thanks.

That'd be v13 ...

Best regards,
Marek Vasut

Okay, i repost again.