thermal: imx: Add nvmem-cells binding on imx6sx
Subsystems (4)
v2 cover thermal: imx: Add nvmem-cells binding on imx6sx
On imx6sx accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first. Fix this by adding a nvmem-cells binding and using it on imx6sx, imx6ul and imx6ull.
The existing binding is kept around because it works fine on imx6qdl.
This was initially reported by Lothar Waßmann <[email protected]> in reply to a patch adding imx6ul/ull support:
---
Changes since v1:
* Move nvmem_cell_read_u32 to nvmem core (Shawn Guo, Srinivas Kandagatla)
* Adjust binding description (Rob Herring)
* Adjust formatting of thermal info cells (Shawn Guo)
* Link: https://lkml.org/lkml/2017/7/6/426
Leonard Crestez (5):
thermal: imx: Add nvmem-cells alternate binding for OCOTP access
nvmem: core: Add nvmem_cell_read_u32
thermal: imx: Add support for reading OCOTP through nvmem
ARM: dts: imx6sx: Use nvmem-cells for tempmon
ARM: dts: imx6ul: Add imx6ul-tempmon
.../devicetree/bindings/thermal/imx-thermal.txt | 7 ++ arch/arm/boot/dts/imx6sx.dtsi | 13 ++- arch/arm/boot/dts/imx6ul.dtsi | 19 ++++ drivers/nvmem/core.c | 37 ++++++++ drivers/thermal/imx_thermal.c | 103 +++++++++++++++------ include/linux/nvmem-consumer.h | 8 ++ 6 files changed, 156 insertions(+), 31 deletions(-)
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PATCH v2 1/5 thermal: imx: Add nvmem-cells alternate binding for OCOTP access
On newer imx SOCs accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first. Add a binding for accessing the same values through the imx-ocotp nvmem driver using nvmem-cells. This is similar to other thermal drivers.
The old binding is preserved for compatibility and because it still works fine on imx6qdl series chips.
In theory this problem could be solved by adding a reference to the OCOTP clock instead but it is better to hide such details in a specific nvmem driver.
--- Documentation/devicetree/bindings/thermal/imx-thermal.txt | 7 +++++++ 1 file changed, 7 insertions(+)
Documentation/devicetree/bindings/thermal/imx-thermal.txt +7 -0
@@ -7,10 +7,17 @@ Required properties: is higher than panic threshold, system will auto reboot by SRC module. - fsl,tempmon : phandle pointer to system controller that contains TEMPMON control registers, e.g. ANATOP on imx6q. +- nvmem-cells: A phandle to the calibration cells provided by ocotp. +- nvmem-cell-names: Should be "calib", "temp_grade". + +Deprecated properties: - fsl,tempmon-data : phandle pointer to fuse controller that contains TEMPMON calibration data, e.g. OCOTP on imx6q. The details about calibration data can be found in SoC Reference Manual. +Direct access to OCOTP via fsl,tempmon-data is incorrect on some newer chips +because it does not handle OCOTP clock requirements. + Optional properties: - clocks : thermal sensor's clock source.
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Re: [PATCH v2 1/5] thermal: imx: Add nvmem-cells alternate binding for OCOTP access
Quoted 8 lines · Leonard Crestez
On newer imx SOCs accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first. Add a binding for accessing the same values through the imx-ocotp nvmem driver using nvmem-cells. This is similar to other thermal drivers.
The old binding is preserved for compatibility and because it still works fine on imx6qdl series chips.
Quoted 8 lines
In theory this problem could be solved by adding a reference to the OCOTP clock instead but it is better to hide such details in a specific nvmem driver.
Signed-off-by Leonard Crestez <[email protected]>--- Documentation/devicetree/bindings/thermal/imx-thermal.txt | 7 +++++++ 1 file changed, 7 insertions(+)
PATCH v2 2/5 nvmem: core: Add nvmem_cell_read_u32
In reply to Leonard CrestezThis function does a quick and easy read of an u32 value without any kind of resource management code on the consumer side.
--- drivers/nvmem/core.c | 37 +++++++++++++++++++++++++++++++++++++ include/linux/nvmem-consumer.h | 8 ++++++++ 2 files changed, 45 insertions(+)
drivers/nvmem/core.c +37 -0
@@ -1111,6 +1111,43 @@ int nvmem_cell_write(struct nvmem_cell *cell, void *buf, size_t len)EXPORT_SYMBOL_GPL (nvmem_cell_write);/** +* nvmem_cell_read_u32() - Read a cell value as an u32 +* +* @dev: Device that requests the nvmem cell. +* @cell_id: Name of nvmem cell to read. +* @val: pointer to output value. +* +* Return: 0 on success or negative errno. +*/ +int nvmem_cell_read_u32 (struct device * dev,const char *cell_id,u32 *val) +{ +struct nvmem_cell *cell; +void *buf; +size_t len; + + cell =nvmem_cell_get (dev, cell_id); +if (IS_ERR (cell)) +return PTR_ERR (cell); + + buf =nvmem_cell_read (cell, &len); +if (IS_ERR (buf)) { +nvmem_cell_put (cell); +return PTR_ERR (buf); + } +if (len !=sizeof (*val)) { +kfree (buf); +nvmem_cell_put (cell); +return -EINVAL ; + } +memcpy (val, buf,sizeof (*val)); + +kfree (buf); +nvmem_cell_put (cell); +return 0 ; +} +EXPORT_SYMBOL_GPL (nvmem_cell_read_u32); + +/** * nvmem_device_cell_read() - Read a given nvmem device and cell * * @nvmem: nvmem device to read from.
include/linux/nvmem-consumer.h +8 -0
@@ -36,6 +36,8 @@ void devm_nvmem_cell_put(struct device *dev, struct nvmem_cell *cell);void *nvmem_cell_read (struct nvmem_cell *cell,size_t *len);int nvmem_cell_write (struct nvmem_cell *cell,void *buf,size_t len); +int nvmem_cell_read_u32 (struct device * dev,const char *cell_id,u32 *val); +/* direct nvmem device read/write interface */ struct nvmem_device *nvmem_device_get (struct device *dev,const char *name); struct nvmem_device *devm_nvmem_device_get(struct device *dev,
@@ -85,6 +87,12 @@ static inline int nvmem_cell_write(struct nvmem_cell *cell,return -ENOSYS ; } +static inline int nvmem_cell_read_u32 (struct device * dev, +const char *cell_id,u32 *val) +{ +return -ENOSYS ; +} +static inline struct nvmem_device *nvmem_device_get (struct device *dev,const char *name) {
Signature · 1 line
2.7.4
Re: [PATCH v2 2/5] nvmem: core: Add nvmem_cell_read_u32
Quoted 4 lines · Leonard Crestez
This function does a quick and easy read of an u32 value without any kind of resource management code on the consumer side.
Signed-off-by Leonard Crestez <[email protected]>
Re: [PATCH v2 2/5] nvmem: core: Add nvmem_cell_read_u32
In reply to Leonard CrestezQuoted 5 lines · Leonard Crestez
This function does a quick and easy read of an u32 value without any kind of resource management code on the consumer side.
Signed-off-by Leonard Crestez <[email protected]>---
Sorry about the long delay, I was expecting this patch to go via Greg KH tree to an rc, which seems to be very late now, so here is my Ack so that you could pick this patch from other tree along with this series.
I will resend my fixes to Greg without this patch.
Quoted 69 lines
drivers/nvmem/core.c | 37 +++++++++++++++++++++++++++++++++++++ include/linux/nvmem-consumer.h | 8 ++++++++ 2 files changed, 45 insertions(+)drivers/nvmem/core.c +37
-0@@ -1111,6 +1111,43 @@ int nvmem_cell_write(struct nvmem_cell *cell, void *buf, size_t len)EXPORT_SYMBOL_GPL (nvmem_cell_write);/** +* nvmem_cell_read_u32() - Read a cell value as an u32 +* +* @dev: Device that requests the nvmem cell. +* @cell_id: Name of nvmem cell to read. +* @val: pointer to output value. +* +* Return: 0 on success or negative errno. +*/ +int nvmem_cell_read_u32 (struct device * dev,const char *cell_id,u32 *val) +{ +struct nvmem_cell *cell; +void *buf; +size_t len; + + cell =nvmem_cell_get (dev, cell_id); +if (IS_ERR (cell)) +return PTR_ERR (cell); + + buf =nvmem_cell_read (cell, &len); +if (IS_ERR (buf)) { +nvmem_cell_put (cell); +return PTR_ERR (buf); + } +if (len !=sizeof (*val)) { +kfree (buf); +nvmem_cell_put (cell); +return -EINVAL ; + } +memcpy (val, buf,sizeof (*val)); + +kfree (buf); +nvmem_cell_put (cell); +return 0 ; +} +EXPORT_SYMBOL_GPL (nvmem_cell_read_u32); + +/** * nvmem_device_cell_read() - Read a given nvmem device and cell * * @nvmem: nvmem device to read from. include/linux/nvmem-consumer.h +2
-0@@ -36,6 +36,8 @@ void devm_nvmem_cell_put(struct device *dev, struct nvmem_cell *cell);void *nvmem_cell_read (struct nvmem_cell *cell,size_t *len);int nvmem_cell_write (struct nvmem_cell *cell,void *buf,size_t len); +int nvmem_cell_read_u32 (struct device * dev,const char *cell_id,u32 *val); +/* direct nvmem device read/write interface */ struct nvmem_device *nvmem_device_get (struct device *dev,const char *name); struct nvmem_device *devm_nvmem_device_get(struct device *dev,@@ -85,6 +87,12 @@ static inline int nvmem_cell_write(struct nvmem_cell *cell,return -ENOSYS ; }
include/linux/nvmem-consumer.h static inline int nvmem_cell_write(struct nvmem_cell *cell, · line 98
Quoted 10 lines
include/linux/nvmem-consumer.h +6
-0+static inline int nvmem_cell_read_u32 (struct device * dev, +const char *cell_id,u32 *val) +{ +return -ENOSYS ; +} +static inline struct nvmem_device *nvmem_device_get (struct device *dev,const char *name) {
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Re: [PATCH v2 2/5] nvmem: core: Add nvmem_cell_read_u32
Quoted 5 lines · Srinivas Kandagatla
Quoted 4 lines · Leonard Crestez
This function does a quick and easy read of an u32 value without any kind of resource management code on the consumer side.
Quoted 8 lines
Quoted 2 lines
Signed-off-by Leonard Crestez <[email protected]>---
Sorry about the long delay, I was expecting this patch to go via Greg KH tree to an rc, which seems to be very late now, so here is my Ack so that you could pick this patch from other tree along with this series.
I will resend my fixes to Greg without this patch.
Ok. Should I resend my series? It's been a while since it was first posted.
PATCH v2 3/5 thermal: imx: Add support for reading OCOTP through nvmem
In reply to Leonard CrestezOn newer imx SOCs accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first. Add support for reading those same values through the nvmem API instead.
The older path is preserved for compatibility with older dts and because it works correctly on imx6qdl chips.
--- drivers/thermal/imx_thermal.c | 103 ++++++++++++++++++++++++++++++------------ 1 file changed, 73 insertions(+), 30 deletions(-)
drivers/thermal/imx_thermal.c +73 -30
@@ -24,6 +24,7 @@#include <linux/slab.h> #include <linux/thermal.h> #include <linux/types.h> +#include <linux/nvmem-consumer.h> #define REG_SET 0x4#define REG_CLR 0x8
@@ -92,7 +93,7 @@ struct imx_thermal_data {struct thermal_cooling_device *cdev;enum thermal_device_mode mode;struct regmap *tempmon; -u32 c1, c2;/* See formula in imx_get_sensor_data() */ +u32 c1, c2;/* See formula in imx_init_calib() */ int temp_passive;int temp_critical;int temp_max;
@@ -175,7 +176,7 @@ static int imx_get_temp(struct thermal_zone_device *tz, int *temp) n_meas = (val &TEMPSENSE0_TEMP_CNT_MASK ) >>TEMPSENSE0_TEMP_CNT_SHIFT ; -/* See imx_get_sensor_data() for formula derivation */ +/* See imx_init_calib() for formula derivation */ *temp = data->c2 - n_meas * data->c1;/* Update alarm value to next higher trip point for TEMPMON_IMX6Q */
@@ -344,29 +345,12 @@ static struct thermal_zone_device_ops imx_tz_ops = { .set_trip_temp = imx_set_trip_temp, }; -static int imx_get_sensor_data (struct platform_device *pdev) +static int imx_init_calib (struct platform_device *pdev,u32 val) {struct imx_thermal_data *data =platform_get_drvdata (pdev); -struct regmap *map;int t1, n1; -int ret; -u32 val;u64 temp64; - map =syscon_regmap_lookup_by_phandle (pdev->dev.of_node, -"fsl,tempmon-data" ); -if (IS_ERR (map)) { - ret =PTR_ERR (map); -dev_err (&pdev->dev,"failed to get sensor regmap: %d\n" , ret); -return ret; - } - - ret =regmap_read (map,OCOTP_ANA1 , &val); -if (ret) { -dev_err (&pdev->dev,"failed to read sensor data: %d\n" , ret); -return ret; - } -if (val ==0 || val == ~0 ) {dev_err (&pdev->dev,"invalid sensor calibration data\n" );return -EINVAL ;
@@ -403,12 +387,12 @@ static int imx_get_sensor_data(struct platform_device *pdev) data->c1 = temp64; data->c2 = n1 * data->c1 +1000 * t1; -/* use OTP for thermal grade */ - ret =regmap_read (map,OCOTP_MEM0 , &val); -if (ret) { -dev_err (&pdev->dev,"failed to read temp grade: %d\n" , ret); -return ret; - } +return 0 ; +} + +static void imx_init_temp_grade (struct platform_device *pdev,u32 val) +{ +struct imx_thermal_data *data =platform_get_drvdata (pdev);/* The maximum die temp is specified by the Temperature Grade */ switch ((val >>6 ) &0x3 ) {
@@ -436,6 +420,55 @@ static int imx_get_sensor_data(struct platform_device *pdev)*/ data->temp_critical = data->temp_max - (1000 *5 ); data->temp_passive = data->temp_max - (1000 *10 ); +} + +static int imx_init_from_tempmon_data (struct platform_device *pdev) +{ +struct regmap *map; +int ret; +u32 val; + + map =syscon_regmap_lookup_by_phandle (pdev->dev.of_node, +"fsl,tempmon-data" ); +if (IS_ERR (map)) { + ret =PTR_ERR (map); +dev_err (&pdev->dev,"failed to get sensor regmap: %d\n" , ret); +return ret; + } + + ret =regmap_read (map,OCOTP_ANA1 , &val); +if (ret) { +dev_err (&pdev->dev,"failed to read sensor data: %d\n" , ret); +return ret; + } + ret =imx_init_calib (pdev, val); +if (ret) +return ret; + + ret =regmap_read (map,OCOTP_MEM0 , &val); +if (ret) { +dev_err (&pdev->dev,"failed to read sensor data: %d\n" , ret); +return ret; + } +imx_init_temp_grade (pdev, val); + +return 0 ; +} + +static int imx_init_from_nvmem_cells (struct platform_device *pdev) +{ +int ret; +u32 val; + + ret =nvmem_cell_read_u32 (&pdev->dev,"calib" , &val); +if (ret) +return ret; +imx_init_calib (pdev, val); + + ret =nvmem_cell_read_u32 (&pdev->dev,"temp_grade" , &val); +if (ret) +return ret; +imx_init_temp_grade (pdev, val);return 0 ; }
@@ -512,10 +545,20 @@ static int imx_thermal_probe(struct platform_device *pdev)platform_set_drvdata (pdev, data); - ret =imx_get_sensor_data (pdev); -if (ret) { -dev_err (&pdev->dev,"failed to get sensor data\n" ); -return ret; +if (of_find_property (pdev->dev.of_node,"nvmem-cells" ,NULL )) { + ret =imx_init_from_nvmem_cells (pdev); +if (ret == -EPROBE_DEFER ) +return ret; +if (ret) { +dev_err (&pdev->dev,"failed to init from nvmem: %d\n" , ret); +return ret; + } + }else { + ret =imx_init_from_tempmon_data (pdev); +if (ret) { +dev_err (&pdev->dev,"failed to init from from fsl,tempmon-data\n" ); +return ret; + } }/* Make sure sensor is in known good state for measurements */
Signature · 1 line
2.7.4
Re: [PATCH v2 3/5] thermal: imx: Add support for reading OCOTP through nvmem
Quoted 8 lines · Leonard Crestez
On newer imx SOCs accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first. Add support for reading those same values through the nvmem API instead.
The older path is preserved for compatibility with older dts and because it works correctly on imx6qdl chips.
Signed-off-by Leonard Crestez <[email protected]>
Zhang Rui
reviewerRe: [PATCH v2 3/5] thermal: imx: Add support for reading OCOTP through nvmem
Quoted 8 lines · Shawn Guo
Quoted 7 lines · Leonard Crestez
On newer imx SOCs accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first. Add support for reading those same values through
the nvmem API instead.
Quoted 6 lines
Quoted 5 lines
The older path is preserved for compatibility with older dts and because it
works correctly on imx6qdl chips.Signed-off-by Leonard Crestez <[email protected]>Acked-by Shawn Guo <[email protected]>
I'm okay with the thermal change.
We still need ACK for the nvmem changes in this patch series.
thanks,
rui
Re: [PATCH v2 3/5] thermal: imx: Add support for reading OCOTP through nvmem
Quoted 13 lines · Zhang Rui
Quoted 12 lines · Shawn Guo
Quoted 11 lines · Leonard Crestez
On newer imx SOCs accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first. Add support for reading those same values through
the nvmem API instead.The older path is preserved for compatibility with older dts and because it
works correctly on imx6qdl chips.
Quoted 5 lines
Quoted 2 lines
Quoted 1 line
Signed-off-by Leonard Crestez <[email protected]>Acked-by Shawn Guo <[email protected]>I'm okay with the thermal change.
We still need ACK for the nvmem changes in this patch series.
NVMEM changes are already sent to Greg K H with other patches (https://lkml.org/lkml/2017/7/26/164), should appear in next.
Quoted 4 lines
thanks,
rui
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Re: [PATCH v2 3/5] thermal: imx: Add support for reading OCOTP through nvmem
Quoted 14 lines · Srinivas Kandagatla
Quoted 13 lines · Zhang Rui
Quoted 12 lines · Shawn Guo
Quoted 10 lines · Leonard Crestez
On newer imx SOCs accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first. Add support for reading those same values through
the nvmem API instead.The older path is preserved for compatibility with older dts and because it
works correctly on imx6qdl chips.
Quoted 8 lines
Quoted 5 lines
Quoted 2 lines
Quoted 1 line
Signed-off-by Leonard Crestez <[email protected]>Acked-by Shawn Guo <[email protected]>I'm okay with the thermal change.
We still need ACK for the nvmem changes in this patch series.NVMEM changes are already sent to Greg K H with other patches
(https://lkml.org/lkml/2017/7/26/164), should appear in next.
These patches have a compile-time dependency on each other. Wouldn't it make more sense for the whole series to go through a single maintainer tree, atomically? Most of the changes are in driver/thermal.
I'm really very confused about how series that touch multiple areas are applied. It seems to be a mostly ad-hoc process.
--
Regards,
Leonard
Re: [PATCH v2 3/5] thermal: imx: Add support for reading OCOTP through nvmem
Quoted 21 lines · Leonard Crestez
Quoted 19 lines · Srinivas Kandagatla
Quoted 18 lines · Zhang Rui
Quoted 8 lines · Shawn Guo
Quoted 6 lines · Leonard Crestez
On newer imx SOCs accessing OCOTP directly is wrong because the ocotp clock
needs to be enabled first. Add support for reading those same values through
the nvmem API instead.Quoted 6 lines
Quoted 5 lines
The older path is preserved for compatibility with older dts and because it
works correctly on imx6qdl chips.Signed-off-by Leonard Crestez <[email protected]>Acked-by Shawn Guo <[email protected]>I'm okay with the thermal change.
We still need ACK for the nvmem changes in this patch series.
Quoted 6 lines
Quoted 2 lines
NVMEM changes are already sent to Greg K H with other patches
(https://lkml.org/lkml/2017/7/26/164), should appear in next.These patches have a compile-time dependency on each other. Wouldn't it make more sense for the whole series to go through a single maintainer tree, atomically? Most of the changes are in driver/thermal.
I was expecting that the nvmem change go in as fix in a rc release so that you could apply the other patches after that.
Let me ping Greg about this!!
Quoted 8 lines
I'm really very confused about how series that touch multiple areas are applied. It seems to be a mostly ad-hoc process.
--
Regards,
Leonard
Zhang Rui
reviewerRe: [PATCH v2 3/5] thermal: imx: Add support for reading OCOTP through nvmem
Quoted 45 lines · Srinivas Kandagatla
Quoted 1 line
Quoted 33 lines · Leonard Crestez
Quoted 31 lines · Srinivas Kandagatla
Quoted 28 lines · Zhang Rui
Quoted 15 lines · Shawn Guo
Quoted 9 lines · Leonard Crestez
On newer imx SOCs accessing OCOTP directly is wrong because the
ocotp clock
needs to be enabled first. Add support for reading those same
values through
the nvmem API instead.Quoted 7 lines
Quoted 6 lines
The older path is preserved for compatibility with older dts and
because it
works correctly on imx6qdl chips.Signed-off-by Leonard Crestez <[email protected]>Acked-by Shawn Guo <[email protected]>I'm okay with the thermal change.
We still need ACK for the nvmem changes in this patch series.Quoted 7 lines
Quoted 2 lines
NVMEM changes are already sent to Greg K H with other patches
(https://lkml.org/lkml/2017/7/26/164), should appear in next.These patches have a compile-time dependency on each other. Wouldn't it
make more sense for the whole series to go through a single maintainer
tree, atomically? Most of the changes are in driver/thermal.
Quoted 5 lines
I was expecting that the nvmem change go in as fix in a rc release so
that you could apply the other patches after that.Let me ping Greg about this!!
As Shawn is okay with patch 4/5 and 5/5, I guess I can queue patch 1/5, 3/5, 4/5, 5/5 for 4.14-rc1, if the nvmem patch can catch 4.13, or I can queue the full patch set for 4.14, with Srinivas' ACK.
thanks,
rui
Quoted 9 lines
Quoted 9 lines
I'm really very confused about how series that touch multiple areas are
applied. It seems to be a mostly ad-hoc process.--
Regards,
Leonard
Re: [PATCH v2 3/5] thermal: imx: Add support for reading OCOTP through nvmem
Quoted 15 lines · Zhang Rui
Quoted 13 lines · Srinivas Kandagatla
Quoted 12 lines · Leonard Crestez
Quoted 7 lines · Srinivas Kandagatla
Quoted 2 lines · Zhang Rui
I'm okay with the thermal change.
We still need ACK for the nvmem changes in this patch series.NVMEM changes are already sent to Greg K H with other patches
https://lkml.org/lkml/2017/8/8/436, should appear in next.These patches have a compile-time dependency on each other. Wouldn't it make more sense for the whole series to go through a single maintainer tree, atomically? Most of the changes are in driver/thermal.
Quoted 8 lines
Quoted 4 lines
I was expecting that the nvmem change go in as fix in a rc release so that you could apply the other patches after that.
Let me ping Greg about this!!
As Shawn is okay with patch 4/5 and 5/5, I guess I can queue patch 1/5, 3/5, 4/5, 5/5 for 4.14-rc1, if the nvmem patch can catch 4.13, or I can queue the full patch set for 4.14, with Srinivas' ACK.
It's been a week since the last email and it seems that nothing happened. I can't find any of these patches in either torvalds/master or linux-next. It seems to me that the nvmem series linked above was not picked up after all?
It's not clear how to proceed. It's been more a month since the series was sent so maybe I should resend it but it's not clear who would pick it up.
--
Regards,
Leonard
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Zhang Rui
reviewerRe: [PATCH v2 3/5] thermal: imx: Add support for reading OCOTP through nvmem
Quoted 33 lines · Leonard Crestez
Quoted 32 lines · Zhang Rui
Quoted 30 lines · Srinivas Kandagatla
Quoted 26 lines · Leonard Crestez
Quoted 14 lines · Srinivas Kandagatla
Quoted 4 lines · Zhang Rui
I'm okay with the thermal change.
We still need ACK for the nvmem changes in this patch series.Quoted 2 lines
NVMEM changes are already sent to Greg K H with other patches
https://lkml.org/lkml/2017/8/8/436, should appear in next.These patches have a compile-time dependency on each other. Wouldn't it make more sense for the whole series to go through a single
maintainer tree, atomically? Most of the changes are in driver/thermal.
Quoted 6 lines
Quoted 6 lines
Quoted 5 lines
I was expecting that the nvmem change go in as fix in a rc release
so that you could apply the other patches after that.Let me ping Greg about this!!
Srinivas,
Will you take patch 2/5?
Only after that, we can push the other changes.
thanks,
rui
Quoted 19 lines
Quoted 5 lines
As Shawn is okay with patch 4/5 and 5/5, I guess I can queue patch 1/5,
3/5, 4/5, 5/5 for 4.14-rc1, if the nvmem patch can catch 4.13, or I can
queue the full patch set for 4.14, with Srinivas' ACK.It's been a week since the last email and it seems that nothing happened. I can't find any of these patches in either torvalds/master or linux-next. It seems to me that the nvmem series linked above was not picked up after all?
It's not clear how to proceed. It's been more a month since the series
was sent so maybe I should resend it but it's not clear who would pick
it up.--
Regards,
Leonard
PATCH v2 4/5 ARM: dts: imx6sx: Use nvmem-cells for tempmon
In reply to Leonard CrestezOn imx6sx accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first. Use the nvmem-cells binding instead.
This requirement does not apply to older imx6qdl chips because there the ocotp access clock (clk_ipg_s) is always enabled.
This is visible by comparing the "System Clocks, Gating, and Override" tables (OCOTP rows) in the 6DQ and 6SX manuals:
http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SXRM.pdf
http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6DQRM.pdf
This happens to work right now because the ocotp clock might be enabled for some other reason. In particular the it might be enabled from the bootloader and it only gets disabled late during boot in clk_disable_unused, after imx-thermal has completed probing.
If imx-thermal is compiled as a module then the system can hang on probe.
--- arch/arm/boot/dts/imx6sx.dtsi | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)
arch/arm/boot/dts/imx6sx.dtsi +12 -1
@@ -675,7 +675,8 @@ compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; };
@@ -993,9 +994,19 @@ }; ocotp: ocotp@021bc000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx6sx-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SX_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; sai1: sai@021d4000 {
Signature · 1 line
2.7.4
Re: [PATCH v2 4/5] ARM: dts: imx6sx: Use nvmem-cells for tempmon
Quoted 16 lines · Leonard Crestez
On imx6sx accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first. Use the nvmem-cells binding instead.
This requirement does not apply to older imx6qdl chips because there the ocotp access clock (
clk_ipg_s) is always enabled.This is visible by comparing the "System Clocks, Gating, and Override" tables (OCOTP rows) in the 6DQ and 6SX manuals:
http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SXRM.pdf
http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6DQRM.pdfThis happens to work right now because the ocotp clock might be enabled for some other reason. In particular the it might be enabled from the bootloader and it only gets disabled late during boot in
clk_disable_unused, after imx-thermal has completed probing.
Quoted 5 lines
If imx-thermal is compiled as a module then the system can hang on probe.
Reported-by Lothar Waßmann <[email protected]>Signed-off-by Leonard Crestez <[email protected]>
I cannot apply dts changes until the driver part gets landed on mainline. Please remind me when dts patches can be applied.
Shawn
Quoted 41 lines
--- arch/arm/boot/dts/imx6sx.dtsi | 13 ++++++++++++- 1 file changed, 12 insertions(+), 1 deletion(-)arch/arm/boot/dts/imx6sx.dtsi +12
-1@@ -675,7 +675,8 @@ compatible = "fsl,imx6sx-tempmon", "fsl,imx6q-tempmon"; interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; fsl,tempmon = <&anatop>; - fsl,tempmon-data = <&ocotp>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>; };@@ -993,9 +994,19 @@ }; ocotp: ocotp@021bc000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx6sx-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6SX_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; sai1: sai@021d4000 {Signature · 1 line
2.7.4
Re: [PATCH v2 4/5] ARM: dts: imx6sx: Use nvmem-cells for tempmon
In reply to Leonard CrestezQuoted 16 lines · Leonard Crestez
On imx6sx accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first. Use the nvmem-cells binding instead.
This requirement does not apply to older imx6qdl chips because there the ocotp access clock (
clk_ipg_s) is always enabled.This is visible by comparing the "System Clocks, Gating, and Override" tables (OCOTP rows) in the 6DQ and 6SX manuals:
http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6SXRM.pdf
http://www.nxp.com/assets/documents/data/en/reference-manuals/IMX6DQRM.pdfThis happens to work right now because the ocotp clock might be enabled for some other reason. In particular the it might be enabled from the bootloader and it only gets disabled late during boot in
clk_disable_unused, after imx-thermal has completed probing.
Quoted 5 lines
If imx-thermal is compiled as a module then the system can hang on probe.
Reported-by Lothar Waßmann <[email protected]>Signed-off-by Leonard Crestez <[email protected]>
I applied patch #4 and #5 to IMX tree for avoiding merge conflict. Rui will drop them from thermal tree.
Shawn
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PATCH v2 5/5 ARM: dts: imx6ul: Add imx6ul-tempmon
In reply to Leonard CrestezThis works identically to imx6sx-tempmon on both imx6ul and imx6ull. It just needs to be defined in dts.
--- arch/arm/boot/dts/imx6ul.dtsi | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
arch/arm/boot/dts/imx6ul.dtsi +19 -0
@@ -598,6 +598,15 @@ fsl,anatop = <&anatop>; }; + tempmon: tempmon { + compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + fsl,tempmon = <&anatop>; + nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; + nvmem-cell-names = "calib", "temp_grade"; + clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; + }; + snvs: snvs@020cc000 { compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; reg = <0x020cc000 0x4000>;
@@ -860,9 +869,19 @@ }; ocotp: ocotp-ctrl@021bc000 { + #address-cells = <1>; + #size-cells = <1>; compatible = "fsl,imx6ul-ocotp", "syscon"; reg = <0x021bc000 0x4000>; clocks = <&clks IMX6UL_CLK_OCOTP>; + + tempmon_calib: calib@38 { + reg = <0x38 4>; + }; + + tempmon_temp_grade: temp-grade@20 { + reg = <0x20 4>; + }; }; lcdif: lcdif@021c8000 {
Signature · 6 lines
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Hi,
Quoted 25 lines · On Fri, 14 Jul 2017 17:11:05 +0300 Leonard Crestez wrote:
On imx6sx accessing OCOTP directly is wrong because the ocotp clock needs to be enabled first. Fix this by adding a nvmem-cells binding and using it on imx6sx, imx6ul and imx6ull.
The existing binding is kept around because it works fine on imx6qdl.
This was initially reported by Lothar Waßmann <[email protected]> in reply to a patch adding imx6ul/ull support:
---
Changes since v1:
* Movenvmem_cell_read_u32to nvmem core (Shawn Guo, Srinivas Kandagatla)
* Adjust binding description (Rob Herring)
* Adjust formatting of thermal info cells (Shawn Guo)
* Link: https://lkml.org/lkml/2017/7/6/426Leonard Crestez (5):
thermal: imx: Add nvmem-cells alternate binding for OCOTP access
nvmem: core: Addnvmem_cell_read_u32
thermal: imx: Add support for reading OCOTP through nvmem
ARM: dts: imx6sx: Use nvmem-cells for tempmon
ARM: dts: imx6ul: Add imx6ul-tempmon
Quoted 8 lines
.../devicetree/bindings/thermal/imx-thermal.txt | 7 ++ arch/arm/boot/dts/imx6sx.dtsi | 13 ++- arch/arm/boot/dts/imx6ul.dtsi | 19 ++++ drivers/nvmem/core.c | 37 ++++++++ drivers/thermal/imx_thermal.c | 103 +++++++++++++++------ include/linux/nvmem-consumer.h | 8 ++ 6 files changed, 156 insertions(+), 31 deletions(-)
Works as expected on TX6UL-5010.
Lothar Waßmann
Quoted 6 lines · Leonard Crestez
Leonard Crestez (5):
thermal: imx: Add nvmem-cells alternate binding for OCOTP access
nvmem: core: Addnvmem_cell_read_u32
thermal: imx: Add support for reading OCOTP through nvmem
ARM: dts: imx6sx: Use nvmem-cells for tempmon
ARM: dts: imx6ul: Add imx6ul-tempmon
For last two dts patches,
Zhang Rui
reviewerQuoted 11 lines · Shawn Guo
Quoted 7 lines · Leonard Crestez
Leonard Crestez (5):
thermal: imx: Add nvmem-cells alternate binding for OCOTP access
nvmem: core: Addnvmem_cell_read_u32
thermal: imx: Add support for reading OCOTP through nvmem
ARM: dts: imx6sx: Use nvmem-cells for tempmon
ARM: dts: imx6ul: Add imx6ul-tempmonFor last two dts patches,
Acked-by Shawn Guo <[email protected]>
thanks.
I will push patch 1,3,4,5 after patch 2/5 merged.
-rui
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Zhang Rui
reviewerQuoted 12 lines · Zhang Rui
Quoted 11 lines · Shawn Guo
Quoted 9 lines · Leonard Crestez
Leonard Crestez (5):
thermal: imx: Add nvmem-cells alternate binding for OCOTP access
nvmem: core: Addnvmem_cell_read_u32
thermal: imx: Add support for reading OCOTP through nvmem
ARM: dts: imx6sx: Use nvmem-cells for tempmon
ARM: dts: imx6ul: Add imx6ul-tempmon
Quoted 6 lines
Quoted 3 lines
For last two dts patches,
Acked-by Shawn Guo <[email protected]>thanks.
I will push patch 1,3,4,5 after patch 2/5 merged.
sorry that this patch set didn't catch this merge window. I've rebased it on top of 4.14-rc1 and queued for 4.15.
thanks,
rui
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