Add platform support for Adaptrum Anarion SOC
Subsystems (2)
v3 cover Add platform support for Adaptrum Anarion SOC
Changes since v2:
* Changed compatible binding of uart[1-3] to "ns16550" (they are not DW UARTs)
* Add support under plat-nsim instead of creating a new stub platform
* Changed board model to "adaptrum,endor-fpga" to allow LEDE scripts to ID the board
* Prefix compatible binding with 'arc-'
Changes since v1:
* Updated CPU core clock to 24 MHz to match HW changes.
Alexandru Gagniuc (2):
ARC: [plat-sim] Add .compatible property for Adaptrum Anarion SOC
ARC: DTS: Add device-tree for Anarion-based development board
arch/arc/boot/dts/adaptrum_anarion.dtsi | 110 ++++++++++++++++++++++++++++ arch/arc/boot/dts/adaptrum_anarion_fpga.dts | 51 +++++++++++++ arch/arc/plat-sim/platform.c | 1 + 3 files changed, 162 insertions(+) create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi create mode 100644 arch/arc/boot/dts/adaptrum_anarion_fpga.dts
Signature · 1 line
2.9.3
PATCH v3 1/2 ARC: [plat-sim] Add .compatible property for Adaptrum Anarion SOC
Anarion does not require any special configuration during early boot. This is compatible with nsim, hence-why it is added here.
As development continues, should we need to add any drivers via Kconfig, we can do that by adding and sourcing a "Kconfig.anarion". This approach was chosen --as opposed to adding plat-anarion/-- because it doesn't add a bunch of extra files.
--- arch/arc/plat-sim/platform.c | 1 + 1 file changed, 1 insertion(+)
arch/arc/plat-sim/platform.c +1 -0
@@ -21,6 +21,7 @@static const char *simulation_compat[]__initconst = { #ifdef CONFIG_ISA_ARCOMPACT +"adaptrum,arc-anarion" ,"snps,nsim" ,"snps,nsimosci" , #else
Signature · 1 line
2.9.3
PATCH v3 2/2 ARC: DTS: Add device-tree for Anarion-based development board
In reply to Alexandru GagniucThis is split into the SOC bindings, and the board dts. The Endor board is currently an FPGA emulation. Once real, silicon arrives, we plan to remove Endor support.
--- arch/arc/boot/dts/adaptrum_anarion.dtsi | 110 ++++++++++++++++++++++++++++ arch/arc/boot/dts/adaptrum_anarion_fpga.dts | 51 +++++++++++++ 2 files changed, 161 insertions(+) create mode 100644 arch/arc/boot/dts/adaptrum_anarion.dtsi create mode 100644 arch/arc/boot/dts/adaptrum_anarion_fpga.dts
arch/arc/boot/dts/adaptrum_anarion.dtsi new file +110 -0
@@ -0,0 +1,110 @@ +/* + * Skeleton for Adaptrum Anarion SOC + * + * (C) Copyright 2017 Adaptrum, Inc. + * Written by Alexandru Gagniuc <alex.g at adaptrum.com> for Adaptrum, Inc. + * Licensed under the GPLv2 or (at your option) any later version + */ + +/* This skeleton is based on the ARC700 CPU */ +#include "skeleton.dtsi" + +/ { + compatible = "adaptrum,anarion"; + #address-cells = <1>; + #size-cells = <1>; + + soc { + compatible = "simple-bus"; + device_type = "soc"; + #address-cells = <1>; + #size-cells = <1>; + ranges; + interrupt-parent = <&core_intc>; + + core_intc: interrupt-controller { + compatible = "snps,arc700-intc"; + interrupt-controller; + #interrupt-cells = <1>; + }; + + uart0: serial at f2202100 { + compatible = "ns16550"; + reg = <0xf2202100 0x20>; + interrupts = <8>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <192000000>; + status = "disabled"; + }; + + uart1: serial at f2202200 { + compatible = "ns16550"; + reg = <0xf2202200 0x20>; + interrupts = <8>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <192000000>; + status = "disabled"; + }; + + uart2: serial at f2202300 { + compatible = "ns16550"; + reg = <0xf2202300 0x20>; + interrupts = <8>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <192000000>; + status = "disabled"; + }; + + uart3: serial at f2202400 { + compatible = "ns16550"; + reg = <0xf2202400 0x20>; + interrupts = <8>; + reg-shift = <2>; + reg-io-width = <4>; + clock-frequency = <192000000>; + status = "disabled"; + }; + + qspi: qspi at f200f000 { + compatible = "adaptrum,anarion-qspi"; + reg = <0xf200f000 0x1000>, + <0x20000000 0x08000000>; + + interrupts = <10>; + status = "disabled"; + }; + + gmac0: ethernet at f2010000 { + compatible = "adaptrum,anarion-gmac", "snps,dwmac"; + reg = <0xf2010000 0x4000>; + + interrupt-parent = <&core_intc>; + interrupts = <20>; + interrupt-names = "macirq"; + + clocks = <&core_clk>; + clock-names = "stmmaceth"; + + snps,pbl = <32>; + status = "disabled"; + }; + + gmac1: ethernet at f2014000 { + compatible = "adaptrum,anarion-gmac", "snps,dwmac"; + reg = <0xf2014000 0x4000>, <0xf2018100 8>; + + interrupt-parent = <&core_intc>; + interrupts = <21>; + interrupt-names = "macirq"; + + clocks = <&core_clk>; + clock-names = "stmmaceth"; + + snps,pbl = <32>; + status = "disabled"; + }; + }; +};
arch/arc/boot/dts/adaptrum_anarion_fpga.dts new file +51 -0
51 lines not on this page · raw message
Signature · 1 line
2.9.3
PATCH v3 2/2 ARC: DTS: Add device-tree for Anarion-based development board
Hi Alexandru,
Quoted 28 lines · Alexandru Gagniuc
This is split into the SOC bindings, and the board dts. The Endor board is currently an FPGA emulation. Once real, silicon arrives, we plan to remove Endor support.
Signed-off-by Alexandru Gagniuc <alex.g at adaptrum.com>---
?arch/arc/boot/dts/adaptrum_anarion.dtsi?????| 110
++++++++++++++++++++++++++++
?arch/arc/boot/dts/adaptrum_anarion_fpga.dts |??51 +++++++++++++ ?2 files changed, 161 insertions(+)
?create mode 100644arch/arc/boot/dts/adaptrum_anarion.dtsi?create mode 100644arch/arc/boot/dts/adaptrum_anarion_fpga.dtsarch/arc/boot/dts/adaptrum_anarion.dtsi new file +5
-0@@ -0,0 +1,110 @@ +/* + * Skeleton for Adaptrum Anarion SOC + * + * (C) Copyright 2017 Adaptrum, Inc. + * Written by Alexandru Gagniuc <alex.g at adaptrum.com> for Adaptrum,Inc.
+ * Licensed under the GPLv2 or (at your option) any later version
+ */
arch/arc/boot/dts/adaptrum_anarion.dtsi line 10
Quoted 3 lines
arch/arc/boot/dts/adaptrum_anarion.dtsi new file +3
-0+ +/* This skeleton is based on the ARC700 CPU */ +#include "skeleton.dtsi"
Perhaps it is better not to use skeleton.dtsi as we are planning to get rid of it.
Signature · 1 line
?Eugeniy Paltsev
PATCH v3 2/2 ARC: DTS: Add device-tree for Anarion-based development board
Quoted 28 lines · Eugeniy Paltsev
Hi Alexandru,
Quoted 25 lines · Alexandru Gagniuc
This is split into the SOC bindings, and the board dts. The Endor board is currently an FPGA emulation. Once real, silicon arrives, we
plan to remove Endor support.Signed-off-by Alexandru Gagniuc <alex.g at adaptrum.com>---
?arch/arc/boot/dts/adaptrum_anarion.dtsi?????| 110
++++++++++++++++++++++++++++
?arch/arc/boot/dts/adaptrum_anarion_fpga.dts |??51 +++++++++++++ ?2 files changed, 161 insertions(+)
?create mode 100644arch/arc/boot/dts/adaptrum_anarion.dtsi?create mode 100644arch/arc/boot/dts/adaptrum_anarion_fpga.dtsarch/arc/boot/dts/adaptrum_anarion.dtsi new file +4
-0@@ -0,0 +1,110 @@ +/* + * Skeleton for Adaptrum Anarion SOC + * + * (C) Copyright 2017 Adaptrum, Inc.
Quoted 9 lines
arch/arc/boot/dts/adaptrum_anarion.dtsi line 10
Quoted 8 lines
arch/arc/boot/dts/adaptrum_anarion.dtsi new file +1
-0+ * Written by Alexandru Gagniuc <alex.g at adaptrum.com> forAdaptrum,
Inc.
+ * Licensed under the GPLv2 or (at your option) any later version
+ */arch/arc/boot/dts/adaptrum_anarion.dtsi new file +3
-0+ +/* This skeleton is based on the ARC700 CPU */ +#include "skeleton.dtsi"
Perhaps it is better not to use skeleton.dtsi as we are planning to get rid of it.
---
Little more explanation:
We faced with fact what we had to override almost all nodes defined in skeleton.dtsi (and other skeletons files like skeleton_hs_idu.dtsi) for our boards. Only the timers nodes are left not overridden. So there is no much sense in skeletons files using and that's why we are planning to get rid of it.
Quoted 5 lines
--?
?Eugeniy Paltsev
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linux-snps-arc mailing list
linux-snps-arc at lists.infradead.org?
Signature · 1 line
?Eugeniy Paltsev
PATCH v3 2/2 ARC: DTS: Add device-tree for Anarion-based development board
In reply to Alexandru GagniucHi Alexandru,
Quoted 1 line · Alexandru Gagniuc
+#include "
skeleton.dtsi"
Eugeniy already commented on that - most probably you'll end up overriding most if not all entries from "skeleton.dtsi" so why bother with it at all?
And I don't see any mention of your own memory node so I assume you rely on the one from our skeleton.dtsi? The first question is if it really matches your setup? I.e. 256 Mb mapped to 0x8000_0000. And even if that's the case what if we change this to something else later?
IMHO having your own "memory" node makes some sens :)
arch/arc/boot/dts/adaptrum_anarion.dtsi line 84
Quoted 6 lines
arch/arc/boot/dts/adaptrum_anarion.dtsi new file +6
-0+ + gmac0: ethernet at f2010000 { + compatible = "adaptrum,anarion-gmac", "snps,dwmac"; + reg = <0xf2010000 0x4000>; + + interrupt-parent = <&core_intc>;
You already specified default INTC above, so you may just drop "interrupt-parent" property from this node.
arch/arc/boot/dts/adaptrum_anarion.dtsi line 99
Quoted 6 lines
arch/arc/boot/dts/adaptrum_anarion.dtsi new file +6
-0+ + gmac1: ethernet at f2014000 { + compatible = "adaptrum,anarion-gmac", "snps,dwmac"; + reg = <0xf2014000 0x4000>, <0xf2018100 8>; + + interrupt-parent = <&core_intc>;
Ditto.
-Alexey
v3 cover Add platform support for Adaptrum Anarion SOC
In reply to Alexandru GagniucQuoted 5 lines · Alexandru Gagniuc
Changes since v2:
* Changed compatible binding of uart[1-3] to "ns16550" (they are not DW UARTs)
* Add support under plat-nsim instead of creating a new stub platform
* Changed board model to "adaptrum,endor-fpga" to allow LEDE scripts to ID the board
* Prefix compatible binding with 'arc-'
Can you provide an updated version soon - it would be nice if it made into next merge window !
Quoted 15 lines
Changes since v1:
* Updated CPU core clock to 24 MHz to match HW changes.Alexandru Gagniuc (2):
ARC: [plat-sim] Add .compatible property for Adaptrum Anarion SOC
ARC: DTS: Add device-tree for Anarion-based development boardarch/arc/boot/dts/adaptrum_anarion.dtsi | 110 ++++++++++++++++++++++++++++ arch/arc/boot/dts/adaptrum_anarion_fpga.dts | 51 +++++++++++++ arch/arc/plat-sim/platform.c | 1 + 3 files changed, 162 insertions(+)create mode 100644
arch/arc/boot/dts/adaptrum_anarion.dtsicreate mode 100644arch/arc/boot/dts/adaptrum_anarion_fpga.dts