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ARM: DRA72x: Add support for detection of DRA71x SR 2.1

PATCH In review Vishal Mahaveer 3 participants 3 messages Aug 26, 2017 – Sep 13, 2017

Subsystems (3)
Arm (32-bit) Arm sub-architectures OMAP2+ support
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Vishal Mahaveer

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#0 lore raw

PATCH 1/1 ARM: DRA72x: Add support for detection of DRA71x SR 2.1

DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors.

Signed-off-by Vishal Mahaveer <[email protected]>
---
 arch/arm/include/asm/arch-omap5/omap.h | 1 +
 arch/arm/include/asm/omap_common.h     | 1 +
 arch/arm/mach-omap2/omap5/hw_data.c    | 2 ++
 arch/arm/mach-omap2/omap5/hwinit.c     | 3 +++
 arch/arm/mach-omap2/omap5/sdram.c      | 2 ++
 board/ti/dra7xx/evm.c                  | 3 +++
 6 files changed, 12 insertions(+)
arch/arm/include/asm/arch-omap5/omap.h +1 -0
index b047f0d..6705544 100644
@@ -63,6 +63,7 @@
 #define DRA752_CONTROL_ID_CODE_ES2_0		0x2B99002F
 #define DRA722_CONTROL_ID_CODE_ES1_0		0x0B9BC02F
 #define DRA722_CONTROL_ID_CODE_ES2_0		0x1B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_1		0x2B9BC02F
 
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
arch/arm/include/asm/omap_common.h +1 -0
index ef5c481..46ee9c2 100644
@@ -766,6 +766,7 @@ static inline u8 is_dra72x(void)
 #define DRA752_ES2_0	0x07520200
 #define DRA722_ES1_0	0x07220100
 #define DRA722_ES2_0	0x07220200
+#define DRA722_ES2_1	0x07220210
 
 /*
  * silicon device type
arch/arm/mach-omap2/omap5/hw_data.c +2 -0
index 4ad6b53..06a9fd2 100644
@@ -719,6 +719,7 @@ void __weak hw_data_init(void)
 
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra72x_dplls;
 	*ctrl = &dra7xx_ctrl;

@@ -753,6 +754,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 		*regs = &ioregs_dra72x_es1;
 		break;
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		*regs = &ioregs_dra72x_es2;
 		break;
arch/arm/mach-omap2/omap5/hwinit.c +3 -0
index afe59e0..d53900f 100644
@@ -377,6 +377,9 @@ void init_omap_revision(void)
 	case DRA722_CONTROL_ID_CODE_ES2_0:
 		*omap_si_rev = DRA722_ES2_0;
 		break;
+	case DRA722_CONTROL_ID_CODE_ES2_1:
+		*omap_si_rev = DRA722_ES2_1;
+		break;
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}
arch/arm/mach-omap2/omap5/sdram.c +2 -0
index 7712923..684b5bc 100644
@@ -481,6 +481,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
 		break;
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
 		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
 		break;

@@ -714,6 +715,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
 	case DRA752_ES2_0:
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		bug_00339_regs_ptr = dra_bug_00339_regs;
 		*iterations = sizeof(dra_bug_00339_regs)/
 			     sizeof(dra_bug_00339_regs[0]);
board/ti/dra7xx/evm.c +3 -0
index 93d3d0b..58feb15 100644
@@ -236,6 +236,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 		break;
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		if (ram_size < CONFIG_MAX_MEM_MAPPED)
 			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 		else

@@ -299,6 +300,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 		break;
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 	default:
 		if (ram_size < CONFIG_MAX_MEM_MAPPED)
 			*dmm_lisa_regs = &lisa_map_2G_x_2;

@@ -643,6 +645,7 @@ void recalibrate_iodelay(void)
 	switch (omap_revision()) {
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		pads = dra72x_core_padconf_array_common;
 		npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 		if (board_is_dra71x_evm()) {
Signature · 1 line
1.9.1
#1 lore raw

PATCH 1/1 ARM: DRA72x: Add support for detection of DRA71x SR 2.1

+ Tom

Quoted 5 lines · Vishal Mahaveer

DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors.

Signed-off-by Vishal Mahaveer <[email protected]>
Reviewed-by Lokesh Vutla <[email protected]>

Thanks and regards,
Lokesh

Quoted 116 lines
---
 arch/arm/include/asm/arch-omap5/omap.h | 1 +
 arch/arm/include/asm/omap_common.h     | 1 +
 arch/arm/mach-omap2/omap5/hw_data.c    | 2 ++
 arch/arm/mach-omap2/omap5/hwinit.c     | 3 +++
 arch/arm/mach-omap2/omap5/sdram.c      | 2 ++
 board/ti/dra7xx/evm.c                  | 3 +++
 6 files changed, 12 insertions(+)
arch/arm/include/asm/arch-omap5/omap.h +1 -0
index b047f0d..6705544 100644
@@ -63,6 +63,7 @@
 #define DRA752_CONTROL_ID_CODE_ES2_0		0x2B99002F
 #define DRA722_CONTROL_ID_CODE_ES1_0		0x0B9BC02F
 #define DRA722_CONTROL_ID_CODE_ES2_0		0x1B9BC02F
+#define DRA722_CONTROL_ID_CODE_ES2_1		0x2B9BC02F
 
 /* UART */
 #define UART1_BASE		(OMAP54XX_L4_PER_BASE + 0x6a000)
arch/arm/include/asm/omap_common.h +1 -0
index ef5c481..46ee9c2 100644
@@ -766,6 +766,7 @@ static inline u8 is_dra72x(void)
 #define DRA752_ES2_0	0x07520200
 #define DRA722_ES1_0	0x07220100
 #define DRA722_ES2_0	0x07220200
+#define DRA722_ES2_1	0x07220210
 
 /*
  * silicon device type
arch/arm/mach-omap2/omap5/hw_data.c +2 -0
index 4ad6b53..06a9fd2 100644
@@ -719,6 +719,7 @@ void __weak hw_data_init(void)
 
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 	*prcm = &dra7xx_prcm;
 	*dplls_data = &dra72x_dplls;
 	*ctrl = &dra7xx_ctrl;

@@ -753,6 +754,7 @@ void get_ioregs(const struct ctrl_ioregs **regs)
 		*regs = &ioregs_dra72x_es1;
 		break;
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		*regs = &ioregs_dra72x_es2;
 		break;
arch/arm/mach-omap2/omap5/hwinit.c +3 -0
index afe59e0..d53900f 100644
@@ -377,6 +377,9 @@ void init_omap_revision(void)
 	case DRA722_CONTROL_ID_CODE_ES2_0:
 		*omap_si_rev = DRA722_ES2_0;
 		break;
+	case DRA722_CONTROL_ID_CODE_ES2_1:
+		*omap_si_rev = DRA722_ES2_1;
+		break;
 	default:
 		*omap_si_rev = OMAP5430_SILICON_ID_INVALID;
 	}
arch/arm/mach-omap2/omap5/sdram.c +2 -0
index 7712923..684b5bc 100644
@@ -481,6 +481,7 @@ void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
 		break;
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		*regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2;
 		*size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz_es2);
 		break;

@@ -714,6 +715,7 @@ const struct read_write_regs *get_bug_regs(u32 *iterations)
 	case DRA752_ES2_0:
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		bug_00339_regs_ptr = dra_bug_00339_regs;
 		*iterations = sizeof(dra_bug_00339_regs)/
 			     sizeof(dra_bug_00339_regs[0]);
board/ti/dra7xx/evm.c +3 -0
index 93d3d0b..58feb15 100644
@@ -236,6 +236,7 @@ void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 		break;
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		if (ram_size < CONFIG_MAX_MEM_MAPPED)
 			*regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 		else

@@ -299,6 +300,7 @@ void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 		break;
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 	default:
 		if (ram_size < CONFIG_MAX_MEM_MAPPED)
 			*dmm_lisa_regs = &lisa_map_2G_x_2;

@@ -643,6 +645,7 @@ void recalibrate_iodelay(void)
 	switch (omap_revision()) {
 	case DRA722_ES1_0:
 	case DRA722_ES2_0:
+	case DRA722_ES2_1:
 		pads = dra72x_core_padconf_array_common;
 		npads = ARRAY_SIZE(dra72x_core_padconf_array_common);
 		if (board_is_dra71x_evm()) {
#2 lore raw
In reply to Vishal Mahaveer
Quoted 6 lines · Vishal Mahaveer

DRA71x processors are reduced pin and software compatible derivative of DRA72 processors. Add support for detection of SR2.1 version of DRA71x family of processors.

Signed-off-by Vishal Mahaveer <[email protected]>
Reviewed-by Lokesh Vutla <[email protected]>

Applied to u-boot/master, thanks!

Signature · 8 lines
Tom
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