Patch "powerpc/mm: Ensure cpumask update is ordered" has been added to the 4.9-stable tree

PATCH [email protected] 1 participant 1 message Aug 28, 2017

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2017-08-28 07:18 UTC #0 lore raw

This is a note to let you know that I've just added the patch titled

powerpc/mm: Ensure cpumask update is ordered

to the 4.9-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
powerpc-mm-ensure-cpumask-update-is-ordered.patch
and it can be found in the queue-4.9 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From 1a92a80ad386a1a6e3b36d576d52a1a456394b70 Mon Sep 17 00:00:00 2001

From: Benjamin Herrenschmidt <[email protected]>
Date: Mon, 24 Jul 2017 14:28:00 +1000
Subject: powerpc/mm: Ensure cpumask update is ordered

From: Benjamin Herrenschmidt <[email protected]>

commit 1a92a80ad386a1a6e3b36d576d52a1a456394b70 upstream.

There is no guarantee that the various isync's involved with the context switch will order the update of the CPU mask with the first TLB entry for the new context being loaded by the HW.

Be safe here and add a memory barrier to order any subsequent load/store which may bring entries into the TLB.

The corresponding barrier on the other side already exists as pte updates use pte_xchg() which uses __cmpxchg_u64 which has a sync after the atomic operation.

Cc [email protected]

Signed-off-by Benjamin Herrenschmidt <[email protected]>

Reviewed-by Nicholas Piggin <[email protected]>

[mpe: Add comments in the code]

[mpe: Backport to 4.12, minor context change]

Signed-off-by Michael Ellerman <[email protected]>

Signed-off-by Greg Kroah-Hartman <[email protected]>

---
 arch/powerpc/include/asm/mmu_context.h      |   20 +++++++++++++++++++-
 arch/powerpc/include/asm/pgtable-be-types.h |    1 +
 arch/powerpc/include/asm/pgtable-types.h    |    1 +
 3 files changed, 21 insertions(+), 1 deletion(-)

arch/powerpc/include/asm/mmu_context.h +19 -1

@@ -75,9 +75,27 @@ static inline void switch_mm_irqs_off(st
 				      struct task_struct *tsk)
 {
 	/* Mark this context has been used on the new CPU */
-	if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next)))
+	if (!cpumask_test_cpu(smp_processor_id(), mm_cpumask(next))) {
 		cpumask_set_cpu(smp_processor_id(), mm_cpumask(next));
 
+		/*
+		 * This full barrier orders the store to the cpumask above vs
+		 * a subsequent operation which allows this CPU to begin loading
+		 * translations for next.
+		 *
+		 * When using the radix MMU that operation is the load of the
+		 * MMU context id, which is then moved to SPRN_PID.
+		 *
+		 * For the hash MMU it is either the first load from slb_cache
+		 * in switch_slb(), and/or the store of paca->mm_ctx_id in
+		 * copy_mm_to_paca().
+		 *
+		 * On the read side the barrier is in pte_xchg(), which orders
+		 * the store to the PTE vs the load of mm_cpumask.
+		 */
+		smp_mb();
+	}
+
 	/* 32-bit keeps track of the current PGDIR in the thread struct */
 #ifdef CONFIG_PPC32
 	tsk->thread.pgdir = next->pgd;

arch/powerpc/include/asm/pgtable-be-types.h +1 -0

@@ -87,6 +87,7 @@ static inline bool pte_xchg(pte_t *ptep,
 	unsigned long *p = (unsigned long *)ptep;
 	__be64 prev;
 
+	/* See comment in switch_mm_irqs_off() */
 	prev = (__force __be64)__cmpxchg_u64(p, (__force unsigned long)pte_raw(old),
 					     (__force unsigned long)pte_raw(new));

arch/powerpc/include/asm/pgtable-types.h +1 -0

@@ -62,6 +62,7 @@ static inline bool pte_xchg(pte_t *ptep,
 {
 	unsigned long *p = (unsigned long *)ptep;
 
+	/* See comment in switch_mm_irqs_off() */
 	return pte_val(old) == __cmpxchg_u64(p, pte_val(old), pte_val(new));
 }
 #endif

Patches currently in stable-queue which might be from [email protected] are

queue-4.9/powerpc-mm-ensure-cpumask-update-is-ordered.patch