Add FPGA, SDRAM drivers and booting to U-boot
Subsystems (5)
cover Add FPGA, SDRAM drivers and booting to U-boot
From: Tien Fong Chee <[email protected]>
This patchset adding FPGA and SDRAM drivers, enable fpga loadfs and booting to U-boot console.
This series is working on top of u-boot.git - http://git.denx.de/u-boot.git
Tien Fong Chee (19):
configs: Add FPGA loadfs config for Arria 10
configs: Add FAT fs support for SPL
arm: socfpga: Add driver for flash to program FPGA
arm: socfpga: Add FPGA loadfs command support
arm: socfpga: Enhance FPGA program support with at least 4 byte data
arm: socfpga: Rename the gen5 sdram driver to more specific name
arm: socfpga: Add DRAM bank size initialization function
arm: socfpga: Add COMPAT macro for Network on Chip(NoC)
arm: socfpga: Add DDR driver for Arria 10
configs: Add DDR Kconfig support for Arria 10
arm: socfpga: Enable build for DDR Arria 10
doc: dtbinding: Add Intel Arria 10 SoCFPGA chosen binding
dts: Add the FPGA design file name to DTS
dts: Add device storage and partition to DTS
arm: socfpga: Add support to memory allocation in SPL
arm: socfpga: Enhance Intel SoCFPGA program header to support Arria
10
arm: socfpga: Adding clock frequency info for U-boot
arm: socfpga: Adding SoCFPGA info for both SPL and U-boot
arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot
.../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 5 +-
arch/arm/mach-socfpga/Kconfig | 1 +
arch/arm/mach-socfpga/board.c | 21 +
arch/arm/mach-socfpga/include/mach/boot0.h | 9 +-
.../include/mach/fpga_manager_arria10.h | 27 +
arch/arm/mach-socfpga/include/mach/sdram.h | 438 +------------
arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 +++-
.../include/mach/{sdram.h => sdram_gen5.h} | 6 +-
arch/arm/mach-socfpga/misc_arria10.c | 5 -
arch/arm/mach-socfpga/spl.c | 93 +++
cmd/fpga.c | 2 +-
common/spl/spl_mmc.c | 2 +-
configs/socfpga_arria10_defconfig | 49 ++-
disk/part.c | 2 +
doc/device-tree-bindings/chosen.txt | 45 ++
drivers/ddr/altera/Kconfig | 2 +-
drivers/ddr/altera/Makefile | 3 +-
drivers/ddr/altera/sdram_arria10.c | 735 ++++++++++++++++++++
drivers/ddr/altera/{sdram.c => sdram_gen5.c} | 0
drivers/fpga/altera.c | 38 +-
drivers/fpga/fpga.c | 8 +
drivers/fpga/socfpga.c | 14 +-
drivers/fpga/socfpga_arria10.c | 386 ++++++++++-
include/altera.h | 6 +
include/configs/socfpga_common.h | 28 +-
include/fdtdec.h | 1 +
include/fpga.h | 2 +
include/spl.h | 2 +
lib/fdtdec.c | 1 +
29 files changed, 1569 insertions(+), 465 deletions(-)
copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
create mode 100644 drivers/ddr/altera/sdram_arria10.c
rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)Signature · 1 line
1.7.7.4
PATCH 1/19 configs: Add FPGA loadfs config for Arria 10
From: Tien Fong Chee <[email protected]>
This config allow FPGA design loaded from FAT fs to FPGA manager.
--- configs/socfpga_arria10_defconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
configs/socfpga_arria10_defconfig +1 -0
@@ -29,3 +29,4 @@ CONFIG_DWAPB_GPIO=y CONFIG_DM_MMC=y CONFIG_SYS_NS16550=y CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_FPGA_LOADFS=y
Signature · 1 line
1.7.7.4
PATCH 1/19 configs: Add FPGA loadfs config for Arria 10
Quoted 14 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This config allow FPGA design loaded from FAT fs to FPGA manager.
Signed-off-by Tien Fong Chee <[email protected]>--- configs/socfpga_arria10_defconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)configs/socfpga_arria10_defconfig +0
-0
configs/socfpga_arria10_defconfig CONFIG_DWAPB_GPIO=y · line 32
Quoted 4 lines
configs/socfpga_arria10_defconfig +1
-0@@ -29,3 +29,4 @@ CONFIG_DWAPB_GPIO=y CONFIG_DM_MMC=y CONFIG_SYS_NS16550=y CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_FPGA_LOADFS=y
You should enable stuff only after you add the necessary support bits ...
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 1/19 configs: Add FPGA loadfs config for Arria 10
Quoted 11 lines · Marek Vasut
Quoted 10 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This config allow FPGA design loaded from FAT fs to FPGA manager.
Signed-off-by Tien Fong Chee <[email protected]>---
configs/socfpga_arria10_defconfig | 1 +1 files changed, 1 insertions(+), 0 deletions(-)
Quoted 13 lines
Quoted 10 lines
configs/socfpga_arria10_defconfig +0
-0@@ -29,3 +29,4 @@ CONFIG_DWAPB_GPIO=yCONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_FPGA_LOADFS=yYou should enable stuff only after you add the necessary support bits
...
I enabled it as early as possible, because i would like to use compiling for detecting any code errors while adding the neccesssary support bits. I can rearrange the patches sequence.
PATCH 1/19 configs: Add FPGA loadfs config for Arria 10
Quoted 25 lines · Tien Fong
Quoted 11 lines · Marek Vasut
Quoted 10 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This config allow FPGA design loaded from FAT fs to FPGA manager.
Signed-off-by Tien Fong Chee <[email protected]>--- configs/socfpga_arria10_defconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)Quoted 13 lines
configs/socfpga_arria10_defconfig CONFIG_DWAPB_GPIO=y · line 32
Quoted 10 lines
configs/socfpga_arria10_defconfig +1
-0@@ -29,3 +29,4 @@ CONFIG_DWAPB_GPIO=y CONFIG_DM_MMC=y CONFIG_SYS_NS16550=y CONFIG_USE_TINY_PRINTF=y +CONFIG_CMD_FPGA_LOADFS=yYou should enable stuff only after you add the necessary support bits
...
Quoted 4 lines
I enabled it as early as possible, because i would like to use compiling for detecting any code errors while adding the neccesssary support bits. I can rearrange the patches sequence.
Except you enable feature which cannot work, so this is wrong. If you need this for debugging purposes, great, but in the series it should go after the groundwork is laid.
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 1/19 configs: Add FPGA loadfs config for Arria 10
Quoted 36 lines · Marek Vasut
Quoted 30 lines · Tien Fong
Quoted 14 lines · Marek Vasut
Quoted 12 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This config allow FPGA design loaded from FAT fs to FPGA manager.
Signed-off-by Tien Fong Chee <[email protected]>---
configs/socfpga_arria10_defconfig | 1 +1 files changed, 1 insertions(+), 0 deletions(-)Quoted 14 lines
Quoted 10 lines
configs/socfpga_arria10_defconfig +0
-0@@ -29,3 +29,4 @@ CONFIG_DWAPB_GPIO=yCONFIG_DM_MMC=y
CONFIG_SYS_NS16550=y
CONFIG_USE_TINY_PRINTF=y
+CONFIG_CMD_FPGA_LOADFS=yYou should enable stuff only after you add the necessary support bits
...Quoted 5 lines
I enabled it as early as possible, because i would like to use compiling for detecting any code errors while adding the neccesssary
support bits. I can rearrange the patches sequence.
Quoted 5 lines
Except you enable feature which cannot work, so this is wrong. If you need this for debugging purposes, great, but in the series it should go
after the groundwork is laid.
Okay, i will reorder the series of patches.
PATCH 2/19 configs: Add FAT fs support for SPL
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
This patch enables FAT file system support for SPL.
--- configs/socfpga_arria10_defconfig | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
configs/socfpga_arria10_defconfig +1 -0
@@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socfpga_arria10_socdk_sdmmc" CONFIG_DEFAULT_FDT_FILE="socfpga_arria10_socdk_sdmmc.dtb" CONFIG_SPL=y CONFIG_SPL_FPGA_SUPPORT=y +CONFIG_SPL_FAT_SUPPORT=y CONFIG_CMD_BOOTZ=y # CONFIG_CMD_IMLS is not set CONFIG_CMD_ASKENV=y
Signature · 1 line
1.7.7.4
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from flash loading RBF to memory and then to program FPGA.
--- .../include/mach/fpga_manager_arria10.h | 27 ++ drivers/fpga/socfpga_arria10.c | 386 +++++++++++++++++++- include/altera.h | 6 + include/configs/socfpga_common.h | 4 + 4 files changed, 422 insertions(+), 1 deletions(-)
arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +27 -0
@@ -8,6 +8,8 @@#ifndef _FPGA_MANAGER_ARRIA10_H_#define _FPGA_MANAGER_ARRIA10_H_ +#include <asm/cache.h> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)
@@ -89,11 +91,36 @@ struct socfpga_fpga_manager {u32 imgcfg_fifo_status; }; +#if defined(CONFIG_CMD_FPGA_LOADFS ) +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { +enum rbf_type section; +enum rbf_security security; +}; + +struct flash_info { +char *interface; +char *dev_part; +char *filename; +int fstype; +u32 remaining; +u32 flash_offset; +struct rbf_info rbfinfo; +struct image_header header; +}; +#endif +/* Functions */ int fpgamgr_program_init (u32 * rbf_data,size_t rbf_size);int fpgamgr_program_finish (void );int is_fpgamgr_user_mode (void );int fpgamgr_wait_early_user_mode (void ); +#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename (const void *fdt,int *len,u32 core); +const char *get_cff_devpart (const void *fdt,int *len); +#endif #endif /* __ASSEMBLY__ */
drivers/fpga/socfpga_arria10.c +385 -1
419 lines not on this page · raw message
include/altera.h +6 -0
@@ -84,6 +84,10 @@ typedef struct {extern int altera_load (Altera_desc *desc,const void *image,size_t size);extern int altera_dump (Altera_desc *desc,const void *buf,size_t bsize);extern int altera_info (Altera_desc *desc); +#if defined(CONFIG_CMD_FPGA_LOADFS ) +int altera_loadfs (Altera_desc *desc,const void *buf,size_t bsize, +fpga_fs_info *fpga_fsinfo); +#endif /* Board specific implementation specific function types *********************************************************************/
@@ -111,6 +115,8 @@ typedef struct {#ifdef CONFIG_FPGA_SOCFPGA int socfpga_load (Altera_desc *desc,const void *rbf_data,size_t rbf_size); +int socfpga_loadfs (Altera_desc *desc,const void *buf,size_t bsize, +fpga_fs_info *fpga_fsinfo);#endif #ifdef CONFIG_FPGA_STRATIX_V
include/configs/socfpga_common.h +4 -0
@@ -27,7 +27,11 @@*/ #define CONFIG_NR_DRAM_BANKS 1#define PHYS_SDRAM_1 0x0 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5 )#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10 ) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) +#endif #define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE#if defined(CONFIG_TARGET_SOCFPGA_GEN5 )
Signature · 1 line
1.7.7.4
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 110 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from flash loading RBF to memory and then to program FPGA.
Signed-off-by Tien Fong Chee <[email protected]>--- .../include/mach/fpga_manager_arria10.h | 27 ++ drivers/fpga/socfpga_arria10.c | 386 +++++++++++++++++++- include/altera.h | 6 + include/configs/socfpga_common.h | 4 + 4 files changed, 422 insertions(+), 1 deletions(-)arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +27
-0@@ -8,6 +8,8 @@#ifndef _FPGA_MANAGER_ARRIA10_H_#define _FPGA_MANAGER_ARRIA10_H_ +#include <asm/cache.h> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)#define ALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK BIT(2)@@ -89,11 +91,36 @@ struct socfpga_fpga_manager {u32 imgcfg_fifo_status; }; +#if defined(CONFIG_CMD_FPGA_LOADFS ) +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { +enum rbf_type section; +enum rbf_security security; +}; + +struct flash_info { +char *interface; +char *dev_part; +char *filename; +int fstype; +u32 remaining; +u32 flash_offset; +struct rbf_info rbfinfo; +struct image_header header; +}; +#endif +/* Functions */ int fpgamgr_program_init (u32 * rbf_data,size_t rbf_size);int fpgamgr_program_finish (void );int is_fpgamgr_user_mode (void );int fpgamgr_wait_early_user_mode (void ); +#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename (const void *fdt,int *len,u32 core); +const char *get_cff_devpart (const void *fdt,int *len); +#endif #endif /* __ASSEMBLY__ */ drivers/fpga/socfpga_arria10.c +17
-1@@ -13,6 +13,12 @@#include <altera.h> #include <common.h> #include <errno.h> +#include <fat.h> +#include <fs.h> +#include <fdtdec.h> +#include <malloc.h> +#include <part.h> +#include <spl.h> #include <wait_bit.h> #include <watchdog.h> @@ -22,6 +28,10 @@#define COMPRESSION_OFFSET 229#define FPGA_TIMEOUT_MSEC 1000/* timeout in ms */ #define FPGA_TIMEOUT_CNT 0x1000000 +#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001DECLARE_GLOBAL_DATA_PTR ;@@ -118,7 +128,7 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void)return wait_for_bit (__func__, &fpga_manager_base->imgcfg_stat, mask, - false,FPGA_TIMEOUT_MSEC , false); + true,FPGA_TIMEOUT_MSEC , false); }static int wait_for_f2s_nstatus_pin (unsigned long value)@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)return 0 ; } +#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename (const void *fdt,int *len,u32 core) +{ +const char *cff_filename =NULL ; +const char *cell; +int nodeoffset;
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 481
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+ nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + +if (nodeoffset >=0 ) { +if (core) + cell =fdt_getprop (fdt, + nodeoffset, +"cffcore-file" , + len); +else + cell =fdt_getprop (fdt, nodeoffset,"cff-file" , len);
This should be a property of the FPGA , not the system . You can have multiple FPGAs and then this would become a problem.
Quoted 6 lines
drivers/fpga/socfpga_arria10.c +6
-0+ +if (cell) + cff_filename = cell; + } + +return cff_filename;
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 497
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+} + +const char *get_cff_devpart (const void *fdt,int *len) +{ +const char *cff_devpart =NULL ; +const char *cell; +int nodeoffset; + nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + + cell =fdt_getprop (fdt, nodeoffset,"cff_devpart" , len);
Indent ? What is this new undocumented DT node about ?
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 511
Quoted 13 lines
drivers/fpga/socfpga_arria10.c +13
-0+if (cell) + cff_devpart = cell; + +return cff_devpart; +} + +void get_rbf_image_info (struct rbf_info *rbf,u16 *buffer) +{ +/* +Magic ID starting at: +-> 1st dword in periph.rbf +-> 2nd dword in core.rbf +*/
Checkpatch should complain about incorrect multiline comment style here ...
Quoted 26 lines
drivers/fpga/socfpga_arria10.c +26
-0+u32 word_reading_max =2 ; +u32 i; + +for (i =0 ; i < word_reading_max; i++) + { +if (RBF_UNENCRYPTED == *(buffer + i))/* PERIPH RBF */ + rbf->security = unencrypted; +else if (RBF_ENCRYPTED == *(buffer + i)) + rbf->security = encrypted; +else if (RBF_UNENCRYPTED == *(buffer + i +1 ))/* CORE RBF */ + rbf->security = unencrypted; +else if (RBF_ENCRYPTED == *(buffer + i +1 )) + rbf->security = encrypted; +else { + rbf->security = invalid; +continue ; + } + +/* PERIPH RBF */ +if (ARRIA10RBF_PERIPH == *(buffer + i +1 )) { + rbf->section = periph_section; +break ; + } +else if (ARRIA10RBF_CORE == *(buffer + i +1 )) { + rbf->section = core_section; +break ;
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 547
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+ }/* CORE RBF */ +else if (ARRIA10RBF_PERIPH == *(buffer + i +2 )) { + rbf->section = periph_section; +break ; + } +else if (ARRIA10RBF_CORE == *(buffer + i +2 )) { + rbf->section = core_section; +break ; + } +else {
} else { ... coding style ...
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+ rbf->section = unknown; +break ; + } + } + +return ; +} + +static int flash_read(struct flash_info *flashinfo, + u32 size_read,
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 567
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+ u32 *buffer_ptr) +{ +size_t ret =EEXIST ; +loff_t actread =0 ; + +#ifdef CONFIG_FS_FAT + ret =fat_read_file (flashinfo->filename, + buffer_ptr, flashinfo->flash_offset, + size_read, &actread); +#endif
How can a generic FPGA driver depend on random FS functionality ? This is broken ...
Quoted 4 lines
drivers/fpga/socfpga_arria10.c +4
-0+if (ret || actread != size_read) { +printf ("Failed to read %s from flash %d " , + flashinfo->filename, + ret);
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 582
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+printf ("!= %d.\n" , size_read); +return -EPERM ; + }else + ret = actread; + +return ret; +} + +static int fs_flash_preinit (struct flash_info *flashinfo, +u32 *buffer,u32 *buffer_sizebytes)
Is this an FPGA driver or MTD driver ?
Quoted 4 lines
drivers/fpga/socfpga_arria10.c +4
-0+{ +u32 *bufferptr_after_header =NULL ; +u32 buffersize_after_header =0 ; +u32 rbf_header_data_size =0 ;
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 596
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+int ret =0 ; + + flashinfo->flash_offset =0 ; + +/* To avoid from keeping re-read the contents */ +struct image_header *header = &(flashinfo->header); +size_t buffer_size = *buffer_sizebytes; +u32 *buffer_ptr = (u32 *)*buffer; + +
Two newlines ... fix
Quoted 286 lines
drivers/fpga/socfpga_arria10.c +243
-0+/* Load mkimage header into buffer */ + ret =flash_read (flashinfo, +sizeof (struct image_header ), buffer_ptr); + +if (0 >= ret) { +printf (" Failed to read mkimage header from flash.\n" ); +return -ENOENT ; + } + +WATCHDOG_RESET (); + +memcpy (header, (u_char *)buffer_ptr,sizeof (*header)); + +if (!image_check_magic (header)) { +printf ("FPGA: Bad Magic Number.\n" ); +return -EBADF ; + } + +if (!image_check_hcrc (header)) { +printf ("FPGA: Bad Header Checksum.\n" ); +return -EPERM ; + } + +/* Getting rbf data size */ + flashinfo->remaining = +image_get_data_size (header); + +/* Calculate total size of both rbf data with mkimage header */ + rbf_header_data_size = flashinfo->remaining + +sizeof (struct image_header ); + +/* Loading to buffer chunk by chunk, normally for OCRAM buffer */ +if (rbf_header_data_size > buffer_size) { +/* Calculate size of rbf data in the buffer */ + buffersize_after_header = + buffer_size -sizeof (struct image_header ); + flashinfo->remaining -= buffersize_after_header; + }else { +/* Loading whole rbf image into buffer, normally for DDR buffer */ + buffer_size = rbf_header_data_size; +/* Calculate size of rbf data in the buffer */ + buffersize_after_header = + buffer_size -sizeof (struct image_header ); + flashinfo->remaining =0 ; + } + +/* Loading mkimage header and rbf data into buffer */ + ret =flash_read (flashinfo, buffer_size, buffer_ptr); + +if (0 >= ret) { +printf (" Failed to read mkimage header and rbf data " ); +printf ("from flash.\n" ); +return -ENOENT ; + } + +/* Getting pointer of rbf data starting address where is it +right after mkimage header */ + bufferptr_after_header = + (u32 *)((u_char *)buffer_ptr +sizeof (struct image_header )); + +/* Update next reading rbf data flash offset */ + flashinfo->flash_offset += buffer_size; + +/* Update the starting addr of rbf data to init FPGA & programming +into FPGA */ + *buffer = (u32 )bufferptr_after_header; + +get_rbf_image_info (&flashinfo->rbfinfo, (u16 *)bufferptr_after_header); + +/* Update the size of rbf data to be programmed into FPGA */ + *buffer_sizebytes = buffersize_after_header; + +#ifdef CONFIG_CHECK_FPGA_DATA_CRC + flashinfo->datacrc = +crc32 (flashinfo->datacrc, + (u_char *)bufferptr_after_header, + buffersize_after_header); +#endif + +if (0 == flashinfo->remaining) { +#ifdef CONFIG_CHECK_FPGA_DATA_CRC +if (flashinfo->datacrc != +image_get_dcrc (&(flashinfo->header))) { +printf ("FPGA: Bad Data Checksum.\n" ); +return -EPERM ; + } +#endif +} +return 0 ; +} + +static int fs_flash_read (struct flash_info *flashinfo,u32 *buffer, +u32 *buffer_sizebytes) +{ +int ret =0 ; +/* To avoid from keeping re-read the contents */ +size_t buffer_size = *buffer_sizebytes; +u32 *buffer_ptr = (u32 *)*buffer; +u32 flash_addr = flashinfo->flash_offset; + +/* Buffer allocated in OCRAM */ +/* Read the data by small chunk by chunk. */ +if (flashinfo->remaining > buffer_size) + flashinfo->remaining -= buffer_size; +else { +/* Buffer allocated in DDR, larger than rbf data most +of the time */ + buffer_size = flashinfo->remaining; + flashinfo->remaining =0 ; + } + + ret =flash_read (flashinfo, buffer_size, buffer_ptr); + +if (0 >= ret) { +printf (" Failed to read rbf data from flash.\n" ); +return -ENOENT ; + } + +#ifdef CONFIG_CHECK_FPGA_DATA_CRC + flashinfo->datacrc = +crc32 (flashinfo->datacrc, + (unsigned char *)buffer_ptr, buffer_size); +#endif + +if (0 == flashinfo->remaining) { +#ifdef CONFIG_CHECK_FPGA_DATA_CRC +if (flashinfo->datacrc != +image_get_dcrc (&(flashinfo->header))) { +printf ("FPGA: Bad Data Checksum.\n" ); +return -EPERM ; + } +#endif +} +/* Update next reading rbf data flash offset */ + flash_addr += buffer_size; + + flashinfo->flash_offset = flash_addr; + +/* Update the size of rbf data to be programmed into FPGA */ + *buffer_sizebytes = buffer_size; + +return 0 ; +} +/* * FPGA Manager to program the FPGA. This is the interface used by FPGA driver. * Return 0 for sucess, non-zero for error. @@ -469,6 +754,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)/* Initialize the FPGA Manager */ status =fpgamgr_program_init ((u32 *)rbf_data, rbf_size); +if (status)return status;@@ -477,3 +763,101 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)return fpgamgr_program_finish (); } + +int socfpga_loadfs (Altera_desc *desc,const void *buf,size_t bsize, +fpga_fs_info *fpga_fsinfo) +{ +u32 buffer =0 ; +u32 buffer_ori =0 ; +size_t buffer_sizebytes =0 ; +size_t buffer_sizebytes_ori =0 ; +struct flash_info flashinfo; +u32 status =0 ; +int ret =0 ; + +memset (&flashinfo,0 ,sizeof (flashinfo)); + +if (fpga_fsinfo->filename ==NULL ) { +printf ("no peripheral RBF filename specified.\n" ); +return -EINVAL ; + } + +WATCHDOG_RESET (); + + buffer_sizebytes = buffer_sizebytes_ori = bsize; + buffer = buffer_ori = (u32 ) buf; + flashinfo.interface = fpga_fsinfo->interface; + flashinfo.dev_part = fpga_fsinfo->dev_part; + flashinfo.filename = fpga_fsinfo->filename; + flashinfo.fstype = fpga_fsinfo->fstype; + +#ifndef CONFIG_SPL_BUILD +if (fs_set_blk_dev (flashinfo.interface, flashinfo.dev_part, + flashinfo.fstype)) +return FPGA_FAIL ; +#endif + +/* Note: Both buffer and buffer_sizebytes values can be altered by +function below. */ + ret =fs_flash_preinit (&flashinfo, &buffer, &buffer_sizebytes); + +if (ret) +return ret; + +if (periph_section == flashinfo.rbfinfo.section) { +/* Initialize the FPGA Manager */ + status =fpgamgr_program_init ((u32 *)buffer, buffer_sizebytes); +if (status) { +printf ("FPGA: Init with periph rbf failed with error. " ); +printf ("code %d\n" , status); +return -EPERM ; + } + } + +WATCHDOG_RESET (); + +/* Transfer data to FPGA Manager */ +fpgamgr_program_write ((void *)buffer, + buffer_sizebytes); + +WATCHDOG_RESET (); + +while (flashinfo.remaining) { + ret =fs_flash_read (&flashinfo, &buffer_ori, + &buffer_sizebytes_ori); + +if (ret) +return ret; + +/* transfer data to FPGA Manager */ +fpgamgr_program_write ((void *)buffer_ori, + buffer_sizebytes_ori); + +WATCHDOG_RESET (); + } + +if (periph_section == flashinfo.rbfinfo.section) { +if (-ETIMEDOUT !=fpgamgr_wait_early_user_mode ()) +printf ("FPGA: Early Release Succeeded.\n" ); +else { +printf ("FPGA: Failed to see Early Release.\n" ); +return -EIO ; + } + }else if (core_section == flashinfo.rbfinfo.section) { +/* Ensure the FPGA entering config done */ + status =fpgamgr_program_finish (); +if (status) +return status; +else +printf ("FPGA: Enter user mode.\n" ); + + }else { +printf ("Config Error: Unsupported FGPA raw binary type.\n" ); +return -ENOEXEC ; + } + +WATCHDOG_RESET (); +return 1 ; + +} +#endif include/altera.h +6
-0@@ -84,6 +84,10 @@ typedef struct {extern int altera_load (Altera_desc *desc,const void *image,size_t size);extern int altera_dump (Altera_desc *desc,const void *buf,size_t bsize);extern int altera_info (Altera_desc *desc); +#if defined(CONFIG_CMD_FPGA_LOADFS ) +int altera_loadfs (Altera_desc *desc,const void *buf,size_t bsize, +fpga_fs_info *fpga_fsinfo); +#endif /* Board specific implementation specific function types *********************************************************************/ @@ -111,6 +115,8 @@ typedef struct {#ifdef CONFIG_FPGA_SOCFPGA int socfpga_load (Altera_desc *desc,const void *rbf_data,size_t rbf_size); +int socfpga_loadfs (Altera_desc *desc,const void *buf,size_t bsize, +fpga_fs_info *fpga_fsinfo);#endif #ifdef CONFIG_FPGA_STRATIX_V include/configs/socfpga_common.h +0
-0
include/configs/socfpga_common.h line 34
Quoted 8 lines
include/configs/socfpga_common.h +4
-0@@ -27,7 +27,11 @@*/ #define CONFIG_NR_DRAM_BANKS 1#define PHYS_SDRAM_1 0x0 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5 )#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10 ) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) +#endif
128 MiB malloc area is nonsense, even those 64 MiB are iffy. Why would you ever need that in a bootloader ?
Quoted 4 lines
include/configs/socfpga_common.h +0
-0#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE#if defined(CONFIG_TARGET_SOCFPGA_GEN5 )
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 125 lines · Marek Vasut
Quoted 124 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from flash loading RBF to memory and then to program FPGA.
Signed-off-by Tien Fong Chee <[email protected]>---
.../include/mach/fpga_manager_arria10.h | 27 ++ drivers/fpga/socfpga_arria10.c | 386
+++++++++++++++++++-
include/altera.h | 6 + include/configs/socfpga_common.h | 4 +4 files changed, 422 insertions(+), 1 deletions(-)(quoted diff) +0
-0
socfpga/include/mach/fpga_manager_arria10.hb/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +0
-0@@ -8,6 +8,8 @@ #ifndef _FPGA_MANAGER_ARRIA10_H_ #define _FPGA_MANAGER_ARRIA10_H_arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +2
-0+#include <asm/cache.h> +#define
ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSKBIT(0)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSKBIT(1)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSKBIT(2)arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +0
-0@@ -89,11 +91,36 @@ struct socfpga_fpga_manager { u32 imgcfg_fifo_status; };arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +21
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { +enum rbf_type section; +enum rbf_security security; +}; + +struct flash_info { +char *interface; +char *dev_part; +char *filename; +int fstype; +u32 remaining; +u32 flash_offset; +struct rbf_info rbfinfo; +struct image_header header; +}; +#endif +/* Functions */
intfpgamgr_program_init(u32 * rbf_data, size_t rbf_size); intfpgamgr_program_finish(void);
intis_fpgamgr_user_mode(void);
intfpgamgr_wait_early_user_mode(void);arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +4
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename (const void *fdt,int *len,u32 core); +const char *get_cff_devpart (const void *fdt,int *len); +#endif
#endif /*__ASSEMBLY__*/drivers/fpga/socfpga_arria10.c +6
-0@@ -13,6 +13,12 @@ #include <altera.h> #include <common.h> #include <errno.h> +#include <fat.h> +#include <fs.h> +#include <fdtdec.h> +#include <malloc.h> +#include <part.h> +#include <spl.h> #include <wait_bit.h> #include <watchdog.h>drivers/fpga/socfpga_arria10.c +4
-0@@ -22,6 +28,10 @@ #define COMPRESSION_OFFSET 229 #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */ #define FPGA_TIMEOUT_CNT 0x1000000 +#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001
DECLARE_GLOBAL_DATA_PTR;drivers/fpga/socfpga_arria10.c +1
-1@@ -118,7 +128,7 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void) return wait_for_bit(__func__, &fpga_manager_base->imgcfg_stat, mask, - false, FPGA_TIMEOUT_MSEC, false); + true, FPGA_TIMEOUT_MSEC, false); }
static intwait_for_f2s_nstatus_pin(unsigned long value)drivers/fpga/socfpga_arria10.c +0
-0@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void) return 0; }drivers/fpga/socfpga_arria10.c +11
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename (const void *fdt,int *len,u32 core) +{ +const char *cff_filename =NULL ; +const char *cell; +int nodeoffset; + nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + +if (nodeoffset >=0 ) { +if (core) + cell = fdt_getprop(fdt,
Quoted 9 lines
Quoted 6 lines
drivers/fpga/socfpga_arria10.c +5
-0+ nodeoffset, +"cffcore-file" , + len); + else + cell = fdt_getprop(fdt, nodeoffset, "cff-file", len);
This should be a property of the FPGA , not the system . You can have multiple FPGAs and then this would become a problem.
This setting is for the only one FPGA inside our SoCFPGA. For external multiple FPGAs programming, user is adviced to store the FPGA filename in environment variable and programming FPGA with fpga loadfs command.
Please note that, peripheral rbf and partition are required in SPL to set up DDR before booting to U-boot.
Quoted 11 lines
Quoted 11 lines
drivers/fpga/socfpga_arria10.c +10
-0+ +if (cell) + cff_filename = cell; + } + +return cff_filename; +} + +const char *get_cff_devpart (const void *fdt,int *len) +{
Quoted 9 lines
Quoted 7 lines
drivers/fpga/socfpga_arria10.c +6
-0+const char *cff_devpart =NULL ; +const char *cell; +int nodeoffset; + nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + + cell = fdt_getprop(fdt, nodeoffset, "cff_devpart",len);
Indent ? What is this new undocumented DT node about ?
You can look the dtbinding doc on patch 12.
Quoted 17 lines
Quoted 4 lines
drivers/fpga/socfpga_arria10.c +3
-0+if (cell) + cff_devpart = cell; +drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 511
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+return cff_devpart; +} + +void get_rbf_image_info (struct rbf_info *rbf,u16 *buffer) +{ +/* +Magic ID starting at: +-> 1st dword in periph.rbf +-> 2nd dword in core.rbf +*/ Checkpatch should complain about incorrect multiline comment style here ...
Okay. I will fix that.
Quoted 33 lines
Quoted 33 lines
drivers/fpga/socfpga_arria10.c +6
-0+u32 word_reading_max =2 ; +u32 i; + +for (i =0 ; i < word_reading_max; i++) + { +if (RBF_UNENCRYPTED == *(buffer + i))/* PERIPH RBF */
drivers/fpga/socfpga_arria10.c +4
-0+ rbf->security = unencrypted; + else if (RBF_ENCRYPTED == *(buffer + i)) + rbf->security = encrypted; + else if (RBF_UNENCRYPTED == *(buffer + i + 1)) /*CORE RBF */
drivers/fpga/socfpga_arria10.c +1
-0+ rbf->security =unencrypted;
drivers/fpga/socfpga_arria10.c +18
-0+else if (RBF_ENCRYPTED == *(buffer + i +1 )) + rbf->security = encrypted; +else { + rbf->security = invalid; +continue ; + } + +/* PERIPH RBF */ +if (ARRIA10RBF_PERIPH == *(buffer + i +1 )) { + rbf->section = periph_section; +break ; + } +else if (ARRIA10RBF_CORE == *(buffer + i +1 )) { + rbf->section = core_section; +break ; + }/* CORE RBF */ +else if (ARRIA10RBF_PERIPH == *(buffer + i +2 )) { + rbf->section = periph_section;
Quoted 9 lines
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 547
Quoted 7 lines
drivers/fpga/socfpga_arria10.c +7
-0+break ; + } +else if (ARRIA10RBF_CORE == *(buffer + i +2 )) { + rbf->section = core_section; +break ; + } +else {} else { ... coding style ...
Okay, i will fix that. This apply to else if?
Quoted 19 lines
Quoted 19 lines
drivers/fpga/socfpga_arria10.c +18
-0+ rbf->section = unknown; +break ; + } + } + +return ; +} + +static int flash_read (struct flash_info *flashinfo, +u32 size_read, +u32 *buffer_ptr) +{ +size_t ret =EEXIST ; +loff_t actread =0 ; + +#ifdef CONFIG_FS_FAT + ret = fat_read_file(flashinfo->filename, + buffer_ptr, flashinfo-
Quoted 6 lines
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 567
Quoted 3 lines
Quoted 1 line
flash_offset,drivers/fpga/socfpga_arria10.c +2
-0+ size_read, &actread); +#endif How can a generic FPGA driver depend on random FS functionality ? This is broken ...
random FS? There would having FAT FS for SDMMC, and UBI FS for QSPI and NAND(implement later). May be i can replace #ifdef CONFIG_FS_FAT witht the codes below, what do you think?
bootdev.boot_device = spl_boot_device();
if(BOOT_DEVICE_MMC1 == bootdev.boot_device)
{ ... }Quoted 17 lines
Quoted 5 lines
drivers/fpga/socfpga_arria10.c +4
-0+if (ret || actread != size_read) { +printf ("Failed to read %s from flash %d " , + flashinfo->filename, + ret);drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 582
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+printf ("!= %d.\n" , size_read); +return -EPERM ; + }else + ret = actread; + +return ret; +} + +static int fs_flash_preinit (struct flash_info *flashinfo, +u32 *buffer,u32 *buffer_sizebytes)Is this an FPGA driver or MTD driver ?
This is FPGA driver. Reading header of rbf, getting filesize and adjusting the beginning offset of RBF.
Quoted 17 lines
Quoted 5 lines
drivers/fpga/socfpga_arria10.c +4
-0+{ +u32 *bufferptr_after_header =NULL ; +u32 buffersize_after_header =0 ; +u32 rbf_header_data_size =0 ;drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 596
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+int ret =0 ; + + flashinfo->flash_offset =0 ; + +/* To avoid from keeping re-read the contents */ +struct image_header *header = &(flashinfo->header); +size_t buffer_size = *buffer_sizebytes; +u32 *buffer_ptr = (u32 *)*buffer; + +Two newlines ... fix
Okay, i will remove.
Quoted 323 lines
Quoted 323 lines
drivers/fpga/socfpga_arria10.c +6
-0+ /* Load mkimage header into buffer */ + ret =flash_read (flashinfo, +sizeof (struct image_header ), buffer_ptr); + +if (0 >= ret) { + printf(" Failed to read mkimage header fromflash.\n");
drivers/fpga/socfpga_arria10.c +22
-0+return -ENOENT ; + } + +WATCHDOG_RESET (); + +memcpy (header, (u_char *)buffer_ptr,sizeof (*header)); + +if (!image_check_magic (header)) { +printf ("FPGA: Bad Magic Number.\n" ); +return -EBADF ; + } + +if (!image_check_hcrc (header)) { +printf ("FPGA: Bad Header Checksum.\n" ); +return -EPERM ; + } + +/* Getting rbf data size */ + flashinfo->remaining = +image_get_data_size (header); + +/* Calculate total size of both rbf data with mkimage header */
drivers/fpga/socfpga_arria10.c +4
-0+ rbf_header_data_size = flashinfo->remaining + +sizeof (struct image_header ); + +/* Loading to buffer chunk by chunk, normally for OCRAM buffer */
drivers/fpga/socfpga_arria10.c +7
-0+if (rbf_header_data_size > buffer_size) { +/* Calculate size of rbf data in the buffer */ + buffersize_after_header = + buffer_size -sizeof (struct image_header ); + flashinfo->remaining -= buffersize_after_header; + }else { +/* Loading whole rbf image into buffer, normally for DDR buffer */
drivers/fpga/socfpga_arria10.c +12
-0+ buffer_size = rbf_header_data_size; +/* Calculate size of rbf data in the buffer */ + buffersize_after_header = + buffer_size -sizeof (struct image_header ); + flashinfo->remaining =0 ; + } + +/* Loading mkimage header and rbf data into buffer */ + ret =flash_read (flashinfo, buffer_size, buffer_ptr); + +if (0 >= ret) { + printf(" Failed to read mkimage header and rbfdata ");
drivers/fpga/socfpga_arria10.c +5
-0+printf ("from flash.\n" ); +return -ENOENT ; + } + +/* Getting pointer of rbf data starting address where is it
drivers/fpga/socfpga_arria10.c +3
-0+right after mkimage header */ + bufferptr_after_header = + (u32 *)((u_char *)buffer_ptr + sizeof(struct
image_header));drivers/fpga/socfpga_arria10.c +5
-0+ +/* Update next reading rbf data flash offset */ + flashinfo->flash_offset += buffer_size; + +/* Update the starting addr of rbf data to init FPGA & programming
drivers/fpga/socfpga_arria10.c +4
-0+into FPGA */ + *buffer = (u32 )bufferptr_after_header; + + get_rbf_image_info(&flashinfo->rbfinfo, (u16*)bufferptr_after_header);
drivers/fpga/socfpga_arria10.c +2
-0+ +/* Update the size of rbf data to be programmed into FPGA */
drivers/fpga/socfpga_arria10.c +22
-0+ *buffer_sizebytes = buffersize_after_header; + +#ifdef CONFIG_CHECK_FPGA_DATA_CRC + flashinfo->datacrc = +crc32 (flashinfo->datacrc, + (u_char *)bufferptr_after_header, + buffersize_after_header); +#endif + +if (0 == flashinfo->remaining) { +#ifdef CONFIG_CHECK_FPGA_DATA_CRC +if (flashinfo->datacrc != +image_get_dcrc (&(flashinfo->header))) { +printf ("FPGA: Bad Data Checksum.\n" ); +return -EPERM ; + } +#endif +} +return 0 ; +} + +static int fs_flash_read(struct flash_info *flashinfo, u32*buffer,
drivers/fpga/socfpga_arria10.c +14
-0+ u32 *buffer_sizebytes) +{ +int ret =0 ; +/* To avoid from keeping re-read the contents */ +size_t buffer_size = *buffer_sizebytes; +u32 *buffer_ptr = (u32 *)*buffer; +u32 flash_addr = flashinfo->flash_offset; + +/* Buffer allocated in OCRAM */ +/* Read the data by small chunk by chunk. */ +if (flashinfo->remaining > buffer_size) + flashinfo->remaining -= buffer_size; +else { +/* Buffer allocated in DDR, larger than rbf data most
drivers/fpga/socfpga_arria10.c +33
-0+of the time */ + buffer_size = flashinfo->remaining; + flashinfo->remaining =0 ; + } + + ret =flash_read (flashinfo, buffer_size, buffer_ptr); + +if (0 >= ret) { +printf (" Failed to read rbf data from flash.\n" ); +return -ENOENT ; + } + +#ifdef CONFIG_CHECK_FPGA_DATA_CRC + flashinfo->datacrc = +crc32 (flashinfo->datacrc, + (unsigned char *)buffer_ptr, buffer_size); +#endif + +if (0 == flashinfo->remaining) { +#ifdef CONFIG_CHECK_FPGA_DATA_CRC +if (flashinfo->datacrc != +image_get_dcrc (&(flashinfo->header))) { +printf ("FPGA: Bad Data Checksum.\n" ); +return -EPERM ; + } +#endif +} +/* Update next reading rbf data flash offset */ + flash_addr += buffer_size; + + flashinfo->flash_offset = flash_addr; + +/* Update the size of rbf data to be programmed into FPGA */
drivers/fpga/socfpga_arria10.c +5
-0+ *buffer_sizebytes = buffer_size; + +return 0 ; +} +/*
* FPGA Manager to program the FPGA. This is the interface used by FPGA driver.
* Return 0 for sucess, non-zero for error.drivers/fpga/socfpga_arria10.c +0
-0@@ -469,6 +754,7 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
/* Initialize the FPGA Manager */
status =fpgamgr_program_init((u32 *)rbf_data, rbf_size); +
if (status)
return status;drivers/fpga/socfpga_arria10.c +0
-0@@ -477,3 +763,101 @@ int socfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size)
returnfpgamgr_program_finish();
}drivers/fpga/socfpga_arria10.c +2
-0+ +int socfpga_loadfs(Altera_desc *desc, const void *buf, size_tbsize,
drivers/fpga/socfpga_arria10.c +28
-0+ fpga_fs_info *fpga_fsinfo) +{ +u32 buffer =0 ; +u32 buffer_ori =0 ; +size_t buffer_sizebytes =0 ; +size_t buffer_sizebytes_ori =0 ; +struct flash_info flashinfo; +u32 status =0 ; +int ret =0 ; + +memset (&flashinfo,0 ,sizeof (flashinfo)); + +if (fpga_fsinfo->filename ==NULL ) { +printf ("no peripheral RBF filename specified.\n" ); +return -EINVAL ; + } + +WATCHDOG_RESET (); + + buffer_sizebytes = buffer_sizebytes_ori = bsize; + buffer = buffer_ori = (u32 ) buf; + flashinfo.interface = fpga_fsinfo->interface; + flashinfo.dev_part = fpga_fsinfo->dev_part; + flashinfo.filename = fpga_fsinfo->filename; + flashinfo.fstype = fpga_fsinfo->fstype; + +#ifndef CONFIG_SPL_BUILD + if (fs_set_blk_dev(flashinfo.interface,flashinfo.dev_part,
drivers/fpga/socfpga_arria10.c +5
-0+ flashinfo.fstype)) +return FPGA_FAIL ; +#endif + +/* Note: Both buffer and buffer_sizebytes values can be altered by
drivers/fpga/socfpga_arria10.c +2
-0+function below. */ + ret = fs_flash_preinit(&flashinfo, &buffer,
&buffer_sizebytes);drivers/fpga/socfpga_arria10.c +7
-0+ +if (ret) +return ret; + +if (periph_section == flashinfo.rbfinfo.section) { +/* Initialize the FPGA Manager */ + status = fpgamgr_program_init((u32 *)buffer,
buffer_sizebytes);drivers/fpga/socfpga_arria10.c +2
-0+if (status) { + printf("FPGA: Init with periph rbf failedwith error. ");
drivers/fpga/socfpga_arria10.c +30
-0+printf ("code %d\n" , status); +return -EPERM ; + } + } + +WATCHDOG_RESET (); + +/* Transfer data to FPGA Manager */ +fpgamgr_program_write ((void *)buffer, + buffer_sizebytes); + +WATCHDOG_RESET (); + +while (flashinfo.remaining) { + ret =fs_flash_read (&flashinfo, &buffer_ori, + &buffer_sizebytes_ori); + +if (ret) +return ret; + +/* transfer data to FPGA Manager */ +fpgamgr_program_write ((void *)buffer_ori, + buffer_sizebytes_ori); + +WATCHDOG_RESET (); + } + +if (periph_section == flashinfo.rbfinfo.section) { +if (-ETIMEDOUT !=fpgamgr_wait_early_user_mode ()) + printf("FPGA: Early ReleaseSucceeded.\n");
drivers/fpga/socfpga_arria10.c +2
-0+else { + printf("FPGA: Failed to see EarlyRelease.\n");
drivers/fpga/socfpga_arria10.c +12
-0+return -EIO ; + } + }else if (core_section == flashinfo.rbfinfo.section) { +/* Ensure the FPGA entering config done */ + status =fpgamgr_program_finish (); +if (status) +return status; +else +printf ("FPGA: Enter user mode.\n" ); + + }else { + printf("Config Error: Unsupported FGPA raw binarytype.\n");
drivers/fpga/socfpga_arria10.c +8
-0+ return -ENOEXEC; + } + +WATCHDOG_RESET (); +return 1 ; + +} +#endif include/altera.h +0
-0@@ -84,6 +84,10 @@ typedef struct { extern int altera_load(Altera_desc *desc, const void *image,size_t size);extern int
altera_dump(Altera_desc *desc, const void *buf, size_t bsize);
extern intaltera_info(Altera_desc *desc);include/altera.h +2
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +int altera_loadfs(Altera_desc *desc, const void *buf, size_tbsize,
include/altera.h +2
-0+ fpga_fs_info *fpga_fsinfo); +#endif
/* Board specific implementation specific function types
*******************************************************************
**/include/altera.h +0
-0@@ -111,6 +115,8 @@ typedef struct {
#ifdefCONFIG_FPGA_SOCFPGA
intsocfpga_load(Altera_desc *desc, const void *rbf_data, size_t rbf_size);
+int socfpga_loadfs(Altera_desc *desc, const void *buf,size_tbsize,include/altera.h +1
-0+ fpga_fs_info *fpga_fsinfo);#endif
#ifdefCONFIG_FPGA_STRATIX_Vinclude/configs/socfpga_common.h +0
-0@@ -27,7 +27,11 @@*/ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x0
Quoted 9 lines
include/configs/socfpga_common.h line 34
Quoted 5 lines
include/configs/socfpga_common.h +4
-0+#if defined(CONFIG_TARGET_SOCFPGA_GEN5 ) #define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10 ) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) +#endif 128 MiB malloc area is nonsense, even those 64 MiB are iffy. Why would
you ever need that in a bootloader ?
This is min require to malloc the buffer in SDRAM for core rbf. Less than this value, something would going wrong, i'm not recall what issue because i already tested this quite long time ago, problem related to FAT and malloc.
Quoted 6 lines
Quoted 5 lines
include/configs/socfpga_common.h +0
-0#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1 #define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 135 lines · Tien Fong
Quoted 125 lines · Marek Vasut
Quoted 124 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from flash loading RBF to memory and then to program FPGA.
Signed-off-by Tien Fong Chee <[email protected]>--- .../include/mach/fpga_manager_arria10.h | 27 ++ drivers/fpga/socfpga_arria10.c | 386 +++++++++++++++++++- include/altera.h | 6 + include/configs/socfpga_common.h | 4 + 4 files changed, 422 insertions(+), 1 deletions(-)(quoted diff) +0
-0
socfpga/include/mach/fpga_manager_arria10.hb/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +2
-0@@ -8,6 +8,8 @@#ifndef _FPGA_MANAGER_ARRIA10_H_#define _FPGA_MANAGER_ARRIA10_H_ +#include <asm/cache.h> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
BIT(2)arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +25
-0@@ -89,11 +91,36 @@ struct socfpga_fpga_manager {u32 imgcfg_fifo_status; }; +#if defined(CONFIG_CMD_FPGA_LOADFS ) +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { +enum rbf_type section; +enum rbf_security security; +}; + +struct flash_info { +char *interface; +char *dev_part; +char *filename; +int fstype; +u32 remaining; +u32 flash_offset; +struct rbf_info rbfinfo; +struct image_header header; +}; +#endif +/* Functions */ int fpgamgr_program_init (u32 * rbf_data,size_t rbf_size);int fpgamgr_program_finish (void );int is_fpgamgr_user_mode (void );int fpgamgr_wait_early_user_mode (void ); +#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename (const void *fdt,int *len,u32 core); +const char *get_cff_devpart (const void *fdt,int *len); +#endif #endif /* __ASSEMBLY__ */ drivers/fpga/socfpga_arria10.c +11
-1@@ -13,6 +13,12 @@#include <altera.h> #include <common.h> #include <errno.h> +#include <fat.h> +#include <fs.h> +#include <fdtdec.h> +#include <malloc.h> +#include <part.h> +#include <spl.h> #include <wait_bit.h> #include <watchdog.h> @@ -22,6 +28,10 @@#define COMPRESSION_OFFSET 229#define FPGA_TIMEOUT_MSEC 1000/* timeout in ms */ #define FPGA_TIMEOUT_CNT 0x1000000 +#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001DECLARE_GLOBAL_DATA_PTR ;@@ -118,7 +128,7 @@ static intwait_for_nconfig_pin_and_nstatus_pin (void ) return wait_for_bit(__func__, &fpga_manager_base->imgcfg_stat, mask, - false,FPGA_TIMEOUT_MSEC , false); + true,FPGA_TIMEOUT_MSEC , false); }static int
wait_for_f2s_nstatus_pin(unsigned long value)drivers/fpga/socfpga_arria10.c +11
-0@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)return 0 ; } +#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename (const void *fdt,int *len,u32 core) +{ +const char *cff_filename =NULL ; +const char *cell; +int nodeoffset; + nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + +if (nodeoffset >=0 ) { +if (core) + cell = fdt_getprop(fdt,Quoted 9 lines
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void)
Quoted 6 lines
drivers/fpga/socfpga_arria10.c +5
-0+ nodeoffset, +"cffcore-file" , + len); + else + cell =fdt_getprop (fdt, nodeoffset,"cff- file", len);This should be a property of the FPGA , not the system . You can have multiple FPGAs and then this would become a problem.
Quoted 1 line
This setting is for the only one FPGA inside our SoCFPGA.
You just said it yourself, it is for the only FPGA in your SOCFPGA , thus it is a property of the FPGA , not a chosen .
Quoted 27 lines
For external
multiple FPGAs programming, user is adviced to store the FPGA filename in environment variable and programming FPGA with fpga loadfs command.Please note that, peripheral rbf and partition are required in SPL to set up DDR before booting to U-boot.
Quoted 11 lines
Quoted 11 lines
drivers/fpga/socfpga_arria10.c +10
-0+ +if (cell) + cff_filename = cell; + } + +return cff_filename; +} + +const char *get_cff_devpart (const void *fdt,int *len) +{Quoted 9 lines
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void)
Quoted 7 lines
drivers/fpga/socfpga_arria10.c +6
-0+const char *cff_devpart =NULL ; +const char *cell; +int nodeoffset; + nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + + cell =fdt_getprop (fdt, nodeoffset,"cff_devpart" , len);Indent ? What is this new undocumented DT node about ?
Quoted 1 line
You can look the dtbinding doc on patch 12.
Ugh, the patch should be in the series before this one.
Quoted 17 lines
Quoted 17 lines
Quoted 4 lines
drivers/fpga/socfpga_arria10.c +3
-0+if (cell) + cff_devpart = cell; +drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 511
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+return cff_devpart; +} + +void get_rbf_image_info (struct rbf_info *rbf,u16 *buffer) +{ +/* +Magic ID starting at: +-> 1st dword in periph.rbf +-> 2nd dword in core.rbf +*/ Checkpatch should complain about incorrect multiline comment style here ...
Quoted 1 line
Okay. I will fix that.
Can you please run checkpatch before submitting your patches ?
Quoted 62 lines
Quoted 33 lines
Quoted 33 lines
drivers/fpga/socfpga_arria10.c +10
-0+u32 word_reading_max =2 ; +u32 i; + +for (i =0 ; i < word_reading_max; i++) + { +if (RBF_UNENCRYPTED == *(buffer + i))/* PERIPH RBF */ + rbf->security = unencrypted; +else if (RBF_ENCRYPTED == *(buffer + i)) + rbf->security = encrypted; +else if (RBF_UNENCRYPTED == *(buffer + i +1 ))/* CORE RBF */
drivers/fpga/socfpga_arria10.c +1
-0+ rbf->security =unencrypted;
drivers/fpga/socfpga_arria10.c +18
-0+else if (RBF_ENCRYPTED == *(buffer + i +1 )) + rbf->security = encrypted; +else { + rbf->security = invalid; +continue ; + } + +/* PERIPH RBF */ +if (ARRIA10RBF_PERIPH == *(buffer + i +1 )) { + rbf->section = periph_section; +break ; + } +else if (ARRIA10RBF_CORE == *(buffer + i +1 )) { + rbf->section = core_section; +break ; + }/* CORE RBF */ +else if (ARRIA10RBF_PERIPH == *(buffer + i +2 )) { + rbf->section = periph_section;Quoted 9 lines
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 547
Quoted 7 lines
drivers/fpga/socfpga_arria10.c +7
-0+break ; + } +else if (ARRIA10RBF_CORE == *(buffer + i +2 )) { + rbf->section = core_section; +break ; + } +else {} else { ... coding style ...
Okay, i will fix that. This apply to else if?
Quoted 19 lines
Quoted 19 lines
drivers/fpga/socfpga_arria10.c +18
-0+ rbf->section = unknown; +break ; + } + } + +return ; +} + +static int flash_read (struct flash_info *flashinfo, +u32 size_read, +u32 *buffer_ptr) +{ +size_t ret =EEXIST ; +loff_t actread =0 ; + +#ifdef CONFIG_FS_FAT + ret = fat_read_file(flashinfo->filename, + buffer_ptr, flashinfo-
Quoted 8 lines
Quoted 6 lines
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 567
Quoted 3 lines
Quoted 1 line
flash_offset,drivers/fpga/socfpga_arria10.c +2
-0+ size_read, &actread); +#endif How can a generic FPGA driver depend on random FS functionality ? This is broken ...
random FS? There would having FAT FS for SDMMC, and UBI FS for QSPI and NAND(implement later).
Driver should not depend on specific FS.
Quoted 6 lines
May be i can replace #ifdef
CONFIG_FS_FATwitht
the codes below, what do you think?bootdev.boot_device = spl_boot_device(); if(BOOT_DEVICE_MMC1 == bootdev.boot_device) { ... }
Nor should it depend on random boot device.
Quoted 17 lines
Quoted 17 lines
Quoted 5 lines
drivers/fpga/socfpga_arria10.c +4
-0+if (ret || actread != size_read) { +printf ("Failed to read %s from flash %d " , + flashinfo->filename, + ret);drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 582
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+printf ("!= %d.\n" , size_read); +return -EPERM ; + }else + ret = actread; + +return ret; +} + +static int fs_flash_preinit (struct flash_info *flashinfo, +u32 *buffer,u32 *buffer_sizebytes)Is this an FPGA driver or MTD driver ?
Quoted 2 lines
This is FPGA driver. Reading header of rbf, getting filesize and adjusting the beginning offset of RBF.
Why do you pass around the struct flashinfo then ?
[...]
Quoted 18 lines
Quoted 9 lines
Quoted 9 lines
include/configs/socfpga_common.h +0
-0@@ -27,7 +27,11 @@*/ #define CONFIG_NR_DRAM_BANKS 1#define PHYS_SDRAM_1 0x0Quoted 9 lines
include/configs/socfpga_common.h line 34
Quoted 5 lines
include/configs/socfpga_common.h +4
-0+#if defined(CONFIG_TARGET_SOCFPGA_GEN5 )#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024) +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10 ) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) +#endif 128 MiB malloc area is nonsense, even those 64 MiB are iffy. Why would
you ever need that in a bootloader ?
Quoted 4 lines
This is min require to malloc the buffer in SDRAM for core rbf. Less than this value, something would going wrong, i'm not recall what issue because i already tested this quite long time ago, problem related to FAT and malloc.
Isn't the loadfs supposed to read the data from the FS and program them into the FPGA without having to read the whole bitstream into the RAM ?
Quoted 5 lines
Quoted 5 lines
Quoted 5 lines
include/configs/socfpga_common.h +0
-0#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE#if defined(CONFIG_TARGET_SOCFPGA_GEN5 )
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 143 lines · Marek Vasut
Quoted 142 lines · Tien Fong
Quoted 140 lines · Marek Vasut
Quoted 132 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from flash loading RBF to memory and then to program FPGA.
Signed-off-by Tien Fong Chee <[email protected]>---
.../include/mach/fpga_manager_arria10.h | 27 ++ drivers/fpga/socfpga_arria10.c | 386
+++++++++++++++++++-
include/altera.h | 6 + include/configs/socfpga_common.h | 4 +4 files changed, 422 insertions(+), 1 deletions(-)(quoted diff) +0
-0
socfpga/include/mach/fpga_manager_arria10.hb/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +0
-0@@ -8,6 +8,8 @@ #ifndef _FPGA_MANAGER_ARRIA10_H_ #define _FPGA_MANAGER_ARRIA10_H_arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +2
-0+#include <asm/cache.h> +#define
ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSKBIT(0)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSKBIT(1)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSKBIT(2)arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +0
-0@@ -89,11 +91,36 @@ struct socfpga_fpga_manager { u32 imgcfg_fifo_status; };arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +21
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { +enum rbf_type section; +enum rbf_security security; +}; + +struct flash_info { +char *interface; +char *dev_part; +char *filename; +int fstype; +u32 remaining; +u32 flash_offset; +struct rbf_info rbfinfo; +struct image_header header; +}; +#endif +/* Functions */
intfpgamgr_program_init(u32 * rbf_data, size_t rbf_size); intfpgamgr_program_finish(void);
intis_fpgamgr_user_mode(void);
intfpgamgr_wait_early_user_mode(void);arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +2
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename(const void *fdt, int *len, u32core);
arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +2
-0+const char *get_cff_devpart (const void *fdt,int *len); +#endif
#endif /*__ASSEMBLY__*/drivers/fpga/socfpga_arria10.c +6
-0@@ -13,6 +13,12 @@ #include <altera.h> #include <common.h> #include <errno.h> +#include <fat.h> +#include <fs.h> +#include <fdtdec.h> +#include <malloc.h> +#include <part.h> +#include <spl.h> #include <wait_bit.h> #include <watchdog.h>drivers/fpga/socfpga_arria10.c +4
-0@@ -22,6 +28,10 @@ #define COMPRESSION_OFFSET 229 #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */ #define FPGA_TIMEOUT_CNT 0x1000000 +#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001
DECLARE_GLOBAL_DATA_PTR;drivers/fpga/socfpga_arria10.c +1
-1@@ -118,7 +128,7 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void) return wait_for_bit(__func__, &fpga_manager_base->imgcfg_stat, mask, - false, FPGA_TIMEOUT_MSEC, false); + true, FPGA_TIMEOUT_MSEC, false); }
static intwait_for_f2s_nstatus_pin(unsigned long value)drivers/fpga/socfpga_arria10.c +0
-0@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void) return 0; }drivers/fpga/socfpga_arria10.c +2
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename(const void *fdt, int *len, u32core)
drivers/fpga/socfpga_arria10.c +14
-0+{ +const char *cff_filename =NULL ; +const char *cell; +int nodeoffset; + nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + +if (nodeoffset >=0 ) { +if (core) + cell =fdt_getprop (fdt, + nodeoffset, +"cffcore-file" , + len); +else + cell = fdt_getprop(fdt, nodeoffset,Quoted 2 lines
"cff-
file", len);This should be a property of the FPGA , not the system . You can have
multiple FPGAs and then this would become a problem.
Quoted 4 lines
Quoted 1 line
This setting is for the only one FPGA inside our SoCFPGA.
You just said it yourself, it is for the only FPGA in your SOCFPGA , thus it is a property of the FPGA , not a chosen .
Okay, what i trying to tell is that there is no multiple FPGAs in our SOCFPGA. The filename is not any hardware properties, it is just a info to tell SPL and U-boot which file to look for programming FPGA. According to chosen node document, chosen node doesn't represent a real HW, but serves as place for passing data. This is why our BSP tool put the filename info here, the file is named by user in our tool, and this info would be consumed by SPL to program FPGA.
What do you think?
Quoted 34 lines
Quoted 34 lines
For external
multiple FPGAs programming, user is adviced to store the FPGA filename
in environment variable and programming FPGA with fpga loadfs command.Please note that, peripheral rbf and partition are required in SPL to
set up DDR before booting to U-boot.Quoted 23 lines
Quoted 19 lines
drivers/fpga/socfpga_arria10.c +16
-0+ +if (cell) + cff_filename = cell; + } + +return cff_filename; +} + +const char *get_cff_devpart (const void *fdt,int *len) +{ +const char *cff_devpart =NULL ; +const char *cell; +int nodeoffset; + nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + + cell = fdt_getprop(fdt, nodeoffset,Quoted 2 lines
"
cff_devpart",
len);Indent ? What is this new undocumented DT node about ?
Quoted 3 lines
Quoted 1 line
You can look the dtbinding doc on patch 12.
Ugh, the patch should be in the series before this one.
Okay, noted.
Quoted 21 lines
Quoted 21 lines
Quoted 21 lines
Quoted 7 lines
drivers/fpga/socfpga_arria10.c +3
-0+if (cell) + cff_devpart = cell; +drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 511
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+return cff_devpart; +} + +void get_rbf_image_info (struct rbf_info *rbf,u16 *buffer) +{ +/* +Magic ID starting at: +-> 1st dword in periph.rbf +-> 2nd dword in core.rbf +*/ Checkpatch should complain about incorrect multiline comment style
here ...
Quoted 3 lines
Quoted 1 line
Okay. I will fix that.
Can you please run checkpatch before submitting your patches ?
Okay, sure.
Quoted 80 lines
Quoted 80 lines
Quoted 42 lines
Quoted 42 lines
drivers/fpga/socfpga_arria10.c +6
-0+u32 word_reading_max =2 ; +u32 i; + +for (i =0 ; i < word_reading_max; i++) + { +if (RBF_UNENCRYPTED == *(buffer + i))/* PERIPH RBF
*/drivers/fpga/socfpga_arria10.c +4
-0+ rbf->security = unencrypted; + else if (RBF_ENCRYPTED == *(buffer + i)) + rbf->security = encrypted; + else if (RBF_UNENCRYPTED == *(buffer + i + 1))/*
CORE RBF */drivers/fpga/socfpga_arria10.c +1
-0+ rbf->security =unencrypted;
drivers/fpga/socfpga_arria10.c +2
-0+else if (RBF_ENCRYPTED == *(buffer + i +1 )) + rbf->security =encrypted;
drivers/fpga/socfpga_arria10.c +11
-0+else { + rbf->security = invalid; +continue ; + } + +/* PERIPH RBF */ +if (ARRIA10RBF_PERIPH == *(buffer + i +1 )) { + rbf->section = periph_section; +break ; + } +else if (ARRIA10RBF_CORE == *(buffer + i +1 )){
drivers/fpga/socfpga_arria10.c +4
-0+ rbf->section = core_section; +break ; + }/* CORE RBF */ + else if (ARRIA10RBF_PERIPH == *(buffer + i +2)) {
drivers/fpga/socfpga_arria10.c +2
-0+ rbf->section = periph_section; +break ;Quoted 9 lines
drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 547
Quoted 7 lines
drivers/fpga/socfpga_arria10.c +2
-0+ } +else if (ARRIA10RBF_CORE == *(buffer + i +2 )){
drivers/fpga/socfpga_arria10.c +4
-0+ rbf->section = core_section; +break ; + } +else {} else { ... coding style ...
Okay, i will fix that. This apply to else if?
Quoted 28 lines
Quoted 23 lines
drivers/fpga/socfpga_arria10.c +18
-0+ rbf->section = unknown; +break ; + } + } + +return ; +} + +static int flash_read (struct flash_info *flashinfo, +u32 size_read, +u32 *buffer_ptr) +{ +size_t ret =EEXIST ; +loff_t actread =0 ; + +#ifdef CONFIG_FS_FAT + ret = fat_read_file(flashinfo->filename, + buffer_ptr, flashinfo-Quoted 2 lines
flash_offset,drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 567
Quoted 2 lines
drivers/fpga/socfpga_arria10.c +2
-0+ size_read, &actread); +#endif How can a generic FPGA driver depend on random FS functionality ? This is broken ...
Quoted 5 lines
Quoted 3 lines
random FS? There would having FAT FS for SDMMC, and UBI FS for QSPI and
NAND(implement later).Driver should not depend on specific FS.
I afraid to use fs_read, need to enable more FS features, which would take a lot memory, could be run out of it in SPL. Do you think it is good to try in SPL?
Quoted 30 lines
Quoted 7 lines
May be i can replace #ifdef
CONFIG_FS_FATwitht
the codes below, what do you think?bootdev.boot_device = spl_boot_device(); if(BOOT_DEVICE_MMC1 == bootdev.boot_device) { ... }Nor should it depend on random boot device.
Quoted 21 lines
Quoted 21 lines
Quoted 9 lines
drivers/fpga/socfpga_arria10.c +2
-0+if (ret || actread != size_read) { + printf("Failed to read %s from flash%d ",
drivers/fpga/socfpga_arria10.c +2
-0+ flashinfo->filename, + ret);drivers/fpga/socfpga_arria10.c int fpgamgr_program_finish(void) · line 582
Quoted 10 lines
drivers/fpga/socfpga_arria10.c +10
-0+printf ("!= %d.\n" , size_read); +return -EPERM ; + }else + ret = actread; + +return ret; +} + +static int fs_flash_preinit (struct flash_info *flashinfo, +u32 *buffer,u32 *buffer_sizebytes)Is this an FPGA driver or MTD driver ?
Quoted 4 lines
Quoted 2 lines
This is FPGA driver. Reading header of rbf, getting filesize and adjusting the beginning offset of RBF.
Why do you pass around the struct flashinfo then ?
This structure contains all infos about the rbf required by FPGA driver to read from flash and programming FPGA.
Quoted 32 lines
[...]
Quoted 23 lines
Quoted 14 lines
Quoted 14 lines
include/configs/socfpga_common.h +1
-0@@ -27,7 +27,11 @@*/ #define CONFIG_NR_DRAM_BANKS 1 #define PHYS_SDRAM_1 0x0 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5 ) #define CONFIG_SYS_MALLOC_LEN (64 * 1024 *Quoted 9 lines
include/configs/socfpga_common.h line 36
Quoted 5 lines
include/configs/socfpga_common.h +3
-01024) +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10 ) +#define CONFIG_SYS_MALLOC_LEN (128 * 1024 * 1024) +#endif 128 MiB malloc area is nonsense, even those 64 MiB are iffy. Why would
you ever need that in a bootloader ?Quoted 7 lines
This is min require to malloc the buffer in SDRAM for core rbf. Less
than this value, something would going wrong, i'm not recall what issue
because i already tested this quite long time ago, problem related to
FAT and malloc.
Quoted 5 lines
Isn't the loadfs supposed to read the data from the FS and program them
into the FPGA without having to read the whole bitstream into the RAM ?
The operation is either reading data from FS into memory and program into FPGA chunk by chunk if memory is smaller than data. or
Reading whole data from FS into memory and program whole into FPGA if memory is larger than data.
Quoted 10 lines
Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
include/configs/socfpga_common.h +0
-0#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1#define
CONFIG_SYS_MEMTEST_ENDPHYS_SDRAM_1_SIZ
E
#ifdefined(CONFIG_TARGET_SOCFPGA_GEN5)
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 144 lines · Tien Fong
Quoted 143 lines · Marek Vasut
Quoted 142 lines · Tien Fong
Quoted 140 lines · Marek Vasut
Quoted 132 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from flash loading RBF to memory and then to program FPGA.
Signed-off-by Tien Fong Chee <[email protected]>--- .../include/mach/fpga_manager_arria10.h | 27 ++ drivers/fpga/socfpga_arria10.c | 386 +++++++++++++++++++- include/altera.h | 6 + include/configs/socfpga_common.h | 4 + 4 files changed, 422 insertions(+), 1 deletions(-)(quoted diff) +0
-0
socfpga/include/mach/fpga_manager_arria10.hb/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +2
-0@@ -8,6 +8,8 @@#ifndef _FPGA_MANAGER_ARRIA10_H_#define _FPGA_MANAGER_ARRIA10_H_ +#include <asm/cache.h> +#define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)#define ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSK BIT(1)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSK
BIT(2)arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +25
-0@@ -89,11 +91,36 @@ struct socfpga_fpga_manager {u32 imgcfg_fifo_status; }; +#if defined(CONFIG_CMD_FPGA_LOADFS ) +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { +enum rbf_type section; +enum rbf_security security; +}; + +struct flash_info { +char *interface; +char *dev_part; +char *filename; +int fstype; +u32 remaining; +u32 flash_offset; +struct rbf_info rbfinfo; +struct image_header header; +}; +#endif +/* Functions */ int fpgamgr_program_init (u32 * rbf_data,size_t rbf_size);int fpgamgr_program_finish (void );int is_fpgamgr_user_mode (void );int fpgamgr_wait_early_user_mode (void ); +#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename (const void *fdt,int *len,u32 core); +const char *get_cff_devpart (const void *fdt,int *len); +#endif #endif /* __ASSEMBLY__ */ drivers/fpga/socfpga_arria10.c +11
-1@@ -13,6 +13,12 @@#include <altera.h> #include <common.h> #include <errno.h> +#include <fat.h> +#include <fs.h> +#include <fdtdec.h> +#include <malloc.h> +#include <part.h> +#include <spl.h> #include <wait_bit.h> #include <watchdog.h> @@ -22,6 +28,10 @@#define COMPRESSION_OFFSET 229#define FPGA_TIMEOUT_MSEC 1000/* timeout in ms */ #define FPGA_TIMEOUT_CNT 0x1000000 +#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001DECLARE_GLOBAL_DATA_PTR ;@@ -118,7 +128,7 @@ static intwait_for_nconfig_pin_and_nstatus_pin (void ) return wait_for_bit(__func__, &fpga_manager_base->imgcfg_stat, mask, - false,FPGA_TIMEOUT_MSEC , false); + true,FPGA_TIMEOUT_MSEC , false); }static int
wait_for_f2s_nstatus_pin(unsigned long value)drivers/fpga/socfpga_arria10.c +16
-0@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)return 0 ; } +#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename (const void *fdt,int *len,u32 core) +{ +const char *cff_filename =NULL ; +const char *cell; +int nodeoffset; + nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + +if (nodeoffset >=0 ) { +if (core) + cell =fdt_getprop (fdt, + nodeoffset, +"cffcore-file" , + len); +else + cell = fdt_getprop(fdt, nodeoffset,Quoted 2 lines
"cff-
file", len);This should be a property of the FPGA , not the system . You can have
multiple FPGAs and then this would become a problem.
Quoted 7 lines
Quoted 4 lines
Quoted 1 line
This setting is for the only one FPGA inside our SoCFPGA.
You just said it yourself, it is for the only FPGA in your SOCFPGA , thus it is a property of the FPGA , not a chosen .
Okay, what i trying to tell is that there is no multiple FPGAs in our SOCFPGA. The filename is not any hardware properties, it is just a info to tell SPL and U-boot which file to look for programming FPGA.
What would happen if you attached an FPGA over ie. SPI or PCIe ? Then you have two FPGAs in the system and you need to describe them in the DT and your "chosen" approach breaks down.
Quoted 5 lines
According to chosen node document, chosen node doesn't represent a real HW, but serves as place for passing data. This is why our BSP tool put the filename info here, the file is named by user in our tool, and this info would be consumed by SPL to program FPGA.
What do you think?
Your BSP tool is broken.
[...]
Quoted 11 lines
Quoted 8 lines
Quoted 6 lines
Quoted 3 lines
How can a generic FPGA driver depend on random FS functionality ? This is broken ...
random FS? There would having FAT FS for SDMMC, and UBI FS for QSPI and
NAND(implement later).Driver should not depend on specific FS.
I afraid to use
fs_read, need to enable more FS features, which would take a lot memory, could be run out of it in SPL. Do you think it is good to try in SPL?
Don't you have like 256k for the SPL on Gen10 ?
[...]
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 177 lines · Marek Vasut
Quoted 171 lines · Tien Fong
Quoted 164 lines · Marek Vasut
Quoted 162 lines · Tien Fong
Quoted 159 lines · Marek Vasut
Quoted 148 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from flash loading
RBF to memory and then to program FPGA.Signed-off-by Tien Fong Chee <[email protected]>---
.../include/mach/fpga_manager_arria10.h | 27 ++
drivers/fpga/socfpga_arria10.c | 386
+++++++++++++++++++-
include/altera.h | 6 +
include/configs/socfpga_common.h | 4 +4 files changed, 422 insertions(+), 1 deletions(-)(quoted diff) +0
-0
socfpga/include/mach/fpga_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.harch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +0
-0@@ -8,6 +8,8 @@ #ifndef _FPGA_MANAGER_ARRIA10_H_ #define _FPGA_MANAGER_ARRIA10_H_arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +2
-0+#include <asm/cache.h> +#define
ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSKBIT(0)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSKBIT(1)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSKBIT(2)
arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +0
-0@@ -89,11 +91,36 @@ struct socfpga_fpga_manager { u32 imgcfg_fifo_status; };arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +21
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { +enum rbf_type section; +enum rbf_security security; +}; + +struct flash_info { +char *interface; +char *dev_part; +char *filename; +int fstype; +u32 remaining; +u32 flash_offset; +struct rbf_info rbfinfo; +struct image_header header; +}; +#endif +/* Functions */
intfpgamgr_program_init(u32 * rbf_data, size_t rbf_size); intfpgamgr_program_finish(void);
intis_fpgamgr_user_mode(void);
intfpgamgr_wait_early_user_mode(void);(quoted diff) +2
-0+#if defined(CONFIG_CMD_FPGA_LOADFS) +const char *get_cff_filename(const void *fdt, int *len,u32
core);arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h +2
-0+const char *get_cff_devpart (const void *fdt,int *len); +#endif
#endif /*__ASSEMBLY__*/drivers/fpga/socfpga_arria10.c +6
-0@@ -13,6 +13,12 @@ #include <altera.h> #include <common.h> #include <errno.h> +#include <fat.h> +#include <fs.h> +#include <fdtdec.h> +#include <malloc.h> +#include <part.h> +#include <spl.h> #include <wait_bit.h> #include <watchdog.h>drivers/fpga/socfpga_arria10.c +4
-0@@ -22,6 +28,10 @@ #define COMPRESSION_OFFSET 229 #define FPGA_TIMEOUT_MSEC 1000 /* timeout in ms */ #define FPGA_TIMEOUT_CNT 0x1000000 +#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001
DECLARE_GLOBAL_DATA_PTR;drivers/fpga/socfpga_arria10.c +0
-0@@ -118,7 +128,7 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void) return wait_for_bit(__func__,&fpga_manager_base-
Quoted 1 line
imgcfg_stat,mask,
drivers/fpga/socfpga_arria10.c +0
-1- false, FPGA_TIMEOUT_MSEC,false);
drivers/fpga/socfpga_arria10.c +1
-0+ true, FPGA_TIMEOUT_MSEC,false);
}
static intwait_for_f2s_nstatus_pin(unsigned long value)drivers/fpga/socfpga_arria10.c +0
-0@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void) return 0; }drivers/fpga/socfpga_arria10.c +2
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename(const void *fdt, int *len,u32
core)drivers/fpga/socfpga_arria10.c +14
-0+{ +const char *cff_filename =NULL ; +const char *cell; +int nodeoffset; + nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + +if (nodeoffset >=0 ) { +if (core) + cell =fdt_getprop (fdt, + nodeoffset, +"cffcore-file" , + len); +else + cell = fdt_getprop(fdt,Quoted 3 lines
nodeoffset,
"cff-
file", len);This should be a property of the FPGA , not the system . You can
have
multiple FPGAs and then this would become a problem.Quoted 5 lines
Quoted 1 line
This setting is for the only one FPGA inside our SoCFPGA.
You just said it yourself, it is for the only FPGA in your SOCFPGA ,
thus it is a property of the FPGA , not a chosen .Quoted 5 lines
Okay, what i trying to tell is that there is no multiple FPGAs in our
SOCFPGA. The filename is not any hardware properties, it is just a info
to tell SPL and U-boot which file to look for programming FPGA.
Quoted 5 lines
What would happen if you attached an FPGA over ie. SPI or PCIe ? Then you have two FPGAs in the system and you need to describe them in
the DT and your "chosen" approach breaks down.
We only need to decribe the internal FPGA of SoCFPGA in DT such as "chosen" to specify which file should SPL looking for getting SDRAM up with programming correct periph rbf into FPGA. When the SDRAM is up running, then only SPL can load U-boot and booting from there. The rest of external multiple FPGAs can be configured through U-boot, such as boot script, interactive in console or from PC host. Other than that, external FPGA can also be configured through Linux.
Quoted 11 lines
Quoted 9 lines
According to chosen node document, chosen node doesn't represent a real
HW, but serves as place for passing data. This is why our BSP tool put
the filename info here, the file is named by user in our tool, and this
info would be consumed by SPL to program FPGA.
What do you think?Your BSP tool is broken.
The BSP tool is used to describe internal FPGA in SOCFPGA. Other external FPGAs other than SOCFPGA itself, it can be programmed through U-boot.
Quoted 14 lines
[...]
Quoted 12 lines
Quoted 12 lines
Quoted 12 lines
Quoted 8 lines
How can a generic FPGA driver depend on random FS
functionality ?
This is broken ...random FS? There would having FAT FS for SDMMC, and UBI FS for QSPI
and
NAND(implement later).
Quoted 9 lines
Quoted 7 lines
Quoted 2 lines
Driver should not depend on specific FS.
I afraid to use
fs_read, need to enable more FS features, which would
take a lot memory, could be run out of it in SPL. Do you think it is
good to try in SPL?Don't you have like 256k for the SPL on Gen10 ?
Yes, i afraid it wouldn't be enough when we enable all NAND and QSPI flashes feature. Our stretch goal is to have all flashes with one defconfig as we did in gen5.
Quoted 2 lines
[...]
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 178 lines · Tien Fong
Quoted 177 lines · Marek Vasut
Quoted 176 lines · Tien Fong
Quoted 164 lines · Marek Vasut
Quoted 162 lines · Tien Fong
Quoted 159 lines · Marek Vasut
Quoted 148 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from flash loading
RBF to memory and then to program FPGA.Signed-off-by Tien Fong Chee <[email protected]>--- .../include/mach/fpga_manager_arria10.h | 27 ++ drivers/fpga/socfpga_arria10.c | 386 +++++++++++++++++++- include/altera.h | 6(quoted diff) +2
-0+ include/configs/socfpga_common.h | 4 + 4 files changed, 422 insertions(+), 1 deletions(-)(quoted diff) +0
-0
socfpga/include/mach/fpga_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h(quoted diff) +2
-0@@ -8,6 +8,8 @@ #ifndef _FPGA_MANAGER_ARRIA10_H_ #define _FPGA_MANAGER_ARRIA10_H_ +#include <asm/cache.h> + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)#define
ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSKBIT(1)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSKBIT(2)
(quoted diff) +23
-0@@ -89,11 +91,36 @@ struct socfpga_fpga_manager { u32 imgcfg_fifo_status; }; +#if defined(CONFIG_CMD_FPGA_LOADFS) +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { + enum rbf_type section; + enum rbf_security security; +}; + +struct flash_info { + char *interface; + char *dev_part; + char *filename; + int fstype; + u32 remaining; + u32 flash_offset; + struct rbf_info rbfinfo; + struct image_header header; +}; +#endif + /* Functions */ int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); int fpgamgr_program_finish(void); int is_fpgamgr_user_mode(void); int fpgamgr_wait_early_user_mode(void); +#if defined(CONFIG_CMD_FPGA_LOADFS) +const char *get_cff_filename(const void *fdt, int *len,u32
core);(quoted diff) +2
-0+const char *get_cff_devpart(const void *fdt, int *len); +#endif #endif /* __ASSEMBLY__ */drivers/fpga/socfpga_arria10.c +11
-1@@ -13,6 +13,12 @@#include <altera.h> #include <common.h> #include <errno.h> +#include <fat.h> +#include <fs.h> +#include <fdtdec.h> +#include <malloc.h> +#include <part.h> +#include <spl.h> #include <wait_bit.h> #include <watchdog.h> @@ -22,6 +28,10 @@#define COMPRESSION_OFFSET 229#define FPGA_TIMEOUT_MSEC 1000/* timeout in ms */ #define FPGA_TIMEOUT_CNT 0x1000000 +#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001DECLARE_GLOBAL_DATA_PTR ;@@ -118,7 +128,7 @@ static intwait_for_nconfig_pin_and_nstatus_pin (void ) return wait_for_bit(__func__, &fpga_manager_base- > imgcfg_stat, mask, - false,FPGA_TIMEOUT_MSEC , false); + true, FPGA_TIMEOUT_MSEC,false);
}static int
wait_for_f2s_nstatus_pin(unsigned long value)drivers/fpga/socfpga_arria10.c +2
-0@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)return 0 ; } +#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename(const void *fdt, int *len,u32
core)drivers/fpga/socfpga_arria10.c +14
-0+{ +const char *cff_filename =NULL ; +const char *cell; +int nodeoffset; + nodeoffset =fdt_subnode_offset (fdt,0 ,"chosen" ); + +if (nodeoffset >=0 ) { +if (core) + cell =fdt_getprop (fdt, + nodeoffset, +"cffcore-file" , + len); +else + cell = fdt_getprop(fdt,Quoted 3 lines
nodeoffset,
"cff-
file", len);This should be a property of the FPGA , not the system . You can
have
multiple FPGAs and then this would become a problem.Quoted 5 lines
Quoted 1 line
This setting is for the only one FPGA inside our SoCFPGA.
You just said it yourself, it is for the only FPGA in your SOCFPGA ,
thus it is a property of the FPGA , not a chosen .Okay, what i trying to tell is that there is no multiple FPGAs in our
SOCFPGA. The filename is not any hardware properties, it is just a info
to tell SPL and U-boot which file to look for programming FPGA.
Quoted 6 lines
Quoted 5 lines
What would happen if you attached an FPGA over ie. SPI or PCIe ? Then you have two FPGAs in the system and you need to describe them in
the DT and your "chosen" approach breaks down.We only need to decribe the internal FPGA of SoCFPGA in DT
This is incorrect. You describe the hardware in DT, if you have multiple FPGAs, then your approach breaks down.
Quoted 16 lines
such as
"chosen" to specify which file should SPL looking for getting SDRAM up with programming correct periph rbf into FPGA. When the SDRAM is up running, then only SPL can load U-boot and booting from there. The rest of external multiple FPGAs can be configured through U-boot, such as boot script, interactive in console or from PC host. Other than that, external FPGA can also be configured through Linux.Quoted 9 lines
Quoted 9 lines
According to chosen node document, chosen node doesn't represent a real
HW, but serves as place for passing data. This is why our BSP tool put
the filename info here, the file is named by user in our tool, and this
info would be consumed by SPL to program FPGA.
What do you think?
Quoted 5 lines
Quoted 2 lines
Your BSP tool is broken.
The BSP tool is used to describe internal FPGA in SOCFPGA. Other external FPGAs other than SOCFPGA itself, it can be programmed through U-boot.
The BSP tool is broken if it generates broken DT, do I have to repeat myself ?
[...]
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 210 lines · Marek Vasut
Quoted 209 lines · Tien Fong
Quoted 207 lines · Marek Vasut
Quoted 192 lines · Tien Fong
Quoted 184 lines · Marek Vasut
Quoted 181 lines · Tien Fong
Quoted 177 lines · Marek Vasut
Quoted 164 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from flash loading
RBF to memory and then to program FPGA.Signed-off-by Tien Fong Chee <[email protected]Quoted 1 line
---
.../include/mach/fpga_manager_arria10.h | 27
++
drivers/fpga/socfpga_arria10.c | 386
+++++++++++++++++++-
include/altera.h | 6
+
include/configs/socfpga_common.h | 4
+4 files changed, 422 insertions(+), 1 deletions(-)(quoted diff) +0
-0
socfpga/include/mach/fpga_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h(quoted diff) +0
-0@@ -8,6 +8,8 @@ #ifndef _FPGA_MANAGER_ARRIA10_H_ #define _FPGA_MANAGER_ARRIA10_H_(quoted diff) +2
-0+#include <asm/cache.h> +#define
ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSKBIT(0)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSKBIT(1)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSKBIT(2)
(quoted diff) +0
-0@@ -89,11 +91,36 @@ struct socfpga_fpga_manager { u32 imgcfg_fifo_status; };(quoted diff) +21
-0+#if defined(CONFIG_CMD_FPGA_LOADFS) +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { + enum rbf_type section; + enum rbf_security security; +}; + +struct flash_info { + char *interface; + char *dev_part; + char *filename; + int fstype; + u32 remaining; + u32 flash_offset; + struct rbf_info rbfinfo; + struct image_header header; +}; +#endif +/* Functions */
int fpgamgr_program_init(u32 *rbf_data,size_trbf_size);
intfpgamgr_program_finish(void);
intis_fpgamgr_user_mode(void);
intfpgamgr_wait_early_user_mode(void);(quoted diff) +2
-0+#if defined(CONFIG_CMD_FPGA_LOADFS) +const char *get_cff_filename(const void *fdt, int*len,
u32
core);
+const char *get_cff_devpart(const void *fdt, int
*len);
+#endif
#endif /*__ASSEMBLY__*/drivers/fpga/socfpga_arria10.c +6
-0@@ -13,6 +13,12 @@ #include <altera.h> #include <common.h> #include <errno.h> +#include <fat.h> +#include <fs.h> +#include <fdtdec.h> +#include <malloc.h> +#include <part.h> +#include <spl.h> #include <wait_bit.h> #include <watchdog.h>drivers/fpga/socfpga_arria10.c +0
-0@@ -22,6 +28,10 @@ #define COMPRESSION_OFFSET 229 #define FPGA_TIMEOUT_MSEC 1000 /* timeout inms */
#defineFPGA_TIMEOUT_CNT0x1000000drivers/fpga/socfpga_arria10.c +4
-0+#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001
DECLARE_GLOBAL_DATA_PTR;drivers/fpga/socfpga_arria10.c +0
-0@@ -118,7 +128,7 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void) return wait_for_bit(__func__,&fpga_manager_base-
Quoted 2 lines
imgcfg_stat,mask,
drivers/fpga/socfpga_arria10.c +0
-1- false, FPGA_TIMEOUT_MSEC,false);
drivers/fpga/socfpga_arria10.c +1
-0+ true, FPGA_TIMEOUT_MSEC,false);
}
static intwait_for_f2s_nstatus_pin(unsigned long value)drivers/fpga/socfpga_arria10.c +0
-0@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void) return 0; }drivers/fpga/socfpga_arria10.c +2
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename(const void *fdt, int*len,
u32
core)drivers/fpga/socfpga_arria10.c +5
-0+{ +const char *cff_filename =NULL ; +const char *cell; +int nodeoffset; + nodeoffset = fdt_subnode_offset(fdt, 0,"chosen");
drivers/fpga/socfpga_arria10.c +6
-0+ +if (nodeoffset >=0 ) { +if (core) + cell = fdt_getprop(fdt, + nodeoffset, + "cffcore-file",
drivers/fpga/socfpga_arria10.c +3
-0+ len); + else + cell = fdt_getprop(fdt,Quoted 3 lines
nodeoffset,
"cff-
file", len);This should be a property of the FPGA , not the system . You
can
have
multiple FPGAs and then this would become a problem.Quoted 5 lines
Quoted 1 line
This setting is for the only one FPGA inside our SoCFPGA.
You just said it yourself, it is for the only FPGA in your SOCFPGA ,
thus it is a property of the FPGA , not a chosen .Quoted 7 lines
Okay, what i trying to tell is that there is no multiple FPGAs in
our
SOCFPGA. The filename is not any hardware properties, it is just a
info
to tell SPL and U-boot which file to look for programming FPGA.What would happen if you attached an FPGA over ie. SPI or PCIe ? Then you have two FPGAs in the system and you need to describe them
in
the DT and your "chosen" approach breaks down.
Quoted 5 lines
Quoted 1 line
We only need to decribe the internal FPGA of SoCFPGA in DT
This is incorrect. You describe the hardware in DT, if you have multiple
FPGAs, then your approach breaks down.
Let me clarify, we don't have FPGA HW properties described in DT, only the RBF files are defined under chosen node. The files are defined only apply for FPGA inside SOCFPGA.
Multiple external FPGA are configured through U-boot.
Quoted 25 lines
Quoted 25 lines
such as
"chosen" to specify which file should SPL looking for getting SDRAM up
with programming correct periph rbf into FPGA. When the SDRAM is up running, then only SPL can load U-boot and booting from there. The rest of external multiple FPGAs can be configured through U- boot,
such as boot script, interactive in console or from PC host. Other than
that, external FPGA can also be configured through Linux.Quoted 14 lines
Quoted 14 lines
According to chosen node document, chosen node doesn't represent a
real
HW, but serves as place for passing data. This is why our BSP tool
put
the filename info here, the file is named by user in our tool, and
this
info would be consumed by SPL to program FPGA.
What do you think?
Quoted 9 lines
Quoted 6 lines
Quoted 2 lines
Your BSP tool is broken.
The BSP tool is used to describe internal FPGA in SOCFPGA. Other external FPGAs other than SOCFPGA itself, it can be programmed through
U-boot.The BSP tool is broken if it generates broken DT, do I have to repeat myself ?
BSP tool is only generate the RBF filename for FPGA inside SOCFPGA. Multiple external FPGA are configured through U-boot.
Quoted 2 lines
[...]
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 251 lines · Tien Fong
Quoted 210 lines · Marek Vasut
Quoted 209 lines · Tien Fong
Quoted 207 lines · Marek Vasut
Quoted 192 lines · Tien Fong
Quoted 184 lines · Marek Vasut
Quoted 181 lines · Tien Fong
Quoted 177 lines · Marek Vasut
Quoted 164 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from flash loading
RBF to memory and then to program FPGA.Signed-off-by Tien Fong Chee <[email protected]Quoted 1 line
---
.../include/mach/fpga_manager_arria10.h|
27
++
drivers/fpga/socfpga_arria10.c|
386
+++++++++++++++++++-
include/altera.h|
6(quoted diff) +2
-0+ include/configs/socfpga_common.h | 4 + 4 files changed, 422 insertions(+), 1 deletions(-)(quoted diff) +0
-0
socfpga/include/mach/fpga_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h(quoted diff) +2
-0@@ -8,6 +8,8 @@ #ifndef _FPGA_MANAGER_ARRIA10_H_ #define _FPGA_MANAGER_ARRIA10_H_ +#include <asm/cache.h> + #define ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSK BIT(0)#define
ALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSKBIT(1)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSKBIT(2)
(quoted diff) +23
-0@@ -89,11 +91,36 @@ struct socfpga_fpga_manager { u32 imgcfg_fifo_status; }; +#if defined(CONFIG_CMD_FPGA_LOADFS) +enum rbf_type {unknown, periph_section, core_section}; +enum rbf_security {invalid, unencrypted, encrypted}; + +struct rbf_info { + enum rbf_type section; + enum rbf_security security; +}; + +struct flash_info { + char *interface; + char *dev_part; + char *filename; + int fstype; + u32 remaining; + u32 flash_offset; + struct rbf_info rbfinfo; + struct image_header header; +}; +#endif + /* Functions */ int fpgamgr_program_init(u32 * rbf_data, size_t rbf_size); int fpgamgr_program_finish(void); int is_fpgamgr_user_mode(void); int fpgamgr_wait_early_user_mode(void); +#if defined(CONFIG_CMD_FPGA_LOADFS) +const char *get_cff_filename(const void *fdt, int *len,u32
core);
+const char *get_cff_devpart(const void *fdt, int
*len);(quoted diff) +1
-0+#endif #endif /* __ASSEMBLY__ */drivers/fpga/socfpga_arria10.c +6
-0@@ -13,6 +13,12 @@#include <altera.h> #include <common.h> #include <errno.h> +#include <fat.h> +#include <fs.h> +#include <fdtdec.h> +#include <malloc.h> +#include <part.h> +#include <spl.h> #include <wait_bit.h> #include <watchdog.h> @@ -22,6 +28,10 @@#define COMPRESSION_OFFSET 229#define FPGA_TIMEOUT_MSEC 1000/* timeout in ms */
#defineFPGA_TIMEOUT_CNT0x1000000drivers/fpga/socfpga_arria10.c +4
-0+#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001DECLARE_GLOBAL_DATA_PTR ;@@ -118,7 +128,7 @@ static intwait_for_nconfig_pin_and_nstatus_pin (void ) return wait_for_bit(__func__, &fpga_manager_base-Quoted 2 lines
imgcfg_stat,drivers/fpga/socfpga_arria10.c +0
-1mask, - false, FPGA_TIMEOUT_MSEC,false);
drivers/fpga/socfpga_arria10.c +1
-0+ true, FPGA_TIMEOUT_MSEC,false);
}static int wait_for_f2s_nstatus_pin(unsigned long
value)drivers/fpga/socfpga_arria10.c +2
-0@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void)return 0 ; } +#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename(const void *fdt, int *len,u32
core)drivers/fpga/socfpga_arria10.c +5
-0+{ +const char *cff_filename =NULL ; +const char *cell; +int nodeoffset; + nodeoffset = fdt_subnode_offset(fdt, 0,"chosen");
drivers/fpga/socfpga_arria10.c +6
-0+ +if (nodeoffset >=0 ) { +if (core) + cell = fdt_getprop(fdt, + nodeoffset, + "cffcore-file",
drivers/fpga/socfpga_arria10.c +3
-0+ len); + else + cell = fdt_getprop(fdt,Quoted 3 lines
nodeoffset,
"cff-
file", len);This should be a property of the FPGA , not the system . You
can
have
multiple FPGAs and then this would become a problem.Quoted 5 lines
Quoted 1 line
This setting is for the only one FPGA inside our SoCFPGA.
You just said it yourself, it is for the only FPGA in your SOCFPGA ,
thus it is a property of the FPGA , not a chosen .Quoted 7 lines
Okay, what i trying to tell is that there is no multiple FPGAs in
our
SOCFPGA. The filename is not any hardware properties, it is just a
info
to tell SPL and U-boot which file to look for programming FPGA.What would happen if you attached an FPGA over ie. SPI or PCIe ? Then you have two FPGAs in the system and you need to describe them
in
the DT and your "chosen" approach breaks down.Quoted 5 lines
Quoted 1 line
We only need to decribe the internal FPGA of SoCFPGA in DT
This is incorrect. You describe the hardware in DT, if you have multiple
FPGAs, then your approach breaks down.Let me clarify, we don't have FPGA HW properties described in DT, only the RBF files are defined under chosen node. The files are defined only apply for FPGA inside SOCFPGA.
Multiple external FPGA are configured through U-boot.Quoted 31 lines
Quoted 31 lines
such as
"chosen" to specify which file should SPL looking for getting SDRAM up
with programming correct periph rbf into FPGA. When the SDRAM is up running, then only SPL can load U-boot and booting from there. The rest of external multiple FPGAs can be configured through U- boot,
such as boot script, interactive in console or from PC host. Other than
that, external FPGA can also be configured through Linux.Quoted 14 lines
Quoted 14 lines
According to chosen node document, chosen node doesn't represent a
real
HW, but serves as place for passing data. This is why our BSP tool
put
the filename info here, the file is named by user in our tool, and
this
info would be consumed by SPL to program FPGA.
What do you think?Quoted 2 lines
Your BSP tool is broken.
The BSP tool is used to describe internal FPGA in SOCFPGA. Other external FPGAs other than SOCFPGA itself, it can be programmed through
U-boot.
Quoted 5 lines
Quoted 3 lines
The BSP tool is broken if it generates broken DT, do I have to repeat myself ?
BSP tool is only generate the RBF filename for FPGA inside SOCFPGA. Multiple external FPGA are configured through U-boot.
What happens if you have FPGA connector over SPI ?
Quoted 1 line
Quoted 1 line
[...]
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 299 lines · Marek Vasut
Quoted 298 lines · Tien Fong
Quoted 243 lines · Marek Vasut
Quoted 241 lines · Tien Fong
Quoted 238 lines · Marek Vasut
Quoted 218 lines · Tien Fong
Quoted 207 lines · Marek Vasut
Quoted 203 lines · Tien Fong
Quoted 198 lines · Marek Vasut
Quoted 182 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This driver handles FPGA program operation from
flash
loading
RBF to memory and then to program FPGA.Signed-off-by Tien Fong Chee <tien.fong.chee@intel.com
Quoted 2 lines
---
.../include/mach/fpga_manager_arria10.h
|
27
++
drivers/fpga/socfpga_arria10.c
|
386
+++++++++++++++++++-
include/altera.h
|
6
+
include/configs/socfpga_common.h
|
4
+4 files changed, 422 insertions(+), 1 deletions(-)(quoted diff) +0
-0
socfpga/include/mach/fpga_manager_arria10.h
b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
index 9cbf696..93a9122 100644
--- a/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h
+++ b/arch/arm/mach-socfpga/include/mach/fpga_manager_arria10.h(quoted diff) +0
-0@@ -8,6 +8,8 @@ #ifndef _FPGA_MANAGER_ARRIA10_H_ #define _FPGA_MANAGER_ARRIA10_H_(quoted diff) +2
-0+#include <asm/cache.h> +#define
ALT_FPGAMGR_IMGCFG_STAT_F2S_CRC_ERROR_SET_MSKBIT(0)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_EARLY_USERMODE_SET_MSKBIT(1)
#defineALT_FPGAMGR_IMGCFG_STAT_F2S_USERMODE_SET_MSKBIT(2)
(quoted diff) +0
-0@@ -89,11 +91,36 @@ struct socfpga_fpga_manager { u32 imgcfg_fifo_status; };(quoted diff) +2
-0+#if defined(CONFIG_CMD_FPGA_LOADFS) +enum rbf_type {unknown, periph_section,
core_section};
+enumrbf_security{invalid, unencrypted,
encrypted};(quoted diff) +18
-0+ +struct rbf_info { + enum rbf_type section; + enum rbf_security security; +}; + +struct flash_info { + char *interface; + char *dev_part; + char *filename; + int fstype; + u32 remaining; + u32 flash_offset; + struct rbf_info rbfinfo; + struct image_header header; +}; +#endif +/* Functions */
int fpgamgr_program_init(u32 *rbf_data,size_trbf_size);
intfpgamgr_program_finish(void);
intis_fpgamgr_user_mode(void);
intfpgamgr_wait_early_user_mode(void);(quoted diff) +2
-0+#if defined(CONFIG_CMD_FPGA_LOADFS) +const char *get_cff_filename(const void *fdt, int*len,
u32
core);
+const char *get_cff_devpart(const void *fdt, int
*len);
+#endif
#endif /*__ASSEMBLY__*/drivers/fpga/socfpga_arria10.c +6
-0@@ -13,6 +13,12 @@ #include <altera.h> #include <common.h> #include <errno.h> +#include <fat.h> +#include <fs.h> +#include <fdtdec.h> +#include <malloc.h> +#include <part.h> +#include <spl.h> #include <wait_bit.h> #include <watchdog.h>drivers/fpga/socfpga_arria10.c +0
-0@@ -22,6 +28,10 @@ #define COMPRESSION_OFFSET 229 #define FPGA_TIMEOUT_MSEC 1000 /* timeoutin
ms */
#defineFPGA_TIMEOUT_CNT0x1000000drivers/fpga/socfpga_arria10.c +4
-0+#define RBF_UNENCRYPTED 0xa65c +#define RBF_ENCRYPTED 0xa65d +#define ARRIA10RBF_PERIPH 0x0001 +#define ARRIA10RBF_CORE 0x8001
DECLARE_GLOBAL_DATA_PTR;drivers/fpga/socfpga_arria10.c +0
-0@@ -118,7 +128,7 @@ static int wait_for_nconfig_pin_and_nstatus_pin(void) return wait_for_bit(__func__,&fpga_manager_base-
Quoted 3 lines
imgcfg_stat,mask,
drivers/fpga/socfpga_arria10.c +0
-1- false,
FPGA_TIMEOUT_MSEC,
false);drivers/fpga/socfpga_arria10.c +1
-0+ true,
FPGA_TIMEOUT_MSEC,
false);
}
static intwait_for_f2s_nstatus_pin(unsigned long value)drivers/fpga/socfpga_arria10.c +0
-0@@ -453,6 +463,281 @@ int fpgamgr_program_finish(void) return 0; }drivers/fpga/socfpga_arria10.c +2
-0+#if defined(CONFIG_CMD_FPGA_LOADFS ) +const char *get_cff_filename(const void *fdt, int*len,
u32
core)drivers/fpga/socfpga_arria10.c +5
-0+{ +const char *cff_filename =NULL ; +const char *cell; +int nodeoffset; + nodeoffset = fdt_subnode_offset(fdt, 0,"chosen");
drivers/fpga/socfpga_arria10.c +5
-0+ +if (nodeoffset >=0 ) { +if (core) + cell =fdt_getprop (fdt, + nodeoffset,
drivers/fpga/socfpga_arria10.c +1
-0+ "cffcore-file",
drivers/fpga/socfpga_arria10.c +3
-0+ len); + else + cell = fdt_getprop(fdt,Quoted 3 lines
nodeoffset,
"cff-
file", len);This should be a property of the FPGA , not the system .
You
can
have
multiple FPGAs and then this would become a problem.Quoted 7 lines
Quoted 2 lines
This setting is for the only one FPGA inside our
SoCFPGA.You just said it yourself, it is for the only FPGA in your
SOCFPGA ,
thus it is a property of the FPGA , not a chosen .Quoted 9 lines
Okay, what i trying to tell is that there is no multiple FPGAs
in
our
SOCFPGA. The filename is not any hardware properties, it is just a
info
to tell SPL and U-boot which file to look for programming FPGA.What would happen if you attached an FPGA over ie. SPI or PCIe ?
Then you have two FPGAs in the system and you need to describe
them
in
the DT and your "chosen" approach breaks down.Quoted 5 lines
Quoted 1 line
We only need to decribe the internal FPGA of SoCFPGA in DT
This is incorrect. You describe the hardware in DT, if you have multiple
FPGAs, then your approach breaks down.Let me clarify, we don't have FPGA HW properties described in DT, only
the RBF files are defined under chosen node. The files are defined only
apply for FPGA inside SOCFPGA.
Multiple external FPGA are configured through U-boot.Quoted 42 lines
Quoted 42 lines
such as
"chosen" to specify which file should SPL looking for getting SDRAM
up
with programming correct periph rbf into FPGA. When the SDRAM is up
running, then only SPL can load U-boot and booting from there. The rest of external multiple FPGAs can be configured through U-
boot,
such as boot script, interactive in console or from PC host. Other
than
that, external FPGA can also be configured through Linux.Quoted 18 lines
Quoted 5 lines
Quoted 13 lines
According to chosen node document, chosen node doesn't represent a
real
HW, but serves as place for passing data. This is why our BSP
tool
put
the filename info here, the file is named by user in our tool,
and
this
info would be consumed by SPL to program FPGA. What do you think?Quoted 2 lines
Your BSP tool is broken.
The BSP tool is used to describe internal FPGA in SOCFPGA. Other
external FPGAs other than SOCFPGA itself, it can be programmed through
U-boot.
Quoted 8 lines
Quoted 6 lines
Quoted 4 lines
The BSP tool is broken if it generates broken DT, do I have to repeat
myself ?BSP tool is only generate the RBF filename for FPGA inside SOCFPGA. Multiple external FPGA are configured through U-boot.
What happens if you have FPGA connector over SPI ?
I assume you are saying FPGA connected to EPCQ, and this is one of the external FPGA configuration, like PCIE. For any external FPGA configuration, FPGA itself/external HOST would get the FPGA data from storage such as EPCQ and configuring the FPGA without HPS/Bootloader intervine. SPL/U-boot would skip the FPGA configuration process when they see the mode is set to external FPGA configuration.
I know you want a DT to describe all FPGAs with FPGA node and their own data filename in every node. But, at this moment, all external FPGAs chip other than SOCFPGA itself are configured through U-boot(script & env variable), or external FPGA configuration method.
How about i just create a FPGA node for SOCFPGA, with FPGA data filename within the node?
Quoted 4 lines
Quoted 3 lines
Quoted 3 lines
[...]
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
On 09/06/2017 07:06 AM, Chee, Tien Fong wrote:
[...]
Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
Quoted 9 lines
Quoted 5 lines
The BSP tool is used to describe internal FPGA in SOCFPGA. Other
external FPGAs other than SOCFPGA itself, it can be programmed through
U-boot.The BSP tool is broken if it generates broken DT, do I have to repeat
myself ?
Quoted 5 lines
Quoted 4 lines
Quoted 2 lines
BSP tool is only generate the RBF filename for FPGA inside SOCFPGA. Multiple external FPGA are configured through U-boot.
What happens if you have FPGA connector over SPI ?
I assume you are saying FPGA connected to EPCQ
No, I mean FPGA connected over SPI bus.
Quoted 11 lines
, and this is one of the
external FPGA configuration, like PCIE. For any external FPGA configuration, FPGA itself/external HOST would get the FPGA data from storage such as EPCQ and configuring the FPGA without HPS/Bootloader intervine. SPL/U-boot would skip the FPGA configuration process when they see the mode is set to external FPGA configuration.I know you want a DT to describe all FPGAs with FPGA node and their own data filename in every node. But, at this moment, all external FPGAs chip other than SOCFPGA itself are configured through U-boot(script & env variable), or external FPGA configuration method.
I want DT which describes hardware and is not misdesigned crap. Just because the BSP tool is broken does not mean I can allow upstream to accept that, no way.
Quoted 2 lines
How about i just create a FPGA node for SOCFPGA, with FPGA data filename within the node?
Isn't that what the FPGA manager in mainline Linux does already ?
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 3/19 arm: socfpga: Add driver for flash to program FPGA
Quoted 50 lines · Marek Vasut
On 09/06/2017 07:06 AM, Chee, Tien Fong wrote:
[...]Quoted 16 lines
Quoted 16 lines
Quoted 16 lines
Quoted 16 lines
Quoted 11 lines
The BSP tool is used to describe internal FPGA in SOCFPGA. Other
external FPGAs other than SOCFPGA itself, it can be programmed
through
U-boot.The BSP tool is broken if it generates broken DT, do I have to
repeat
myself ?Quoted 6 lines
Quoted 5 lines
Quoted 3 lines
BSP tool is only generate the RBF filename for FPGA inside SOCFPGA.
Multiple external FPGA are configured through U-boot.What happens if you have FPGA connector over SPI ?
I assume you are saying FPGA connected to EPCQ
No, I mean FPGA connected over SPI bus.
Quoted 11 lines
, and this is one of the
external FPGA configuration, like PCIE. For any external FPGA configuration, FPGA itself/external HOST would get the FPGA data from
storage such as EPCQ and configuring the FPGA without HPS/Bootloader
intervine. SPL/U-boot would skip the FPGA configuration process when
they see the mode is set to external FPGA configuration.Quoted 7 lines
I know you want a DT to describe all FPGAs with FPGA node and their own
data filename in every node. But, at this moment, all external FPGAs
chip other than SOCFPGA itself are configured through U-boot(script &
env variable), or external FPGA configuration method.I want DT which describes hardware and is not misdesigned crap. Just because the BSP tool is broken does not mean I can allow upstream
to accept that, no way.Quoted 1 line
Quoted 4 lines
Quoted 2 lines
How about i just create a FPGA node for SOCFPGA, with FPGA data filename within the node?
Isn't that what the FPGA manager in mainline Linux does already ?
Yeah, i will port from Linux DTS, and filenames added into the node.
PATCH 4/19 arm: socfpga: Add FPGA loadfs command support
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
This patch enables FPGA loadfs command support to U-boot console.
--- cmd/fpga.c | 2 +- drivers/fpga/altera.c | 38 ++++++++++++++++++++++++++++++-------- drivers/fpga/fpga.c | 8 ++++++++ include/fpga.h | 2 ++ 4 files changed, 41 insertions(+), 9 deletions(-)
cmd/fpga.c +1 -1
@@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga, "(Xilinx only)\n"#endif #if defined(CONFIG_CMD_FPGA_LOADFS ) -"Load device from filesystem (FAT by default) (Xilinx only)\n" +"Load device from filesystem (FAT by default)\n" " loadfs [dev] [address] [image size] [blocksize] <interface>\n" " [<dev[:part]>] <filename>\n"#endif
drivers/fpga/altera.c +30 -8
@@ -23,25 +23,30 @@ static const struct altera_fpga {enum altera_family family;const char *name;int (*load)(Altera_desc *,const void *,size_t ); +int (*loadfs)(Altera_desc *,const void *,size_t , +fpga_fs_info *);int (*dump)(Altera_desc *,const void *,size_t );int (*info)(Altera_desc *); } altera_fpga[] = { #if defined(CONFIG_FPGA_ACEX1K) - { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, - { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, + { Altera_ACEX1K, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump, ACEX1K_info }, + { Altera_CYC2, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump, ACEX1K_info }, #elif defined(CONFIG_FPGA_CYCLON2) - { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, - { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, + { Altera_ACEX1K, "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info }, + { Altera_CYC2, "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info }, #endif #if defined(CONFIG_FPGA_STRATIX_II) - { Altera_StratixII, "StratixII", StratixII_load, + { Altera_StratixII, "StratixII", StratixII_load, NULL, StratixII_dump, StratixII_info }, #endif #if defined(CONFIG_FPGA_STRATIX_V) - { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL }, + { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL, NULL }, #endif -#if defined(CONFIG_FPGA_SOCFPGA) - { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, +#if defined(CONFIG_FPGA_SOCFPGA) && !defined(CONFIG_CMD_FPGA_LOADFS) + { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL, NULL }, +#endif +#if defined(CONFIG_FPGA_SOCFPGA) && defined(CONFIG_CMD_FPGA_LOADFS) + { Altera_SoCFPGA, "SoC FPGA", socfpga_load, socfpga_loadfs, NULL, NULL }, #endif };
@@ -174,3 +179,20 @@ int altera_info(Altera_desc *desc)return FPGA_SUCCESS ; } + +#if defined(CONFIG_CMD_FPGA_LOADFS ) +int altera_loadfs (Altera_desc *desc,const void *buf,size_t bsize, +fpga_fs_info *fpga_fsinfo) +{ +const struct altera_fpga *fpga =altera_desc_to_fpga (desc, __func__); + +if (!fpga) +return FPGA_FAIL ; + +debug_cond (FPGA_DEBUG ,"%s: Launching the %s FS Loader...\n" , + __func__, fpga->name); +if (fpga->loadfs) +return fpga->loadfs (desc, buf, bsize, fpga_fsinfo); +return 0 ; +} +#endif
drivers/fpga/fpga.c +8 -0
@@ -198,6 +198,14 @@ int fpga_fsload(int devnum, const void *buf, size_t size,fpga_no_sup ((char *)__func__,"Xilinx devices" );#endif break ; +#if defined(CONFIG_FPGA_ALTERA ) +case fpga_altera: + ret_val =altera_loadfs (desc->devdesc, buf, size, + fpga_fsinfo); +#else +fpga_no_sup ((char *)__func__,"Altera devices" ); +#endif +break ;default :printf ("%s: Invalid or unsupported device type %d\n" , __func__, desc->devtype);
include/fpga.h +2 -0
@@ -56,8 +56,10 @@ int fpga_count(void);const fpga_desc *const fpga_get_desc (int devnum);int fpga_load (int devnum,const void *buf,size_t bsize,bitstream_type bstype); +#if defined(CONFIG_CMD_FPGA_LOADFS )int fpga_fsload (int devnum,const void *buf,size_t size,fpga_fs_info *fpga_fsinfo); +#endif int fpga_loadbitstream (int devnum,char *fpgadata,size_t size,bitstream_type bstype);int fpga_dump (int devnum,const void *buf,size_t bsize);
Signature · 1 line
1.7.7.4
PATCH 4/19 arm: socfpga: Add FPGA loadfs command support
Quoted 5 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This patch enables FPGA loadfs command support to U-boot console.
Signed-off-by Tien Fong Chee <[email protected]>
But you enabled support for this in patch 1/19 ... ordering issue ? Patch changelog doesn't match what the patch does ...
Quoted 89 lines
--- cmd/fpga.c | 2 +- drivers/fpga/altera.c | 38 ++++++++++++++++++++++++++++++-------- drivers/fpga/fpga.c | 8 ++++++++ include/fpga.h | 2 ++ 4 files changed, 41 insertions(+), 9 deletions(-)cmd/fpga.c +1
-1@@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga, "(Xilinx only)\n"#endif #if defined(CONFIG_CMD_FPGA_LOADFS ) -"Load device from filesystem (FAT by default) (Xilinx only)\n" +"Load device from filesystem (FAT by default)\n" " loadfs [dev] [address] [image size] [blocksize] <interface>\n" " [<dev[:part]>] <filename>\n"#endif drivers/fpga/altera.c +30
-8@@ -23,25 +23,30 @@ static const struct altera_fpga {enum altera_family family;const char *name;int (*load)(Altera_desc *,const void *,size_t ); +int (*loadfs)(Altera_desc *,const void *,size_t , +fpga_fs_info *);int (*dump)(Altera_desc *,const void *,size_t );int (*info)(Altera_desc *); } altera_fpga[] = { #if defined(CONFIG_FPGA_ACEX1K) - { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, - { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump, ACEX1K_info }, + { Altera_ACEX1K, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump, ACEX1K_info }, + { Altera_CYC2, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump, ACEX1K_info }, #elif defined(CONFIG_FPGA_CYCLON2) - { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, - { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump, CYC2_info }, + { Altera_ACEX1K, "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info }, + { Altera_CYC2, "CycloneII", CYC2_load, NULL, CYC2_dump, CYC2_info }, #endif #if defined(CONFIG_FPGA_STRATIX_II) - { Altera_StratixII, "StratixII", StratixII_load, + { Altera_StratixII, "StratixII", StratixII_load, NULL, StratixII_dump, StratixII_info }, #endif #if defined(CONFIG_FPGA_STRATIX_V) - { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL }, + { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL, NULL }, #endif -#if defined(CONFIG_FPGA_SOCFPGA) - { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, +#if defined(CONFIG_FPGA_SOCFPGA) && !defined(CONFIG_CMD_FPGA_LOADFS) + { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL, NULL }, +#endif +#if defined(CONFIG_FPGA_SOCFPGA) && defined(CONFIG_CMD_FPGA_LOADFS) + { Altera_SoCFPGA, "SoC FPGA", socfpga_load, socfpga_loadfs, NULL, NULL }, #endif };@@ -174,3 +179,20 @@ int altera_info(Altera_desc *desc)return FPGA_SUCCESS ; } + +#if defined(CONFIG_CMD_FPGA_LOADFS ) +int altera_loadfs (Altera_desc *desc,const void *buf,size_t bsize, +fpga_fs_info *fpga_fsinfo) +{ +const struct altera_fpga *fpga =altera_desc_to_fpga (desc, __func__); + +if (!fpga) +return FPGA_FAIL ; + +debug_cond (FPGA_DEBUG ,"%s: Launching the %s FS Loader...\n" , + __func__, fpga->name); +if (fpga->loadfs) +return fpga->loadfs (desc, buf, bsize, fpga_fsinfo); +return 0 ; +} +#endif drivers/fpga/fpga.c +0
-0
drivers/fpga/fpga.c int fpga_fsload(int devnum, const void *buf, size_t size, · line 204
Quoted 7 lines
drivers/fpga/fpga.c +4
-0@@ -198,6 +198,14 @@ int fpga_fsload(int devnum, const void *buf, size_t size,fpga_no_sup ((char *)__func__,"Xilinx devices" );#endif break ; +#if defined(CONFIG_FPGA_ALTERA ) +case fpga_altera: + ret_val =altera_loadfs (desc->devdesc, buf, size, + fpga_fsinfo);
Why is this not a generic code ? Load stuff from FS and program it into the FPGA directly, should be pretty generic operation IMO.
Quoted 23 lines
drivers/fpga/fpga.c +4
-0+#else +fpga_no_sup ((char *)__func__,"Altera devices" ); +#endif +break ;default :printf ("%s: Invalid or unsupported device type %d\n" , __func__, desc->devtype);include/fpga.h +2
-0@@ -56,8 +56,10 @@ int fpga_count(void);const fpga_desc *const fpga_get_desc (int devnum);int fpga_load (int devnum,const void *buf,size_t bsize,bitstream_type bstype); +#if defined(CONFIG_CMD_FPGA_LOADFS )int fpga_fsload (int devnum,const void *buf,size_t size,fpga_fs_info *fpga_fsinfo); +#endif int fpga_loadbitstream (int devnum,char *fpgadata,size_t size,bitstream_type bstype);int fpga_dump (int devnum,const void *buf,size_t bsize);
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 4/19 arm: socfpga: Add FPGA loadfs command support
Quoted 10 lines · Marek Vasut
Quoted 6 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This patch enables FPGA loadfs command support to U-boot console.
Signed-off-by Tien Fong Chee <[email protected]>But you enabled support for this in patch 1/19 ... ordering issue ? Patch changelog doesn't match what the patch does ...
This patch is adding the FPGA loadfs command support for Arria 10. I enabled FPGA loadfs in patch 1/19, so i can compile the changes in this patch immediately.
So, you want me to improve the commit message and reordering?
Quoted 119 lines
Quoted 119 lines
---
cmd/fpga.c | 2 +-
drivers/fpga/altera.c | 38 ++++++++++++++++++++++++++++++------- -
drivers/fpga/fpga.c | 8 ++++++++
include/fpga.h | 2 ++4 files changed, 41 insertions(+), 9 deletions(-)cmd/fpga.c +0
-0@@ -363,7 +363,7 @@ U_BOOT_CMD(fpga, 6, 1, do_fpga,"(Xilinx only)\n"
#endif
#ifdefined(CONFIG_CMD_FPGA_LOADFS)cmd/fpga.c +0
-1- "Load device from filesystem (FAT by default) (Xilinxonly)\n"
cmd/fpga.c +1
-0+ "Load device from filesystem (FAT by default)\n"" loadfs [dev] [address] [image size] [blocksize] <interface>\n"
" [<dev[:part]>] <filename>\n" #endifdrivers/fpga/altera.c +0
-0@@ -23,25 +23,30 @@ static const struct altera_fpga { enum altera_family family; const char *name;int (*load)(Altera_desc *, const
void *,size_t);drivers/fpga/altera.c +1
-0+ int (*loadfs)(Altera_desc *, constvoid *,
size_t,drivers/fpga/altera.c +1
-0+ fpga_fs_info *);int (*dump)(Altera_desc *, const
void *,size_t);
int (*info)(Altera_desc *);
} altera_fpga[] = {
#ifdefined(CONFIG_FPGA_ACEX1K)drivers/fpga/altera.c +0
-1- { Altera_ACEX1K, "ACEX1K", ACEX1K_load, ACEX1K_dump,
ACEX1K_info},drivers/fpga/altera.c +0
-1- { Altera_CYC2, "ACEX1K", ACEX1K_load, ACEX1K_dump,
ACEX1K_info},drivers/fpga/altera.c +1
-0+ { Altera_ACEX1K, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
ACEX1K_info},drivers/fpga/altera.c +1
-0+ { Altera_CYC2, "ACEX1K", ACEX1K_load, NULL, ACEX1K_dump,
ACEX1K_info},
#elifdefined(CONFIG_FPGA_CYCLON2)drivers/fpga/altera.c +0
-1- { Altera_ACEX1K, "CycloneII", CYC2_load, CYC2_dump,
CYC2_info},drivers/fpga/altera.c +0
-1- { Altera_CYC2, "CycloneII", CYC2_load, CYC2_dump,
CYC2_info},drivers/fpga/altera.c +1
-0+ { Altera_ACEX1K, "CycloneII", CYC2_load, NULL, CYC2_dump,
CYC2_info},drivers/fpga/altera.c +1
-0+ { Altera_CYC2, "CycloneII", CYC2_load, NULL, CYC2_dump,
CYC2_info},
#endif
#ifdefined(CONFIG_FPGA_STRATIX_II)drivers/fpga/altera.c +1
-1- { Altera_StratixII, "StratixII", StratixII_load, + { Altera_StratixII, "StratixII", StratixII_load, NULL,StratixII_dump,
StratixII_info},
#endif
#ifdefined(CONFIG_FPGA_STRATIX_V)drivers/fpga/altera.c +0
-1- { Altera_StratixV,"StratixV" , stratixv_load,NULL ,NULL },
drivers/fpga/altera.c +1
-0+ { Altera_StratixV, "StratixV", stratixv_load, NULL, NULL,NULL },
#endifdrivers/fpga/altera.c +1
-2-#if defined(CONFIG_FPGA_SOCFPGA) - { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL }, +#if defined(CONFIG_FPGA_SOCFPGA) &&!defined(CONFIG_CMD_FPGA_LOADFS)
drivers/fpga/altera.c +1
-0+ { Altera_SoCFPGA, "SoC FPGA", socfpga_load, NULL, NULL,NULL },
drivers/fpga/altera.c +2
-0+#endif +#if defined(CONFIG_FPGA_SOCFPGA) &&
defined(CONFIG_CMD_FPGA_LOADFS)drivers/fpga/altera.c +1
-0+ { Altera_SoCFPGA, "SoC FPGA", socfpga_load,
socfpga_loadfs, NULL, NULL },
#endif
};drivers/fpga/altera.c +0
-0@@ -174,3 +179,20 @@ int altera_info(Altera_desc *desc)
returnFPGA_SUCCESS;
}drivers/fpga/altera.c +3
-0+ +#if defined(CONFIG_CMD_FPGA_LOADFS ) +int altera_loadfs(Altera_desc *desc, const void *buf, size_tbsize,
drivers/fpga/altera.c +3
-0+ fpga_fs_info *fpga_fsinfo) +{ + const struct altera_fpga *fpga = altera_desc_to_fpga(desc,
__func__);drivers/fpga/altera.c +5
-0+ +if (!fpga) +return FPGA_FAIL ; + + debug_cond(FPGA_DEBUG, "%s: Launching the %s FSLoader...\n",
drivers/fpga/altera.c +3
-0+ __func__, fpga->name); +if (fpga->loadfs) + return fpga->loadfs(desc, buf, bsize,
fpga_fsinfo);drivers/fpga/altera.c +3
-0+ return 0; +} +#endif drivers/fpga/fpga.c +0
-0@@ -198,6 +198,14 @@ int fpga_fsload(int devnum, const void *buf, size_t size,
fpga_no_sup((char *)__func__, "Xilinx devices");
#endif
break;
Quoted 9 lines
drivers/fpga/fpga.c int fpga_fsload(int devnum, const void *buf, size_t size, · line 204
Quoted 5 lines
drivers/fpga/fpga.c +3
-0+#if defined(CONFIG_FPGA_ALTERA ) +case fpga_altera: + ret_val = altera_loadfs(desc->devdesc,buf, size,
drivers/fpga/fpga.c +1
-0+ fpga_fsinfo);Why is this not a generic code ? Load stuff from FS and program it into
the FPGA directly, should be pretty generic operation IMO.
This is generic multiplexing code, calling generic function name fpga_fsload will lead to repective FPGA driver.
Quoted 27 lines
Quoted 26 lines
drivers/fpga/fpga.c +2
-0+#else + fpga_no_sup((char *)__func__, "Alteradevices");
drivers/fpga/fpga.c +2
-0+#endif +break ;default:
printf("%s: Invalid or unsupported device type %d\n",
__func__,desc->devtype);include/fpga.h +2
-0@@ -56,8 +56,10 @@ int fpga_count(void); const fpga_desc *const fpga_get_desc(int devnum); int fpga_load(int devnum, const void *buf, size_t bsize, bitstream_type bstype); +#if defined(CONFIG_CMD_FPGA_LOADFS ) int fpga_fsload(int devnum, const void *buf, size_t size, fpga_fs_info *fpga_fsinfo); +#endif int fpga_loadbitstream(int devnum, char *fpgadata, size_t size, bitstream_type bstype); int fpga_dump(int devnum, const void *buf, size_t bsize);
PATCH 4/19 arm: socfpga: Add FPGA loadfs command support
Quoted 8 lines · Tien Fong
Quoted 7 lines · Marek Vasut
Quoted 6 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This patch enables FPGA loadfs command support to U-boot console.
Signed-off-by Tien Fong Chee <[email protected]>
Quoted 8 lines
Quoted 3 lines
But you enabled support for this in patch 1/19 ... ordering issue ? Patch changelog doesn't match what the patch does ...
This patch is adding the FPGA loadfs command support for Arria 10. I enabled FPGA loadfs in patch 1/19, so i can compile the changes in this patch immediately.
So, you want me to improve the commit message and reordering?
Yes
Signature · 2 lines
Best regards, Marek Vasut
PATCH 5/19 arm: socfpga: Enhance FPGA program support with at least 4 byte data
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
This patch enables FPGA program with minimum 4 byte data size.
--- drivers/fpga/socfpga.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-)
drivers/fpga/socfpga.c +8 -6
@@ -1,5 +1,5 @@/* -* Copyright (C) 2012 Altera Corporation <www.altera.com> +* Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause
@@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)uint32_t loops4 =DIV_ROUND_UP (rbf_size %32 ,4 ); asmvolatile ( +" cmp %2, #0\n" +" beq 2f\n" "1: ldmia %0!, {r0-r7}\n" " stmia %1!, {r0-r7}\n" " sub %1, #32\n" " subs %2, #1\n" " bne 1b\n" -" cmp %3, #0\n" -" beq 3f\n" -"2: ldr %2, [%0], #4\n" +"2: cmp %3, #0\n" +" beq 4f\n" +"3: ldr %2, [%0], #4\n" " str %2, [%1]\n" " subs %3, #1\n" -" bne 2b\n" -"3: nop\n" +" bne 3b\n" +"4: nop\n" :"+r" (src),"+r" (dst),"+r" (loops32),"+r" (loops4) : :"r0" ,"r1" ,"r2" ,"r3" ,"r4" ,"r5" ,"r6" ,"r7" ,"cc" ); }
Signature · 1 line
1.7.7.4
PATCH 5/19 arm: socfpga: Enhance FPGA program support with at least 4 byte data
Quoted 3 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This patch enables FPGA program with minimum 4 byte data size.
What does that mean ? Expand the description, it's inobvious
Quoted 43 lines
Signed-off-by Tien Fong Chee <[email protected]>--- drivers/fpga/socfpga.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-)drivers/fpga/socfpga.c +8
-6@@ -1,5 +1,5 @@/* -* Copyright (C) 2012 Altera Corporation <www.altera.com> +* Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)uint32_t loops4 =DIV_ROUND_UP (rbf_size %32 ,4 ); asmvolatile ( +" cmp %2, #0\n" +" beq 2f\n" "1: ldmia %0!, {r0-r7}\n" " stmia %1!, {r0-r7}\n" " sub %1, #32\n" " subs %2, #1\n" " bne 1b\n" -" cmp %3, #0\n" -" beq 3f\n" -"2: ldr %2, [%0], #4\n" +"2: cmp %3, #0\n" +" beq 4f\n" +"3: ldr %2, [%0], #4\n" " str %2, [%1]\n" " subs %3, #1\n" -" bne 2b\n" -"3: nop\n" +" bne 3b\n" +"4: nop\n" :"+r" (src),"+r" (dst),"+r" (loops32),"+r" (loops4) : :"r0" ,"r1" ,"r2" ,"r3" ,"r4" ,"r5" ,"r6" ,"r7" ,"cc" ); }
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 5/19 arm: socfpga: Enhance FPGA program support with at least 4 byte data
Quoted 7 lines · Marek Vasut
Quoted 4 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This patch enables FPGA program with minimum 4 byte data size.
What does that mean ? Expand the description, it's inobvious
The exisitng FPGA program function only support the FPGA data which size is >= 32 bytes. For the size smaller than that, the operation would have failed.
Quoted 50 lines
Quoted 49 lines
Signed-off-by Tien Fong Chee <[email protected]>---
drivers/fpga/socfpga.c | 14 ++++++++------1 files changed, 8 insertions(+), 6 deletions(-)drivers/fpga/socfpga.c +1
-1@@ -1,5 +1,5 @@ /* -* Copyright (C) 2012 Altera Corporation <www.altera.com> +* Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size) uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
asm volatile(drivers/fpga/socfpga.c +2
-0+" cmp %2, #0\n" +" beq 2f\n" "1: ldmia %0!, {r0-r7}\n"
" stmia %1!, {r0-r7}\n"
" sub %1, #32\n"
" subs %2, #1\n"
" bne 1b\n"drivers/fpga/socfpga.c +0
-3-" cmp %3, #0\n" -" beq 3f\n" - "2: ldr %2, [%0], #4\n"
drivers/fpga/socfpga.c +3
-0+"2: cmp %3, #0\n" +" beq 4f\n" + "3: ldr %2, [%0], #4\n"
" str %2, [%1]\n"
" subs %3, #1\n"drivers/fpga/socfpga.c +2
-2-" bne 2b\n" -"3: nop\n" +" bne 3b\n" +"4: nop\n" : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", "cc");
}
PATCH 5/19 arm: socfpga: Enhance FPGA program support with at least 4 byte data
Quoted 11 lines · Tien Fong
Quoted 7 lines · Marek Vasut
Quoted 4 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
This patch enables FPGA program with minimum 4 byte data size.
What does that mean ? Expand the description, it's inobvious
The exisitng FPGA program function only support the FPGA data which size is >= 32 bytes. For the size smaller than that, the operation would have failed.
Because ... ?
And you fix it how ... ?
That should be in the commit message, describe the problem and how you fix it.
Quoted 49 lines
Quoted 49 lines
Quoted 49 lines
Signed-off-by Tien Fong Chee <[email protected]>--- drivers/fpga/socfpga.c | 14 ++++++++------ 1 files changed, 8 insertions(+), 6 deletions(-)drivers/fpga/socfpga.c +3
-4@@ -1,5 +1,5 @@/* -* Copyright (C) 2012 Altera Corporation <www.altera.com> +* Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size)uint32_t loops4 =DIV_ROUND_UP (rbf_size %32 ,4 ); asmvolatile ( +" cmp %2, #0\n" +" beq 2f\n" "1: ldmia %0!, {r0-r7}\n" " stmia %1!, {r0-r7}\n" " sub %1, #32\n" " subs %2, #1\n" " bne 1b\n" -" cmp %3, #0\n" -" beq 3f\n" - "2: ldr %2, [%0], #4\n"
drivers/fpga/socfpga.c +3
-0+"2: cmp %3, #0\n" +" beq 4f\n" + "3: ldr %2, [%0], #4\n"
drivers/fpga/socfpga.c +2
-2" str %2, [%1]\n" " subs %3, #1\n" -" bne 2b\n" -"3: nop\n" +" bne 3b\n" +"4: nop\n" : "+r"(src), "+r"(dst), "+r"(loops32),"+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"cc");
}
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 5/19 arm: socfpga: Enhance FPGA program support with at least 4 byte data
Quoted 15 lines · Marek Vasut
Quoted 6 lines · Tien Fong
Quoted 4 lines · Marek Vasut
Quoted 2 lines · tien.fong.chee at intel.com
Quoted 8 lines
Quoted 5 lines
Quoted 3 lines
From: Tien Fong Chee <[email protected]>
This patch enables FPGA program with minimum 4 byte data size.
What does that mean ? Expand the description, it's inobvious
The exisitng FPGA program function only support the FPGA data which size is >= 32 bytes. For the size smaller than that, the operation would have failed.
Quoted 8 lines
Because ... ?
And you fix it how ... ?
That should be in the commit message, describe the problem and how you
fix it.
Okay.
Quoted 56 lines
Quoted 55 lines
Quoted 55 lines
Quoted 55 lines
Signed-off-by Tien Fong Chee <[email protected]>---
drivers/fpga/socfpga.c | 14 ++++++++------1 files changed, 8 insertions(+), 6 deletions(-)drivers/fpga/socfpga.c +1
-1@@ -1,5 +1,5 @@ /* -* Copyright (C) 2012 Altera Corporation <www.altera.com> +* Copyright (C) 2012-2017 Altera Corporation <www.altera.com> * All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause @@ -55,18 +55,20 @@ void fpgamgr_program_write(const void *rbf_data, size_t rbf_size) uint32_t loops4 = DIV_ROUND_UP(rbf_size % 32, 4);
asm volatile(drivers/fpga/socfpga.c +2
-0+" cmp %2, #0\n" +" beq 2f\n" "1: ldmia %0!, {r0-r7}\n"
" stmia %1!, {r0-r7}\n"
" sub %1, #32\n"
" subs %2, #1\n"
" bne 1b\n"drivers/fpga/socfpga.c +0
-3-" cmp %3, #0\n" -" beq 3f\n" - "2: ldr %2, [%0],#4\n
"drivers/fpga/socfpga.c +3
-0+"2: cmp %3, #0\n" +" beq 4f\n" + "3: ldr %2, [%0],#4\n
"
" str %2, [%1]\n"
" subs %3, #1\n"drivers/fpga/socfpga.c +2
-2-" bne 2b\n" -"3: nop\n" +" bne 3b\n" +"4: nop\n" : "+r"(src), "+r"(dst), "+r"(loops32), "+r"(loops4) :
: "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"cc");
}
PATCH 6/19 arm: socfpga: Rename the gen5 sdram driver to more specific name
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
Current sdram driver is only applied to gen5 device, hence it is better to rename sdram driver to more specific name which is related to gen5 device.
---
arch/arm/mach-socfpga/include/mach/sdram.h | 436 +-------------------
.../include/mach/{sdram.h => sdram_gen5.h} | 6 +-
drivers/ddr/altera/Makefile | 2 +-
drivers/ddr/altera/{sdram.c => sdram_gen5.c} | 0
4 files changed, 9 insertions(+), 435 deletions(-)
copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%)
rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)arch/arm/mach-socfpga/include/mach/sdram.h +5 -431
@@ -1,442 +1,16 @@/* -* Copyright Altera Corporation (C) 2014-2015 +* Copyright (C) 2017 Intel Corporation <www.intel.com> * -* SPDX-License-Identifier: GPL-2.0+ +* SPDX-License-Identifier: GPL-2.0 */ #ifndef _SDRAM_H_#define _SDRAM_H_#ifndef __ASSEMBLY__ -unsigned long sdram_calculate_size (void ); -int sdram_mmr_init_full (unsigned int sdr_phy_reg); -int sdram_calibration_full (void ); - -const struct socfpga_sdram_config *socfpga_get_sdram_config (void ); - -void socfpga_get_seq_ac_init (const u32 **init,unsigned int *nelem); -void socfpga_get_seq_inst_init (const u32 **init,unsigned int *nelem); -const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config (void ); -const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config (void ); -const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config (void ); - -#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) - -struct socfpga_sdr_ctrl { -u32 ctrl_cfg; -u32 dram_timing1; -u32 dram_timing2; -u32 dram_timing3; -u32 dram_timing4;/* 0x10 */ -u32 lowpwr_timing; -u32 dram_odt; -u32 extratime1; -u32 __padding0[3 ]; -u32 dram_addrw;/* 0x2c */ -u32 dram_if_width;/* 0x30 */ -u32 dram_dev_width; -u32 dram_sts; -u32 dram_intr; -u32 sbe_count;/* 0x40 */ -u32 dbe_count; -u32 err_addr; -u32 drop_count; -u32 drop_addr;/* 0x50 */ -u32 lowpwr_eq; -u32 lowpwr_ack; -u32 static_cfg; -u32 ctrl_width;/* 0x60 */ -u32 cport_width; -u32 cport_wmap; -u32 cport_rmap; -u32 rfifo_cmap;/* 0x70 */ -u32 wfifo_cmap; -u32 cport_rdwr; -u32 port_cfg; -u32 fpgaport_rst;/* 0x80 */ -u32 __padding1; -u32 fifo_cfg; -u32 protport_default; -u32 prot_rule_addr;/* 0x90 */ -u32 prot_rule_id; -u32 prot_rule_data; -u32 prot_rule_rdwr; -u32 __padding2[3 ]; -u32 mp_priority;/* 0xac */ -u32 mp_weight0;/* 0xb0 */ -u32 mp_weight1; -u32 mp_weight2; -u32 mp_weight3; -u32 mp_pacing0;/* 0xc0 */ -u32 mp_pacing1; -u32 mp_pacing2; -u32 mp_pacing3; -u32 mp_threshold0;/* 0xd0 */ -u32 mp_threshold1; -u32 mp_threshold2; -u32 __padding3[29 ]; -u32 phy_ctrl0;/* 0x150 */ -u32 phy_ctrl1; -u32 phy_ctrl2; -}; - -/* SDRAM configuration structure for the SPL. */ -struct socfpga_sdram_config { -u32 ctrl_cfg; -u32 dram_timing1; -u32 dram_timing2; -u32 dram_timing3; -u32 dram_timing4; -u32 lowpwr_timing; -u32 dram_odt; -u32 extratime1; -u32 dram_addrw; -u32 dram_if_width; -u32 dram_dev_width; -u32 dram_intr; -u32 lowpwr_eq; -u32 static_cfg; -u32 ctrl_width; -u32 cport_width; -u32 cport_wmap; -u32 cport_rmap; -u32 rfifo_cmap; -u32 wfifo_cmap; -u32 cport_rdwr; -u32 port_cfg; -u32 fpgaport_rst; -u32 fifo_cfg; -u32 mp_priority; -u32 mp_weight0; -u32 mp_weight1; -u32 mp_weight2; -u32 mp_weight3; -u32 mp_pacing0; -u32 mp_pacing1; -u32 mp_pacing2; -u32 mp_pacing3; -u32 mp_threshold0; -u32 mp_threshold1; -u32 mp_threshold2; -u32 phy_ctrl0; -}; - -struct socfpga_sdram_rw_mgr_config { -u8 activate_0_and_1; -u8 activate_0_and_1_wait1; -u8 activate_0_and_1_wait2; -u8 activate_1; -u8 clear_dqs_enable; -u8 guaranteed_read; -u8 guaranteed_read_cont; -u8 guaranteed_write; -u8 guaranteed_write_wait0; -u8 guaranteed_write_wait1; -u8 guaranteed_write_wait2; -u8 guaranteed_write_wait3; -u8 idle; -u8 idle_loop1; -u8 idle_loop2; -u8 init_reset_0_cke_0; -u8 init_reset_1_cke_0; -u8 lfsr_wr_rd_bank_0; -u8 lfsr_wr_rd_bank_0_data; -u8 lfsr_wr_rd_bank_0_dqs; -u8 lfsr_wr_rd_bank_0_nop; -u8 lfsr_wr_rd_bank_0_wait; -u8 lfsr_wr_rd_bank_0_wl_1; -u8 lfsr_wr_rd_dm_bank_0; -u8 lfsr_wr_rd_dm_bank_0_data; -u8 lfsr_wr_rd_dm_bank_0_dqs; -u8 lfsr_wr_rd_dm_bank_0_nop; -u8 lfsr_wr_rd_dm_bank_0_wait; -u8 lfsr_wr_rd_dm_bank_0_wl_1; -u8 mrs0_dll_reset; -u8 mrs0_dll_reset_mirr; -u8 mrs0_user; -u8 mrs0_user_mirr; -u8 mrs1; -u8 mrs1_mirr; -u8 mrs2; -u8 mrs2_mirr; -u8 mrs3; -u8 mrs3_mirr; -u8 precharge_all; -u8 read_b2b; -u8 read_b2b_wait1; -u8 read_b2b_wait2; -u8 refresh_all; -u8 rreturn; -u8 sgle_read; -u8 zqcl; - -u8 true_mem_data_mask_width; -u8 mem_address_mirroring; -u8 mem_data_mask_width; -u8 mem_data_width; -u8 mem_dq_per_read_dqs; -u8 mem_dq_per_write_dqs; -u8 mem_if_read_dqs_width; -u8 mem_if_write_dqs_width; -u8 mem_number_of_cs_per_dimm; -u8 mem_number_of_ranks; -u8 mem_virtual_groups_per_read_dqs; -u8 mem_virtual_groups_per_write_dqs; -}; - -struct socfpga_sdram_io_config { -u16 delay_per_opa_tap; -u8 delay_per_dchain_tap; -u8 delay_per_dqs_en_dchain_tap; -u8 dll_chain_length; -u8 dqdqs_out_phase_max; -u8 dqs_en_delay_max; -u8 dqs_en_delay_offset; -u8 dqs_en_phase_max; -u8 dqs_in_delay_max; -u8 dqs_in_reserve; -u8 dqs_out_reserve; -u8 io_in_delay_max; -u8 io_out1_delay_max; -u8 io_out2_delay_max; -u8 shift_dqs_en_when_shift_dqs; -}; - -struct socfpga_sdram_misc_config { -u32 reg_file_init_seq_signature; -u8 afi_rate_ratio; -u8 calib_lfifo_offset; -u8 calib_vfifo_offset; -u8 enable_super_quick_calibration; -u8 max_latency_count_width; -u8 read_valid_fifo_size; -u8 tinit_cntr0_val; -u8 tinit_cntr1_val; -u8 tinit_cntr2_val; -u8 treset_cntr0_val; -u8 treset_cntr1_val; -u8 treset_cntr2_val; -}; - -#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 -#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 -#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 -#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 -#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 -#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 -#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 -#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 -#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 -#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 -#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 -#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 -#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 -#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 -#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 -#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 -#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 -#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 -/* Register template: sdr::ctrlgrp::dramtiming1 */ -#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 -#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 -#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 -#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 -#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 -#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 -#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 -#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 -#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 -#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 -#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramtiming2 */ -#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 -#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 -#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 -#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 -#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 -#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 -#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 -#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 -#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff -/* Register template: sdr::ctrlgrp::dramtiming3 */ -#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 -#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 -#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 -#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 -#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 -#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 -#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 -#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 -#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramtiming4 */ -#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 -#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 -#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 -#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 -#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::lowpwrtiming */ -#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 -#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 -#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 -#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff -/* Register template: sdr::ctrlgrp::dramaddrw */ -#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 -#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 -#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 -#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 -#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 -#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 -#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 -#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f -/* Register template: sdr::ctrlgrp::dramifwidth */ -#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 -#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff -/* Register template: sdr::ctrlgrp::dramdevwidth */ -#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 -#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramintr */ -#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 -#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 -#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 -#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 -/* Register template: sdr::ctrlgrp::staticcfg */ -#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 -#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 -#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 -#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 -#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 -#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 -/* Register template: sdr::ctrlgrp::ctrlwidth */ -#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 -#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 -/* Register template: sdr::ctrlgrp::cportwidth */ -#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 -#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff -/* Register template: sdr::ctrlgrp::cportwmap */ -#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 -#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::cportrmap */ -#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 -#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::rfifocmap */ -#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 -#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::wfifocmap */ -#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 -#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::cportrdwr */ -#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 -#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff -/* Register template: sdr::ctrlgrp::portcfg */ -#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 -#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 -#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 -#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::fifocfg */ -#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 -#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 -#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 -#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::mppriority */ -#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 -#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ -0xffffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ -0xffffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ -0x0000ffff -/* Register template: sdr::ctrlgrp::remappriority */ -#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 -#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET (x) \ - (((x) << 12) & 0xfffff000) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET (x) \ - (((x) << 10) & 0x00000c00) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET (x) \ - (((x) << 6) & 0x000000c0) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET (x) \ - (((x) << 8) & 0x00000100) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET (x) \ - (((x) << 9) & 0x00000200) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET (x) \ - (((x) << 4) & 0x00000030) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET (x) \ - (((x) << 2) & 0x0000000c) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET (x) \ - (((x) << 0) & 0x00000003) -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET (x) \ - (((x) << 12) & 0xfffff000) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET (x) \ - (((x) << 0) & 0x00000fff) -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET (x) \ - (((x) << 0) & 0x00000fff) -/* Register template: sdr::ctrlgrp::dramodt */ -#define SDR_CTRLGRP_DRAMODT_READ_LSB 4 -#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 -#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 -#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f -/* Field instance: sdr::ctrlgrp::dramsts */ -#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 -#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 -/* Register template: sdr::ctrlgrp::extratime1 */ -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20 -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24 -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28 - -/* SDRAM width macro for configuration with ECC */ -#define SDRAM_WIDTH_32BIT_WITH_ECC 40 -#define SDRAM_WIDTH_16BIT_WITH_ECC 24 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5 ) +#include <asm/arch/sdram_gen5.h> +#endif #endif #endif /* _SDRAM_H_ */
arch/arm/mach-socfpga/include/mach/sdram_gen5.h renamed from arch/arm/mach-socfpga/include/mach/sdram.h +3 -3
@@ -3,8 +3,8 @@* * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _SDRAM_H_ -#define _SDRAM_H_ +#ifndef _SOCFPGA_SDRAM_GEN5_H_ +#define _SOCFPGA_SDRAM_GEN5_H_#ifndef __ASSEMBLY__
@@ -439,4 +439,4 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \#define SDRAM_WIDTH_16BIT_WITH_ECC 24#endif -#endif /* _SDRAM_H_ */ +#endif /* _SOCFPGA_SDRAM_GEN5_H_ */
drivers/ddr/altera/Makefile +1 -1
@@ -9,5 +9,5 @@ # ifdef CONFIG_ALTERA_SDRAM -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o endif
drivers/ddr/altera/sdram_gen5.c renamed from drivers/ddr/altera/sdram.c +0 -0
Signature · 1 line
1.7.7.4
Marek Vasut
NAKPATCH 6/19 arm: socfpga: Rename the gen5 sdram driver to more specific name
Quoted 21 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
Current sdram driver is only applied to gen5 device, hence it is better to rename sdram driver to more specific name which is related to gen5 device.
Signed-off-by Tien Fong Chee <[email protected]>--- arch/arm/mach-socfpga/include/mach/sdram.h | 436 +------------------- .../include/mach/{sdram.h => sdram_gen5.h} | 6 +- drivers/ddr/altera/Makefile | 2 +- drivers/ddr/altera/{sdram.c => sdram_gen5.c} | 0 4 files changed, 9 insertions(+), 435 deletions(-) copy arch/arm/mach-socfpga/include/mach/{sdram.h => sdram_gen5.h} (99%) rename drivers/ddr/altera/{sdram.c => sdram_gen5.c} (100%)arch/arm/mach-socfpga/include/mach/sdram.h +0
-0
arch/arm/mach-socfpga/include/mach/sdram.h line 4
Quoted 6 lines
arch/arm/mach-socfpga/include/mach/sdram.h +2
-2@@ -1,442 +1,16 @@/* -* Copyright Altera Corporation (C) 2014-2015 +* Copyright (C) 2017 Intel Corporation <www.intel.com> * -* SPDX-License-Identifier: GPL-2.0+ +* SPDX-License-Identifier: GPL-2.0
NAK, do NOT change the license.
Also, use git format-patch -M -C for renames
Quoted 481 lines
arch/arm/mach-socfpga/include/mach/sdram.h +3
-429*/ #ifndef _SDRAM_H_#define _SDRAM_H_#ifndef __ASSEMBLY__ -unsigned long sdram_calculate_size (void ); -int sdram_mmr_init_full (unsigned int sdr_phy_reg); -int sdram_calibration_full (void ); - -const struct socfpga_sdram_config *socfpga_get_sdram_config (void ); - -void socfpga_get_seq_ac_init (const u32 **init,unsigned int *nelem); -void socfpga_get_seq_inst_init (const u32 **init,unsigned int *nelem); -const struct socfpga_sdram_rw_mgr_config *socfpga_get_sdram_rwmgr_config (void ); -const struct socfpga_sdram_io_config *socfpga_get_sdram_io_config (void ); -const struct socfpga_sdram_misc_config *socfpga_get_sdram_misc_config (void ); - -#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) - -struct socfpga_sdr_ctrl { -u32 ctrl_cfg; -u32 dram_timing1; -u32 dram_timing2; -u32 dram_timing3; -u32 dram_timing4;/* 0x10 */ -u32 lowpwr_timing; -u32 dram_odt; -u32 extratime1; -u32 __padding0[3 ]; -u32 dram_addrw;/* 0x2c */ -u32 dram_if_width;/* 0x30 */ -u32 dram_dev_width; -u32 dram_sts; -u32 dram_intr; -u32 sbe_count;/* 0x40 */ -u32 dbe_count; -u32 err_addr; -u32 drop_count; -u32 drop_addr;/* 0x50 */ -u32 lowpwr_eq; -u32 lowpwr_ack; -u32 static_cfg; -u32 ctrl_width;/* 0x60 */ -u32 cport_width; -u32 cport_wmap; -u32 cport_rmap; -u32 rfifo_cmap;/* 0x70 */ -u32 wfifo_cmap; -u32 cport_rdwr; -u32 port_cfg; -u32 fpgaport_rst;/* 0x80 */ -u32 __padding1; -u32 fifo_cfg; -u32 protport_default; -u32 prot_rule_addr;/* 0x90 */ -u32 prot_rule_id; -u32 prot_rule_data; -u32 prot_rule_rdwr; -u32 __padding2[3 ]; -u32 mp_priority;/* 0xac */ -u32 mp_weight0;/* 0xb0 */ -u32 mp_weight1; -u32 mp_weight2; -u32 mp_weight3; -u32 mp_pacing0;/* 0xc0 */ -u32 mp_pacing1; -u32 mp_pacing2; -u32 mp_pacing3; -u32 mp_threshold0;/* 0xd0 */ -u32 mp_threshold1; -u32 mp_threshold2; -u32 __padding3[29 ]; -u32 phy_ctrl0;/* 0x150 */ -u32 phy_ctrl1; -u32 phy_ctrl2; -}; - -/* SDRAM configuration structure for the SPL. */ -struct socfpga_sdram_config { -u32 ctrl_cfg; -u32 dram_timing1; -u32 dram_timing2; -u32 dram_timing3; -u32 dram_timing4; -u32 lowpwr_timing; -u32 dram_odt; -u32 extratime1; -u32 dram_addrw; -u32 dram_if_width; -u32 dram_dev_width; -u32 dram_intr; -u32 lowpwr_eq; -u32 static_cfg; -u32 ctrl_width; -u32 cport_width; -u32 cport_wmap; -u32 cport_rmap; -u32 rfifo_cmap; -u32 wfifo_cmap; -u32 cport_rdwr; -u32 port_cfg; -u32 fpgaport_rst; -u32 fifo_cfg; -u32 mp_priority; -u32 mp_weight0; -u32 mp_weight1; -u32 mp_weight2; -u32 mp_weight3; -u32 mp_pacing0; -u32 mp_pacing1; -u32 mp_pacing2; -u32 mp_pacing3; -u32 mp_threshold0; -u32 mp_threshold1; -u32 mp_threshold2; -u32 phy_ctrl0; -}; - -struct socfpga_sdram_rw_mgr_config { -u8 activate_0_and_1; -u8 activate_0_and_1_wait1; -u8 activate_0_and_1_wait2; -u8 activate_1; -u8 clear_dqs_enable; -u8 guaranteed_read; -u8 guaranteed_read_cont; -u8 guaranteed_write; -u8 guaranteed_write_wait0; -u8 guaranteed_write_wait1; -u8 guaranteed_write_wait2; -u8 guaranteed_write_wait3; -u8 idle; -u8 idle_loop1; -u8 idle_loop2; -u8 init_reset_0_cke_0; -u8 init_reset_1_cke_0; -u8 lfsr_wr_rd_bank_0; -u8 lfsr_wr_rd_bank_0_data; -u8 lfsr_wr_rd_bank_0_dqs; -u8 lfsr_wr_rd_bank_0_nop; -u8 lfsr_wr_rd_bank_0_wait; -u8 lfsr_wr_rd_bank_0_wl_1; -u8 lfsr_wr_rd_dm_bank_0; -u8 lfsr_wr_rd_dm_bank_0_data; -u8 lfsr_wr_rd_dm_bank_0_dqs; -u8 lfsr_wr_rd_dm_bank_0_nop; -u8 lfsr_wr_rd_dm_bank_0_wait; -u8 lfsr_wr_rd_dm_bank_0_wl_1; -u8 mrs0_dll_reset; -u8 mrs0_dll_reset_mirr; -u8 mrs0_user; -u8 mrs0_user_mirr; -u8 mrs1; -u8 mrs1_mirr; -u8 mrs2; -u8 mrs2_mirr; -u8 mrs3; -u8 mrs3_mirr; -u8 precharge_all; -u8 read_b2b; -u8 read_b2b_wait1; -u8 read_b2b_wait2; -u8 refresh_all; -u8 rreturn; -u8 sgle_read; -u8 zqcl; - -u8 true_mem_data_mask_width; -u8 mem_address_mirroring; -u8 mem_data_mask_width; -u8 mem_data_width; -u8 mem_dq_per_read_dqs; -u8 mem_dq_per_write_dqs; -u8 mem_if_read_dqs_width; -u8 mem_if_write_dqs_width; -u8 mem_number_of_cs_per_dimm; -u8 mem_number_of_ranks; -u8 mem_virtual_groups_per_read_dqs; -u8 mem_virtual_groups_per_write_dqs; -}; - -struct socfpga_sdram_io_config { -u16 delay_per_opa_tap; -u8 delay_per_dchain_tap; -u8 delay_per_dqs_en_dchain_tap; -u8 dll_chain_length; -u8 dqdqs_out_phase_max; -u8 dqs_en_delay_max; -u8 dqs_en_delay_offset; -u8 dqs_en_phase_max; -u8 dqs_in_delay_max; -u8 dqs_in_reserve; -u8 dqs_out_reserve; -u8 io_in_delay_max; -u8 io_out1_delay_max; -u8 io_out2_delay_max; -u8 shift_dqs_en_when_shift_dqs; -}; - -struct socfpga_sdram_misc_config { -u32 reg_file_init_seq_signature; -u8 afi_rate_ratio; -u8 calib_lfifo_offset; -u8 calib_vfifo_offset; -u8 enable_super_quick_calibration; -u8 max_latency_count_width; -u8 read_valid_fifo_size; -u8 tinit_cntr0_val; -u8 tinit_cntr1_val; -u8 tinit_cntr2_val; -u8 treset_cntr0_val; -u8 treset_cntr1_val; -u8 treset_cntr2_val; -}; - -#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 -#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 -#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 -#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 -#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 -#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 -#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 -#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 -#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 -#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 -#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 -#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 -#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 -#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 -#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 -#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 -#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 -#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 -/* Register template: sdr::ctrlgrp::dramtiming1 */ -#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 -#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 -#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 -#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 -#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 -#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 -#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 -#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 -#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 -#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 -#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramtiming2 */ -#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 -#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 -#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 -#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 -#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 -#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 -#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 -#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 -#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff -/* Register template: sdr::ctrlgrp::dramtiming3 */ -#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 -#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 -#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 -#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 -#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 -#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 -#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 -#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 -#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramtiming4 */ -#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 -#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 -#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 -#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 -#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::lowpwrtiming */ -#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 -#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 -#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 -#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff -/* Register template: sdr::ctrlgrp::dramaddrw */ -#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 -#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 -#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 -#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 -#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 -#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 -#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 -#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f -/* Register template: sdr::ctrlgrp::dramifwidth */ -#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 -#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff -/* Register template: sdr::ctrlgrp::dramdevwidth */ -#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 -#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramintr */ -#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 -#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 -#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 -#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 -/* Register template: sdr::ctrlgrp::staticcfg */ -#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 -#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 -#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 -#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 -#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 -#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 -/* Register template: sdr::ctrlgrp::ctrlwidth */ -#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 -#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 -/* Register template: sdr::ctrlgrp::cportwidth */ -#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 -#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff -/* Register template: sdr::ctrlgrp::cportwmap */ -#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 -#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::cportrmap */ -#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 -#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::rfifocmap */ -#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 -#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::wfifocmap */ -#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 -#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::cportrdwr */ -#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 -#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff -/* Register template: sdr::ctrlgrp::portcfg */ -#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 -#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 -#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 -#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::fifocfg */ -#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 -#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 -#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 -#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::mppriority */ -#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 -#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_1 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK 0xfffc0000 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK 0x0003ffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_2 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_3 */ -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK 0x0003ffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_0 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_1 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK 0xf0000000 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK 0x0fffffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_2 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK 0xffffffff -/* Register template: sdr::ctrlgrp::mppacing::mppacing_3 */ -#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */ -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ -0xffffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */ -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ -0xffffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */ -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ -0x0000ffff -/* Register template: sdr::ctrlgrp::remappriority */ -#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 -#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */ -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET (x) \ - (((x) << 12) & 0xfffff000) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET (x) \ - (((x) << 10) & 0x00000c00) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET (x) \ - (((x) << 6) & 0x000000c0) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET (x) \ - (((x) << 8) & 0x00000100) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET (x) \ - (((x) << 9) & 0x00000200) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET (x) \ - (((x) << 4) & 0x00000030) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET (x) \ - (((x) << 2) & 0x0000000c) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET (x) \ - (((x) << 0) & 0x00000003) -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH 20 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET (x) \ - (((x) << 12) & 0xfffff000) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET (x) \ - (((x) << 0) & 0x00000fff) -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET (x) \ - (((x) << 0) & 0x00000fff) -/* Register template: sdr::ctrlgrp::dramodt */ -#define SDR_CTRLGRP_DRAMODT_READ_LSB 4 -#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 -#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 -#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f -/* Field instance: sdr::ctrlgrp::dramsts */ -#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 -#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 -/* Register template: sdr::ctrlgrp::extratime1 */ -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20 -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24 -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28 - -/* SDRAM width macro for configuration with ECC */ -#define SDRAM_WIDTH_32BIT_WITH_ECC 40 -#define SDRAM_WIDTH_16BIT_WITH_ECC 24 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5 ) +#include <asm/arch/sdram_gen5.h> +#endif #endif #endif /* _SDRAM_H_ */ arch/arm/mach-socfpga/include/mach/sdram_gen5.h renamed from arch/arm/mach-socfpga/include/mach/sdram.h +3
-3@@ -3,8 +3,8 @@* * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _SDRAM_H_ -#define _SDRAM_H_ +#ifndef _SOCFPGA_SDRAM_GEN5_H_ +#define _SOCFPGA_SDRAM_GEN5_H_#ifndef __ASSEMBLY__@@ -439,4 +439,4 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \#define SDRAM_WIDTH_16BIT_WITH_ECC 24#endif -#endif /* _SDRAM_H_ */ +#endif /* _SOCFPGA_SDRAM_GEN5_H_ */ drivers/ddr/altera/Makefile +1
-1@@ -9,5 +9,5 @@ # ifdef CONFIG_ALTERA_SDRAM -obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o endifdrivers/ddr/altera/sdram_gen5.c renamed from drivers/ddr/altera/sdram.c +0
-0
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 6/19 arm: socfpga: Rename the gen5 sdram driver to more specific name
Quoted 36 lines · Marek Vasut
Quoted 27 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
Current sdram driver is only applied to gen5 device, hence it is better
to rename sdram driver to more specific name which is related to gen5
device.Signed-off-by Tien Fong Chee <[email protected]>---
arch/arm/mach-socfpga/include/mach/sdram.h | 436 +-------
------------
.../include/mach/{sdram.h => sdram_gen5.h} | 6 +- drivers/ddr/altera/Makefile | 2 +-drivers/ddr/altera/{sdram.c=> sdram_gen5.c} | 04 files changed, 9 insertions(+), 435 deletions(-)copy
arch/arm/mach-socfpga/include/mach/{sdram.h=>sdram_gen5.h} (99%)
renamedrivers/ddr/altera/{sdram.c=>sdram_gen5.c} (100%)arch/arm/mach-socfpga/include/mach/sdram.h +0
-0arch/arm/mach-socfpga/include/mach/sdram.h line 4
Quoted 6 lines
arch/arm/mach-socfpga/include/mach/sdram.h +2
-2@@ -1,442 +1,16 @@ /* -* Copyright Altera Corporation (C) 2014-2015 +* Copyright (C) 2017 Intel Corporation <www.intel.com> * -* SPDX-License-Identifier: GPL-2.0+ +* SPDX-License-Identifier: GPL-2.0 NAK, do NOT change the license.
Quoted 2 lines
Also, use git format-patch -M -C for renames
Okay.
Quoted 543 lines
Quoted 542 lines
arch/arm/mach-socfpga/include/mach/sdram.h +0
-0*/ #ifndef _SDRAM_H_ #define _SDRAM_H_
#ifndef__ASSEMBLY__arch/arm/mach-socfpga/include/mach/sdram.h +0
-7-unsigned long sdram_calculate_size (void ); -int sdram_mmr_init_full (unsigned int sdr_phy_reg); -int sdram_calibration_full (void ); - -const struct socfpga_sdram_config *socfpga_get_sdram_config (void ); - -void socfpga_get_seq_ac_init(const u32 **init, unsigned int*nelem);
-voidsocfpga_get_seq_inst_init(const u32 **init, unsigned int *nelem);
-const structsocfpga_sdram_rw_mgr_config*socfpga_get_sdram_rwmgr_config(void);
-const structsocfpga_sdram_io_config*socfpga_get_sdram_io_config(void);
-const structsocfpga_sdram_misc_config*socfpga_get_sdram_misc_config(void);arch/arm/mach-socfpga/include/mach/sdram.h +0
-218- -#define SDR_CTRLGRP_ADDRESS (SOCFPGA_SDR_ADDRESS | 0x5000) - -struct socfpga_sdr_ctrl { -u32 ctrl_cfg; -u32 dram_timing1; -u32 dram_timing2; -u32 dram_timing3; -u32 dram_timing4;/* 0x10 */ -u32 lowpwr_timing; -u32 dram_odt; -u32 extratime1; -u32 __padding0[3 ]; -u32 dram_addrw;/* 0x2c */ -u32 dram_if_width;/* 0x30 */ -u32 dram_dev_width; -u32 dram_sts; -u32 dram_intr; -u32 sbe_count;/* 0x40 */ -u32 dbe_count; -u32 err_addr; -u32 drop_count; -u32 drop_addr;/* 0x50 */ -u32 lowpwr_eq; -u32 lowpwr_ack; -u32 static_cfg; -u32 ctrl_width;/* 0x60 */ -u32 cport_width; -u32 cport_wmap; -u32 cport_rmap; -u32 rfifo_cmap;/* 0x70 */ -u32 wfifo_cmap; -u32 cport_rdwr; -u32 port_cfg; -u32 fpgaport_rst;/* 0x80 */ -u32 __padding1; -u32 fifo_cfg; -u32 protport_default; -u32 prot_rule_addr;/* 0x90 */ -u32 prot_rule_id; -u32 prot_rule_data; -u32 prot_rule_rdwr; -u32 __padding2[3 ]; -u32 mp_priority;/* 0xac */ -u32 mp_weight0;/* 0xb0 */ -u32 mp_weight1; -u32 mp_weight2; -u32 mp_weight3; -u32 mp_pacing0;/* 0xc0 */ -u32 mp_pacing1; -u32 mp_pacing2; -u32 mp_pacing3; -u32 mp_threshold0;/* 0xd0 */ -u32 mp_threshold1; -u32 mp_threshold2; -u32 __padding3[29 ]; -u32 phy_ctrl0;/* 0x150 */ -u32 phy_ctrl1; -u32 phy_ctrl2; -}; - -/* SDRAM configuration structure for the SPL. */ -struct socfpga_sdram_config { -u32 ctrl_cfg; -u32 dram_timing1; -u32 dram_timing2; -u32 dram_timing3; -u32 dram_timing4; -u32 lowpwr_timing; -u32 dram_odt; -u32 extratime1; -u32 dram_addrw; -u32 dram_if_width; -u32 dram_dev_width; -u32 dram_intr; -u32 lowpwr_eq; -u32 static_cfg; -u32 ctrl_width; -u32 cport_width; -u32 cport_wmap; -u32 cport_rmap; -u32 rfifo_cmap; -u32 wfifo_cmap; -u32 cport_rdwr; -u32 port_cfg; -u32 fpgaport_rst; -u32 fifo_cfg; -u32 mp_priority; -u32 mp_weight0; -u32 mp_weight1; -u32 mp_weight2; -u32 mp_weight3; -u32 mp_pacing0; -u32 mp_pacing1; -u32 mp_pacing2; -u32 mp_pacing3; -u32 mp_threshold0; -u32 mp_threshold1; -u32 mp_threshold2; -u32 phy_ctrl0; -}; - -struct socfpga_sdram_rw_mgr_config { -u8 activate_0_and_1; -u8 activate_0_and_1_wait1; -u8 activate_0_and_1_wait2; -u8 activate_1; -u8 clear_dqs_enable; -u8 guaranteed_read; -u8 guaranteed_read_cont; -u8 guaranteed_write; -u8 guaranteed_write_wait0; -u8 guaranteed_write_wait1; -u8 guaranteed_write_wait2; -u8 guaranteed_write_wait3; -u8 idle; -u8 idle_loop1; -u8 idle_loop2; -u8 init_reset_0_cke_0; -u8 init_reset_1_cke_0; -u8 lfsr_wr_rd_bank_0; -u8 lfsr_wr_rd_bank_0_data; -u8 lfsr_wr_rd_bank_0_dqs; -u8 lfsr_wr_rd_bank_0_nop; -u8 lfsr_wr_rd_bank_0_wait; -u8 lfsr_wr_rd_bank_0_wl_1; -u8 lfsr_wr_rd_dm_bank_0; -u8 lfsr_wr_rd_dm_bank_0_data; -u8 lfsr_wr_rd_dm_bank_0_dqs; -u8 lfsr_wr_rd_dm_bank_0_nop; -u8 lfsr_wr_rd_dm_bank_0_wait; -u8 lfsr_wr_rd_dm_bank_0_wl_1; -u8 mrs0_dll_reset; -u8 mrs0_dll_reset_mirr; -u8 mrs0_user; -u8 mrs0_user_mirr; -u8 mrs1; -u8 mrs1_mirr; -u8 mrs2; -u8 mrs2_mirr; -u8 mrs3; -u8 mrs3_mirr; -u8 precharge_all; -u8 read_b2b; -u8 read_b2b_wait1; -u8 read_b2b_wait2; -u8 refresh_all; -u8 rreturn; -u8 sgle_read; -u8 zqcl; - -u8 true_mem_data_mask_width; -u8 mem_address_mirroring; -u8 mem_data_mask_width; -u8 mem_data_width; -u8 mem_dq_per_read_dqs; -u8 mem_dq_per_write_dqs; -u8 mem_if_read_dqs_width; -u8 mem_if_write_dqs_width; -u8 mem_number_of_cs_per_dimm; -u8 mem_number_of_ranks; -u8 mem_virtual_groups_per_read_dqs; -u8 mem_virtual_groups_per_write_dqs; -}; - -struct socfpga_sdram_io_config { -u16 delay_per_opa_tap; -u8 delay_per_dchain_tap; -u8 delay_per_dqs_en_dchain_tap; -u8 dll_chain_length; -u8 dqdqs_out_phase_max; -u8 dqs_en_delay_max; -u8 dqs_en_delay_offset; -u8 dqs_en_phase_max; -u8 dqs_in_delay_max; -u8 dqs_in_reserve; -u8 dqs_out_reserve; -u8 io_in_delay_max; -u8 io_out1_delay_max; -u8 io_out2_delay_max; -u8 shift_dqs_en_when_shift_dqs; -}; - -struct socfpga_sdram_misc_config { -u32 reg_file_init_seq_signature; -u8 afi_rate_ratio; -u8 calib_lfifo_offset; -u8 calib_vfifo_offset; -u8 enable_super_quick_calibration; -u8 max_latency_count_width; -u8 read_valid_fifo_size; -u8 tinit_cntr0_val; -u8 tinit_cntr1_val; -u8 tinit_cntr2_val; -u8 treset_cntr0_val; -u8 treset_cntr1_val; -u8 treset_cntr2_val; -}; - -#define SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB 23 -#define SDR_CTRLGRP_CTRLCFG_NODMPINS_MASK 0x00800000 -#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB 22 -#define SDR_CTRLGRP_CTRLCFG_DQSTRKEN_MASK 0x00400000 -#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB 16 -#define SDR_CTRLGRP_CTRLCFG_STARVELIMIT_MASK 0x003f0000 -#define SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB 15 -#define SDR_CTRLGRP_CTRLCFG_REORDEREN_MASK 0x00008000 -#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB 11 -#define SDR_CTRLGRP_CTRLCFG_ECCCORREN_MASK 0x00000800 -#define SDR_CTRLGRP_CTRLCFG_ECCEN_LSB 10 -#define SDR_CTRLGRP_CTRLCFG_ECCEN_MASK 0x00000400 -#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB 8 -#define SDR_CTRLGRP_CTRLCFG_ADDRORDER_MASK 0x00000300 -#define SDR_CTRLGRP_CTRLCFG_MEMBL_LSB 3 -#define SDR_CTRLGRP_CTRLCFG_MEMBL_MASK 0x000000f8 -#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB 0 -#define SDR_CTRLGRP_CTRLCFG_MEMTYPE_MASK 0x00000007 -/* Register template: sdr::ctrlgrp::dramtiming1 */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-13-#define SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB 24 -#define SDR_CTRLGRP_DRAMTIMING1_TRFC_MASK 0xff000000 -#define SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB 18 -#define SDR_CTRLGRP_DRAMTIMING1_TFAW_MASK 0x00fc0000 -#define SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB 14 -#define SDR_CTRLGRP_DRAMTIMING1_TRRD_MASK 0x0003c000 -#define SDR_CTRLGRP_DRAMTIMING1_TCL_LSB 9 -#define SDR_CTRLGRP_DRAMTIMING1_TCL_MASK 0x00003e00 -#define SDR_CTRLGRP_DRAMTIMING1_TAL_LSB 4 -#define SDR_CTRLGRP_DRAMTIMING1_TAL_MASK 0x000001f0 -#define SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING1_TCWL_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramtiming2 */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-11-#define SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB 25 -#define SDR_CTRLGRP_DRAMTIMING2_TWTR_MASK 0x1e000000 -#define SDR_CTRLGRP_DRAMTIMING2_TWR_LSB 21 -#define SDR_CTRLGRP_DRAMTIMING2_TWR_MASK 0x01e00000 -#define SDR_CTRLGRP_DRAMTIMING2_TRP_LSB 17 -#define SDR_CTRLGRP_DRAMTIMING2_TRP_MASK 0x001e0000 -#define SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB 13 -#define SDR_CTRLGRP_DRAMTIMING2_TRCD_MASK 0x0001e000 -#define SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING2_TREFI_MASK 0x00001fff -/* Register template: sdr::ctrlgrp::dramtiming3 */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-11-#define SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB 19 -#define SDR_CTRLGRP_DRAMTIMING3_TCCD_MASK 0x00780000 -#define SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB 15 -#define SDR_CTRLGRP_DRAMTIMING3_TMRD_MASK 0x00078000 -#define SDR_CTRLGRP_DRAMTIMING3_TRC_LSB 9 -#define SDR_CTRLGRP_DRAMTIMING3_TRC_MASK 0x00007e00 -#define SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB 4 -#define SDR_CTRLGRP_DRAMTIMING3_TRAS_MASK 0x000001f0 -#define SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING3_TRTP_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramtiming4 */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-7-#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_LSB 20 -#define SDR_CTRLGRP_DRAMTIMING4_MINPWRSAVECYCLES_MASK 0x00f00000 -#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB 10 -#define SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_MASK 0x000ffc00 -#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB 0 -#define SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::lowpwrtiming */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-5-#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB 16 -#define SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_MASK 0x000f0000 -#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB 0 -#define SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_MASK 0x0000ffff -/* Register template: sdr::ctrlgrp::dramaddrw */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-9-#define SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB 13 -#define SDR_CTRLGRP_DRAMADDRW_CSBITS_MASK 0x0000e000 -#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB 10 -#define SDR_CTRLGRP_DRAMADDRW_BANKBITS_MASK 0x00001c00 -#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB 5 -#define SDR_CTRLGRP_DRAMADDRW_ROWBITS_MASK 0x000003e0 -#define SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB 0 -#define SDR_CTRLGRP_DRAMADDRW_COLBITS_MASK 0x0000001f -/* Register template: sdr::ctrlgrp::dramifwidth */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB 0 -#define SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_MASK 0x000000ff -/* Register template: sdr::ctrlgrp::dramdevwidth */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB 0 -#define SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_MASK 0x0000000f -/* Register template: sdr::ctrlgrp::dramintr */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-5-#define SDR_CTRLGRP_DRAMINTR_INTREN_LSB 0 -#define SDR_CTRLGRP_DRAMINTR_INTREN_MASK 0x00000001 -#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB 4 -#define SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_MASK 0x00000030 -/* Register template: sdr::ctrlgrp::staticcfg */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-7-#define SDR_CTRLGRP_STATICCFG_APPLYCFG_LSB 3 -#define SDR_CTRLGRP_STATICCFG_APPLYCFG_MASK 0x00000008 -#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB 2 -#define SDR_CTRLGRP_STATICCFG_USEECCASDATA_MASK 0x00000004 -#define SDR_CTRLGRP_STATICCFG_MEMBL_LSB 0 -#define SDR_CTRLGRP_STATICCFG_MEMBL_MASK 0x00000003 -/* Register template: sdr::ctrlgrp::ctrlwidth */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB 0 -#define SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_MASK 0x00000003 -/* Register template: sdr::ctrlgrp::cportwidth */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB 0 -#define SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_MASK 0x000fffff -/* Register template: sdr::ctrlgrp::cportwmap */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB 0 -#define SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::cportrmap */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB 0 -#define SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::rfifocmap */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB 0 -#define SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::wfifocmap */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB 0 -#define SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_MASK 0x00ffffff -/* Register template: sdr::ctrlgrp::cportrdwr */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB 0 -#define SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_MASK 0x000fffff -/* Register template: sdr::ctrlgrp::portcfg */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-5-#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB 10 -#define SDR_CTRLGRP_PORTCFG_AUTOPCHEN_MASK 0x000ffc00 -#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_LSB 0 -#define SDR_CTRLGRP_PORTCFG_PORTPROTOCOL_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::fifocfg */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-5-#define SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB 10 -#define SDR_CTRLGRP_FIFOCFG_INCSYNC_MASK 0x00000400 -#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB 0 -#define SDR_CTRLGRP_FIFOCFG_SYNCMODE_MASK 0x000003ff -/* Register template: sdr::ctrlgrp::mppriority */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB 0 -#define SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_MASK 0x3fffffff -/* Register template: sdr::ctrlgrp::mpweight::mpweight_0 */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-2-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_MASK
0xffffffff
-/* Register template:
sdr::ctrlgrp::mpweight::mpweight_1 */arch/arm/mach-socfpga/include/mach/sdram.h +0
-2-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB 18 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_MASK
0xfffc0000arch/arm/mach-socfpga/include/mach/sdram.h +0
-2-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_MASK
0x0003ffff
-/* Register template:
sdr::ctrlgrp::mpweight::mpweight_2 */arch/arm/mach-socfpga/include/mach/sdram.h +0
-2-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_MASK
0xffffffff
-/* Register template:
sdr::ctrlgrp::mpweight::mpweight_3 */arch/arm/mach-socfpga/include/mach/sdram.h +0
-2-#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB 0 -#define SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_MASK
0x0003ffff
-/* Register template:
sdr::ctrlgrp::mppacing::mppacing_0 */arch/arm/mach-socfpga/include/mach/sdram.h +0
-2-#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_MASK
0xffffffff
-/* Register template:
sdr::ctrlgrp::mppacing::mppacing_1 */arch/arm/mach-socfpga/include/mach/sdram.h +0
-2-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB 28 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_MASK
0xf0000000arch/arm/mach-socfpga/include/mach/sdram.h +0
-2-#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_MASK
0x0fffffff
-/* Register template:
sdr::ctrlgrp::mppacing::mppacing_2 */arch/arm/mach-socfpga/include/mach/sdram.h +0
-2-#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_MASK
0xffffffff
-/* Register template:
sdr::ctrlgrp::mppacing::mppacing_3 */arch/arm/mach-socfpga/include/mach/sdram.h +0
-2-#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB 0 -#define SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_MASK
0x00ffffff
-/* Register template:
sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_0 */arch/arm/mach-socfpga/include/mach/sdram.h +0
-6-#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_MASK \ -0xffffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_1 */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-6-#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_MASK \ -0xffffffff -/* Register template: sdr::ctrlgrp::mpthresholdrst::mpthresholdrst_2 */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-6-#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB 0 -#define \ -SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ -0x0000ffff -/* Register template: sdr::ctrlgrp::remappriority */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_LSB 0 -#define SDR_CTRLGRP_REMAPPRIORITY_PRIORITYREMAP_MASK 0x000000ff -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_0 */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-19-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_LSB 12 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_WIDTH 20 -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_SAMPLECOUNT_19_0_SET (x) \ - (((x) << 12) & 0xfffff000) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ADDLATSEL_SET (x) \ - (((x) << 10) & 0x00000c00) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSLOGICDELAYEN_SET (x) \ - (((x) << 6) & 0x000000c0) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_RESETDELAYEN_SET (x) \ - (((x) << 8) & 0x00000100) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_LPDDRDIS_SET (x) \ - (((x) << 9) & 0x00000200) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQSDELAYEN_SET (x) \ - (((x) << 4) & 0x00000030) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_DQDELAYEN_SET (x) \ - (((x) << 2) & 0x0000000c) -#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_0_ACDELAYEN_SET (x) \ - (((x) << 0) & 0x00000003) -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_1 */ -#define
SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_WIDTH20 -#defineSDR_CTRLGRP_PHYCTRL_PHYCTRL_1_LONGIDLESAMPLECOUNT_19_0_SET(x)\
- (((x) << 12) &0xfffff000)arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_PHYCTRL_PHYCTRL_1_SAMPLECOUNT_31_20_SET (x) \ - (((x) << 0) & 0x00000fff) -/* Register template: sdr::ctrlgrp::phyctrl::phyctrl_2 */ -#define
SDR_CTRLGRP_PHYCTRL_PHYCTRL_2_LONGIDLESAMPLECOUNT_31_20_SET(x)\
- (((x) << 0) &0x00000fff)
-/* Register template:
sdr::ctrlgrp::dramodt */arch/arm/mach-socfpga/include/mach/sdram.h +0
-5-#define SDR_CTRLGRP_DRAMODT_READ_LSB 4 -#define SDR_CTRLGRP_DRAMODT_READ_MASK 0x000000f0 -#define SDR_CTRLGRP_DRAMODT_WRITE_LSB 0 -#define SDR_CTRLGRP_DRAMODT_WRITE_MASK 0x0000000f -/* Field instance: sdr::ctrlgrp::dramsts */
arch/arm/mach-socfpga/include/mach/sdram.h +0
-3-#define SDR_CTRLGRP_DRAMSTS_DBEERR_MASK 0x00000008 -#define SDR_CTRLGRP_DRAMSTS_SBEERR_MASK 0x00000004 -/* Register template: sdr::ctrlgrp::extratime1 */
arch/arm/mach-socfpga/include/mach/sdram.h +3
-7-#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB 20 -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB 24 -#define SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB 28 - -/* SDRAM width macro for configuration with ECC */ -#define SDRAM_WIDTH_32BIT_WITH_ECC 40 -#define SDRAM_WIDTH_16BIT_WITH_ECC 24 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5 ) +#include <asm/arch/sdram_gen5.h> +#endif
#endif
#endif /* _SDRAM_H_ */arch/arm/mach-socfpga/include/mach/sdram_gen5.h renamed from arch/arm/mach-socfpga/include/mach/sdram.h +2
-2@@ -3,8 +3,8 @@* * SPDX-License-Identifier: GPL-2.0+ */ -#ifndef _SDRAM_H_ -#define _SDRAM_H_ +#ifndef _SOCFPGA_SDRAM_GEN5_H_ +#define _SOCFPGA_SDRAM_GEN5_H_
#ifndef__ASSEMBLY__arch/arm/mach-socfpga/include/mach/sdram_gen5.h renamed from arch/arm/mach-socfpga/include/mach/sdram.h +0
-0@@ -439,4 +439,4 @@ SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_MASK \ #define SDRAM_WIDTH_16BIT_WITH_ECC 24
#endifarch/arm/mach-socfpga/include/mach/sdram_gen5.h renamed from arch/arm/mach-socfpga/include/mach/sdram.h +1
-1-#endif /* _SDRAM_H_ */ +#endif /* _SOCFPGA_SDRAM_GEN5_H_ */ drivers/ddr/altera/Makefile +0
-0@@ -9,5 +9,5 @@ #
ifdefCONFIG_ALTERA_SDRAMdrivers/ddr/altera/Makefile +1
-1-obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.oendif
drivers/ddr/altera/sdram_gen5.c renamed from drivers/ddr/altera/sdram.c +0
-0
PATCH 7/19 arm: socfpga: Add DRAM bank size initialization function
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
Add function for both multiple DRAM bank and single DRAM bank size initialization. This common functionality could be used by every single SOCFPGA board.
--- arch/arm/mach-socfpga/board.c | 12 ++++++++++++ include/configs/socfpga_common.h | 1 + 2 files changed, 13 insertions(+), 0 deletions(-)
arch/arm/mach-socfpga/board.c +12 -0
@@ -29,6 +29,18 @@ int board_init(void)return 0 ; } +int dram_init_banksize (void ) +{ +#if !defined(CONFIG_SYS_SDRAM_BASE ) && !defined(CONFIG_SYS_SDRAM_SIZE ) +fdtdec_setup_memory_banksize (); +#else + gd->bd->bi_dram[0 ].start =CONFIG_SYS_SDRAM_BASE ; + gd->bd->bi_dram[0 ].size =CONFIG_SYS_SDRAM_SIZE ; +#endif + +return 0 ; +} +#ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { .usb_gusbcfg = 0x1417,
include/configs/socfpga_common.h +1 -0
@@ -47,6 +47,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x08000040#else
Signature · 1 line
1.7.7.4
PATCH 7/19 arm: socfpga: Add DRAM bank size initialization function
Quoted 17 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
Add function for both multiple DRAM bank and single DRAM bank size initialization. This common functionality could be used by every single SOCFPGA board.
Signed-off-by Tien Fong Chee <[email protected]>--- arch/arm/mach-socfpga/board.c | 12 ++++++++++++ include/configs/socfpga_common.h | 1 + 2 files changed, 13 insertions(+), 0 deletions(-)arch/arm/mach-socfpga/board.c +0
-0
arch/arm/mach-socfpga/board.c int board_init(void) · line 35
Quoted 7 lines
arch/arm/mach-socfpga/board.c +4
-0@@ -29,6 +29,18 @@ int board_init(void)return 0 ; } +int dram_init_banksize (void ) +{ +#if !defined(CONFIG_SYS_SDRAM_BASE ) && !defined(CONFIG_SYS_SDRAM_SIZE ) +fdtdec_setup_memory_banksize ();
This should work on al boards, so why do you need this macro ? Also, this should go into arch/arm/ , not board/
Quoted 24 lines
arch/arm/mach-socfpga/board.c +8
-0+#else + gd->bd->bi_dram[0 ].start =CONFIG_SYS_SDRAM_BASE ; + gd->bd->bi_dram[0 ].size =CONFIG_SYS_SDRAM_SIZE ; +#endif + +return 0 ; +} +#ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = { .usb_gusbcfg = 0x1417,include/configs/socfpga_common.h +1
-0@@ -47,6 +47,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x08000040#else
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 7/19 arm: socfpga: Add DRAM bank size initialization function
Quoted 15 lines · Marek Vasut
Quoted 14 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
Add function for both multiple DRAM bank and single DRAM bank size initialization. This common functionality could be used by every single
SOCFPGA board.Signed-off-by Tien Fong Chee <[email protected]>---
arch/arm/mach-socfpga/board.c | 12 ++++++++++++include/configs/socfpga_common.h| 1 +2 files changed, 13 insertions(+), 0 deletions(-)
Quoted 17 lines
Quoted 13 lines
arch/arm/mach- renamed from arch/arm/mach-socfpga/board.c +0
-0
socfpga/board.c
index a41d089..3f2e30a 100644arch/arm/mach-socfpga/board.c +0
-0@@ -29,6 +29,18 @@ int board_init(void) return 0; }arch/arm/mach-socfpga/board.c +3
-0+int dram_init_banksize (void ) +{ +#if !defined(CONFIG_SYS_SDRAM_BASE) &&!defined(CONFIG_SYS_SDRAM_SIZE)
arch/arm/mach-socfpga/board.c int board_init(void) · line 35
Quoted 1 line
arch/arm/mach-socfpga/board.c +1
-0+fdtdec_setup_memory_banksize ();This should work on al boards, so why do you need this macro ? Also, this should go into
arch/arm/, not board/
In case these macros are not defined, then we need to get the info from DTS. This is in arch/arm/mach-socpfga/board.c . I found some in arch/arm, and other in board/ .
Quoted 27 lines
Quoted 26 lines
arch/arm/mach-socfpga/board.c +8
-0+#else + gd->bd->bi_dram[0 ].start =CONFIG_SYS_SDRAM_BASE ; + gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; +#endif + +return 0 ; +} +#ifdef
CONFIG_USB_GADGET
structdwc2_plat_otg_datasocfpga_otg_data= {
.usb_gusbcfg =0x1417,include/configs/socfpga_common.h +0
-0@@ -47,6 +47,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#defineCONFIG_SYS_SDRAM_BASEPHYS_SDRAM_1
+#defineCONFIG_SYS_SDRAM_SIZEPHYS_SDRAM_1_SIZE
#ifdefCONFIG_SOCFPGA_VIRTUAL_TARGET
#defineCONFIG_SYS_TEXT_BASE0x08000040
#else
PATCH 7/19 arm: socfpga: Add DRAM bank size initialization function
Quoted 33 lines · Tien Fong
Quoted 24 lines · Marek Vasut
Quoted 23 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
Add function for both multiple DRAM bank and single DRAM bank size initialization. This common functionality could be used by every single
SOCFPGA board.Signed-off-by Tien Fong Chee <[email protected]>--- arch/arm/mach-socfpga/board.c | 12 ++++++++++++ include/configs/socfpga_common.h | 1 + 2 files changed, 13 insertions(+), 0 deletions(-)arch/arm/mach- renamed from arch/arm/mach-socfpga/board.c +0
-0
socfpga/board.c
index a41d089..3f2e30a 100644arch/arm/mach-socfpga/board.c +0
-0@@ -29,6 +29,18 @@ int board_init(void)return 0 ; }Quoted 8 lines
arch/arm/mach-socfpga/board.c int board_init(void) · line 35
Quoted 5 lines
arch/arm/mach-socfpga/board.c +4
-0+int dram_init_banksize (void ) +{ +#if !defined(CONFIG_SYS_SDRAM_BASE ) && !defined(CONFIG_SYS_SDRAM_SIZE ) +fdtdec_setup_memory_banksize ();This should work on al boards, so why do you need this macro ? Also, this should go into
arch/arm/, not board/
Quoted 3 lines
In case these macros are not defined, then we need to get the info from DTS. This is in
arch/arm/mach-socpfga/board.c. I found some inarch/arm, and other in board/ .
Every socfpga platform in u-boot has a dts, so you can always extract the memory config from it and it's the preferred method.
Quoted 26 lines
Quoted 26 lines
Quoted 26 lines
arch/arm/mach-socfpga/board.c +8
-0+#else + gd->bd->bi_dram[0 ].start =CONFIG_SYS_SDRAM_BASE ; + gd->bd->bi_dram[0 ].size =CONFIG_SYS_SDRAM_SIZE ; +#endif + +return 0 ; +} +#ifdef CONFIG_USB_GADGET struct dwc2_plat_otg_data socfpga_otg_data = {arch/arm/mach-socfpga/board.c +0
-0.usb_gusbcfg = 0x1417,include/configs/socfpga_common.h +1
-0@@ -47,6 +47,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_SDRAM_SIZE PHYS_SDRAM_1_SIZE#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET #define CONFIG_SYS_TEXT_BASE 0x08000040#else
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 7/19 arm: socfpga: Add DRAM bank size initialization function
Quoted 39 lines · Marek Vasut
Quoted 38 lines · Tien Fong
Quoted 36 lines · Marek Vasut
Quoted 30 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every
single
SOCFPGA board.Signed-off-by Tien Fong Chee <[email protected]>---
arch/arm/mach-socfpga/board.c | 12 ++++++++++++include/configs/socfpga_common.h| 1 +2 files changed, 13 insertions(+), 0 deletions(-)arch/arm/mach- renamed from arch/arm/mach-socfpga/board.c +0
-0
socfpga/board.c
index a41d089..3f2e30a 100644arch/arm/mach-socfpga/board.c +0
-0@@ -29,6 +29,18 @@ int board_init(void) return 0; }arch/arm/mach-socfpga/board.c +3
-0+int dram_init_banksize (void ) +{ +#if !defined(CONFIG_SYS_SDRAM_BASE) &&!defined(CONFIG_SYS_SDRAM_SIZE)
arch/arm/mach-socfpga/board.c int board_init(void) · line 35
Quoted 1 line
arch/arm/mach-socfpga/board.c +1
-0+fdtdec_setup_memory_banksize ();This should work on al boards, so why do you need this macro ? Also, this should go into
arch/arm/, not board/
Quoted 7 lines
Quoted 4 lines
In case these macros are not defined, then we need to get the info from
DTS. This is inarch/arm/mach-socpfga/board.c. I found some inarch/arm, and other in board/ .Every socfpga platform in u-boot has a dts, so you can always extract the memory config from it and it's the preferred method.
This implementation supports both method, from header or DTS.
Quoted 30 lines
Quoted 29 lines
Quoted 29 lines
Quoted 29 lines
arch/arm/mach-socfpga/board.c +8
-0+#else + gd->bd->bi_dram[0 ].start =CONFIG_SYS_SDRAM_BASE ; + gd->bd->bi_dram[0].size = CONFIG_SYS_SDRAM_SIZE; +#endif + +return 0 ; +} +#ifdef
CONFIG_USB_GADGET
structdwc2_plat_otg_datasocfpga_otg_data= {
.usb_gusbcfg =0x1417,include/configs/socfpga_common.h +0
-0@@ -47,6 +47,7 @@ (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
#defineCONFIG_SYS_SDRAM_BASEPHYS_SDRAM_1
+#defineCONFIG_SYS_SDRAM_SIZEPHYS_SDRAM_1_SIZE
#ifdefCONFIG_SOCFPGA_VIRTUAL_TARGET
#defineCONFIG_SYS_TEXT_BASE0x08000040
#else
PATCH 7/19 arm: socfpga: Add DRAM bank size initialization function
Quoted 40 lines · Tien Fong
Quoted 39 lines · Marek Vasut
Quoted 38 lines · Tien Fong
Quoted 36 lines · Marek Vasut
Quoted 23 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
Add function for both multiple DRAM bank and single DRAM bank size
initialization. This common functionality could be used by every
single
SOCFPGA board.Signed-off-by Tien Fong Chee <[email protected]>--- arch/arm/mach-socfpga/board.c | 12 ++++++++++++ include/configs/socfpga_common.h | 1 + 2 files changed, 13 insertions(+), 0 deletions(-)arch/arm/mach- renamed from arch/arm/mach-socfpga/board.c +0
-0
socfpga/board.c
index a41d089..3f2e30a 100644arch/arm/mach-socfpga/board.c int board_init(void) · line 36
Quoted 8 lines
arch/arm/mach-socfpga/board.c +4
-0@@ -29,6 +29,18 @@ int board_init(void)return 0 ; } +int dram_init_banksize (void ) +{ +#if !defined(CONFIG_SYS_SDRAM_BASE ) && !defined(CONFIG_SYS_SDRAM_SIZE ) +fdtdec_setup_memory_banksize ();This should work on al boards, so why do you need this macro ? Also, this should go into
arch/arm/, not board/
Quoted 8 lines
Quoted 7 lines
Quoted 4 lines
In case these macros are not defined, then we need to get the info from
DTS. This is inarch/arm/mach-socpfga/board.c. I found some inarch/arm, and other in board/ .Every socfpga platform in u-boot has a dts, so you can always extract the memory config from it and it's the preferred method.
This implementation supports both method, from header or DTS.
We want to support only the DT method, so drop the other one.
Signature · 2 lines
Best regards, Marek Vasut
Chee
PATCH 7/19 arm: socfpga: Add DRAM bank size initialization function
Quoted 53 lines · Marek Vasut
Quoted 52 lines · Tien Fong
Quoted 50 lines · Marek Vasut
Quoted 48 lines · Tien Fong
Quoted 31 lines · Marek Vasut
Quoted 28 lines · tien.fong.chee at intel.com
From: Tien Fong Chee <[email protected]>
Add function for both multiple DRAM bank and single DRAM bank
size
initialization. This common functionality could be used by every
single
SOCFPGA board.Signed-off-by Tien Fong Chee <[email protected]>---
arch/arm/mach-socfpga/board.c | 12 ++++++++++++include/configs/socfpga_common.h| 1 +2 files changed, 13 insertions(+), 0 deletions(-)arch/arm/mach- renamed from arch/arm/mach-socfpga/board.c +0
-0
socfpga/board.c
index a41d089..3f2e30a 100644arch/arm/mach-socfpga/board.c +0
-0@@ -29,6 +29,18 @@ int board_init(void) return 0; }Quoted 9 lines
arch/arm/mach-socfpga/board.c int board_init(void) · line 35
Quoted 5 lines
arch/arm/mach-socfpga/board.c +3
-0+int dram_init_banksize (void ) +{ +#if !defined(CONFIG_SYS_SDRAM_BASE) &&!defined(CONFIG_SYS_SDRAM_SIZE)
arch/arm/mach-socfpga/board.c +1
-0+fdtdec_setup_memory_banksize ();This should work on al boards, so why do you need this macro ?
Also, this should go intoarch/arm/, not board/In case these macros are not defined, then we need to get the info
from
DTS. This is inarch/arm/mach-socpfga/board.c. I found some inarch/arm, and other in board/ .
Quoted 7 lines
Quoted 5 lines
Quoted 4 lines
Every socfpga platform in u-boot has a dts, so you can always extract
the memory config from it and it's the preferred method.This implementation supports both method, from header or DTS.
We want to support only the DT method, so drop the other one.
Okay, noted.
PATCH 8/19 arm: socfpga: Add COMPAT macro for Network on Chip(NoC)
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
This is required by DDR to configure NoC firewall setting based on DTS. The NoC firewall is used to control any data transaction between IP interfacing with DDR.
--- include/fdtdec.h | 1 + lib/fdtdec.c | 1 + 2 files changed, 2 insertions(+), 0 deletions(-)
include/fdtdec.h +1 -0
@@ -163,6 +163,7 @@ enum fdt_compat_id {COMPAT_ALTERA_SOCFPGA_F2SDR0 ,/* SoCFPGA fpga2SDRAM0 bridge */ COMPAT_ALTERA_SOCFPGA_F2SDR1 ,/* SoCFPGA fpga2SDRAM1 bridge */ COMPAT_ALTERA_SOCFPGA_F2SDR2 ,/* SoCFPGA fpga2SDRAM2 bridge */ +COMPAT_ALTERA_SOCFPGA_NOC ,/* Arria10 NOC */ COMPAT_COUNT, };
lib/fdtdec.c +1 -0
@@ -76,6 +76,7 @@ static const char * const compat_names[COMPAT_COUNT] = {COMPAT (ALTERA_SOCFPGA_F2SDR0 ,"altr,socfpga-fpga2sdram0-bridge" ),COMPAT (ALTERA_SOCFPGA_F2SDR1 ,"altr,socfpga-fpga2sdram1-bridge" ),COMPAT (ALTERA_SOCFPGA_F2SDR2 ,"altr,socfpga-fpga2sdram2-bridge" ), + COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"), };const char *fdtdec_get_compatible (enum fdt_compat_id id)
Signature · 1 line
1.7.7.4
PATCH 9/19 arm: socfpga: Add DDR driver for Arria 10
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
Add DDR driver suppport for Arria 10.
--- arch/arm/mach-socfpga/include/mach/sdram.h | 2 + arch/arm/mach-socfpga/include/mach/sdram_arria10.h | 103 +++- drivers/ddr/altera/sdram_arria10.c | 735 ++++++++++++++++++++ 3 files changed, 839 insertions(+), 1 deletions(-) create mode 100644 drivers/ddr/altera/sdram_arria10.c
arch/arm/mach-socfpga/include/mach/sdram.h +2 -0
@@ -10,6 +10,8 @@#if defined(CONFIG_TARGET_SOCFPGA_GEN5 )#include <asm/arch/sdram_gen5.h> +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10 ) +#include <asm/arch/sdram_arria10.h> #endif #endif
arch/arm/mach-socfpga/include/mach/sdram_arria10.h +102 -1
119 lines not on this page · raw message
drivers/ddr/altera/sdram_arria10.c new file +735 -0
735 lines not on this page · raw message
Signature · 1 line
1.7.7.4
PATCH 10/19 configs: Add DDR Kconfig support for Arria 10
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
This patch enables DDR Kconfig support for Arria 10.
--- arch/arm/mach-socfpga/Kconfig | 1 + drivers/ddr/altera/Kconfig | 2 +- 2 files changed, 2 insertions(+), 1 deletions(-)
arch/arm/mach-socfpga/Kconfig +1 -0
@@ -40,6 +40,7 @@ config TARGET_SOCFPGA_ARRIA5 config TARGET_SOCFPGA_ARRIA10 bool select SPL_BOARD_INIT if SPL + select ALTERA_SDRAM config TARGET_SOCFPGA_CYCLONE5 bool
drivers/ddr/altera/Kconfig +1 -1
@@ -1,5 +1,5 @@ config ALTERA_SDRAM bool "SoCFPGA DDR SDRAM driver" - depends on TARGET_SOCFPGA_GEN5 + depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10 help Enable DDR SDRAM controller for the SoCFPGA devices.
Signature · 1 line
1.7.7.4
PATCH 11/19 arm: socfpga: Enable build for DDR Arria 10
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
This patch is for enabling the DDR support on Arria 10.
--- drivers/ddr/altera/Makefile | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
drivers/ddr/altera/Makefile +1 -0
@@ -10,4 +10,5 @@ ifdef CONFIG_ALTERA_SDRAM obj-$(CONFIG_TARGET_SOCFPGA_GEN5) += sdram_gen5.o sequencer.o +obj-$(CONFIG_TARGET_SOCFPGA_ARRIA10) += sdram_arria10.o endif
Signature · 1 line
1.7.7.4
PATCH 12/19 doc: dtbinding: Add Intel Arria 10 SoCFPGA chosen binding
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
This patch adding the Intel Arria 10 SoCFPGA chosen binding info.
--- doc/device-tree-bindings/chosen.txt | 45 +++++++++++++++++++++++++++++++++++ 1 files changed, 45 insertions(+), 0 deletions(-)
doc/device-tree-bindings/chosen.txt +45 -0
@@ -63,3 +63,48 @@ Example u-boot,spl-boot-order = &sdmmc, "/sdhci at fe330000"; }; }; + +Intel SoCFPGA +-------------- + +Arria 10 FPGA design filename and partition properties +------------------------------------------------------ +In Intel Arria 10 SoCFPGA, FPGA is programmed by both SPL and U-boot. +Those FPGA designs are normally stored in the flashes, it could be in SDMMC, +QSPI and NAND. +For bootloader to know where to look those files and how to program the FPGA, +those files' filename, and flash partition are defined in device tree. +There are three properties as shown in below: + +Example +------- +/ { + chosen { + cff-file = "ghrd_10as066n2.periph.rbf.mkimage"; + }; +}; + +cff-file is assigned with peripheral raw binary filename. Peripheral raw binary +file is used to configure FPGA IOs, IO48, DDR and PLL. + +/ { + chosen { + cffcore-file = "ghrd_10as066n2.core.rbf.mkimage"; + }; +}; + +cffcore-file is assigned with core raw binary filename. Core raw binary +file contains FPGA design, which is used to configure FPGA CRAM and ERAM. + +/ { + chosen { + cff_devpart = "0:1"; + }; +}; + +cff_devpart is assigned to partition(default: FAT) where cff-file and +cffcore-file are stored. +[<dev{:part}>] dev is flash device number and part is flash partition. + +Note: For cff-file, the device number is always zero, and only the partition +could be defined by user.
Signature · 1 line
1.7.7.4
PATCH 13/19 dts: Add the FPGA design file name to DTS
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
During FPGA program, FPGA raw binary data file would be searched from flash based on the file name defined in DTS, and then feeding the FPGA file found from flash into FPGA manager for configuring FPGA.
--- .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi +2 -2
@@ -20,8 +20,8 @@ chosen { /* Bootloader setting: uboot.rbf_filename */ - cff-file = "ghrd_10as066n2.periph.rbf"; - early-release-fpga-config; + cff-file = "ghrd_10as066n2.periph.rbf.mkimage"; + cffcore-file = "ghrd_10as066n2.core.rbf.mkimage"; }; soc {
Signature · 1 line
1.7.7.4
PATCH 14/19 dts: Add device storage and partition to DTS
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
SPL need to know the location of RBF files, before loading RBF into memory and program FPGA.
--- .../dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi | 1 + 1 files changed, 1 insertions(+), 0 deletions(-)
arch/arm/dts/socfpga_arria10_socdk_sdmmc_handoff.dtsi +1 -0
@@ -22,6 +22,7 @@ /* Bootloader setting: uboot.rbf_filename */ cff-file = "ghrd_10as066n2.periph.rbf.mkimage"; cffcore-file = "ghrd_10as066n2.core.rbf.mkimage"; + cff_devpart = "0:1"; }; soc {
Signature · 1 line
1.7.7.4
PATCH 15/19 arm: socfpga: Add support to memory allocation in SPL
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
Add support to memory allocation in SPL for preparation to enable FAT in SPL. Memory allocation is needed by FAT to work properly.
--- include/configs/socfpga_common.h | 23 ++++++++++++++++++++++- 1 files changed, 22 insertions(+), 1 deletions(-)
include/configs/socfpga_common.h +22 -1
@@ -292,17 +292,34 @@ unsigned int cm_get_qspi_controller_clk_hz(void);/* * SPL * -* SRAM Memory layout: +* SRAM Memory layout for gen 5: * * 0xFFFF_0000 ...... Start of SRAM * 0xFFFF_xxxx ...... Top of stack (grows down) * 0xFFFF_yyyy ...... Malloc area * 0xFFFF_zzzz ...... Global Data * 0xFFFF_FF00 ...... End of SRAM +* +* SRAM Memory layout for Arria 10: +* 0xFFE0_0000 ...... Start of SRAM (bottom) +* 0xFFEx_xxxx ...... Top of stack (grows down to bottom) +* 0xFFEy_yyyy ...... Malloc area (grows up to top) +* 0xFFEz_zzzz ...... Global Data +* 0xFFE3_FFFF ...... End of SRAM (top) */ #define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE +#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10 ) +/* SPL memory allocation configuration, it is required by FAT feature */ +#ifndef CONFIG_SYS_SPL_MALLOC_START +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00002000 +#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \ + GENERATED_GBL_DATA_SIZE - \ + CONFIG_SYS_SPL_MALLOC_SIZE + \ + CONFIG_SYS_INIT_RAM_ADDR) +#endif +#endif /* SPL SDMMC boot support */ #ifdef CONFIG_SPL_MMC_SUPPORT
@@ -332,7 +349,11 @@ unsigned int cm_get_qspi_controller_clk_hz(void);/* * Stack setup */ +#if defined(CONFIG_TARGET_SOCFPGA_GEN5 )#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR +#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10 ) +#define CONFIG_SPL_STACK (CONFIG_SYS_SPL_MALLOC_START - 1) +#endif /* Extra Environment */ #ifndef CONFIG_SPL_BUILD
Signature · 1 line
1.7.7.4
PATCH 16/19 arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
Enhance preloader header with both additional program length and program entry offset attributes, which offset is relative to the start of program header.
--- arch/arm/mach-socfpga/include/mach/boot0.h | 9 +++++++-- 1 files changed, 7 insertions(+), 2 deletions(-)
arch/arm/mach-socfpga/include/mach/boot0.h +7 -2
@@ -11,8 +11,13 @@ .balignl 64,0xf33db33f; .word 0x1337c0d3; /* SoCFPGA preloader validation word */ - .word 0xc01df00d; /* Version, flags, length */ - .word 0xcafec0d3; /* Checksum, zero-pad */ + .word 0xc01df00d; /* Header length(2B),flags(1B),version(1B) */ +#ifndef CONFIG_TARGET_SOCFPGA_GEN5 + .word 0xfeedface; /* Program length(4B) */ + .word 0xf00dcafe; /* Program entry offset(4B),relative to */ +/* the start of program header */ +#endif + .word 0xcafec0d3; /* Simple checksum(2B),spare offset(2B) */ nop;b reset;/* SoCFPGA jumps here */
Signature · 1 line
1.7.7.4
PATCH 17/19 arm: socfpga: Adding clock frequency info for U-boot
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
Clock frequency info is required in U-boot.
--- arch/arm/mach-socfpga/board.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
arch/arm/mach-socfpga/board.c +6 -0
@@ -8,7 +8,10 @@#include <common.h> #include <errno.h> +#include <fdtdec.h> #include <asm/arch/reset_manager.h> +#include <asm/arch/clock_manager.h> +#include <asm/arch/misc.h> #include <asm/io.h> #include <usb.h>
@@ -26,6 +29,9 @@ int board_init(void)/* Address of boot parameters for ATAG (if ATAG is used) */ gd->bd->bi_boot_params =CONFIG_SYS_SDRAM_BASE +0x100 ; +/* configuring the clock based on handoff */ +cm_basic_init (gd->fdt_blob); +return 0 ; }
Signature · 1 line
1.7.7.4
PATCH 18/19 arm: socfpga: Adding SoCFPGA info for both SPL and U-boot
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
SoC FPGA info is required in both SPL and U-boot.
--- arch/arm/mach-socfpga/board.c | 3 +++ arch/arm/mach-socfpga/misc_arria10.c | 5 ----- arch/arm/mach-socfpga/spl.c | 6 ++++++ 3 files changed, 9 insertions(+), 5 deletions(-)
arch/arm/mach-socfpga/board.c +3 -0
@@ -32,6 +32,9 @@ int board_init(void)/* configuring the clock based on handoff */ cm_basic_init (gd->fdt_blob); +/* Add device descriptor to FPGA device table */ +socfpga_fpga_add (); +return 0 ; }
arch/arm/mach-socfpga/misc_arria10.c +0 -5
@@ -94,11 +94,6 @@ int arch_early_init_r(void)/* assert reset to all except L4WD0 and L4TIMER0 */ socfpga_per_reset_all (); -/* configuring the clock based on handoff */ -/* TODO: Add call to cm_basic_init() */ - -/* Add device descriptor to FPGA device table */ -socfpga_fpga_add (); return 0; }#else
arch/arm/mach-socfpga/spl.c +6 -0
@@ -15,6 +15,7 @@#include <asm/arch/system_manager.h> #include <asm/arch/freeze_controller.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/misc.h> #include <asm/arch/scan_manager.h> #include <asm/arch/sdram.h> #include <asm/arch/scu.h>
@@ -208,6 +209,11 @@ void spl_board_init(void)/* enable console uart printing */ preloader_console_init (); + +WATCHDOG_RESET (); + +/* Add device descriptor to FPGA device table */ +socfpga_fpga_add (); }void board_init_f (ulong dummy)
Signature · 1 line
1.7.7.4
PATCH 19/19 arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot
In reply to tien.fong.chee at intel.comFrom: Tien Fong Chee <[email protected]>
Enable SPL loading U-boot from SDMMC to DDR and booting U-boot.
--- arch/arm/mach-socfpga/spl.c | 87 +++++++++++++++++++++++++++++++++++++ common/spl/spl_mmc.c | 2 +- configs/socfpga_arria10_defconfig | 49 ++++++++++++++++++++- disk/part.c | 2 + include/spl.h | 2 + 5 files changed, 139 insertions(+), 3 deletions(-)
arch/arm/mach-socfpga/spl.c +87 -0
@@ -15,6 +15,7 @@#include <asm/arch/system_manager.h> #include <asm/arch/freeze_controller.h> #include <asm/arch/clock_manager.h> +#include <asm/arch/fpga_manager.h> #include <asm/arch/misc.h> #include <asm/arch/scan_manager.h> #include <asm/arch/sdram.h>
@@ -22,6 +23,10 @@#include <asm/arch/nic301.h> #include <asm/sections.h> #include <fdtdec.h> +#include <fat.h> +#include <fs.h> +#include <linux/ctype.h> +#include <mmc.h> #include <watchdog.h> #if defined(CONFIG_TARGET_SOCFPGA_ARRIA10 )#include <asm/arch/pinmux.h>
@@ -29,6 +34,9 @@DECLARE_GLOBAL_DATA_PTR ; +#define BSIZE 4096 +#define PERIPH_RBF 0 +#if defined(CONFIG_TARGET_SOCFPGA_GEN5 )static struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE ;
@@ -197,6 +205,11 @@ void board_init_f(ulong dummy)#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10 )void spl_board_init (void ) { +int rval =0 ; +int len =0 ; +u32 buffer[BSIZE ]__aligned(ARCH_DMA_MINALIGN) ; +struct spl_boot_device bootdev; +/* configuring the clock based on handoff */ cm_basic_init (gd->fdt_blob);WATCHDOG_RESET ();
@@ -214,6 +227,80 @@ void spl_board_init(void)/* Add device descriptor to FPGA device table */ socfpga_fpga_add (); + + bootdev.boot_device =spl_boot_device (); + +if (BOOT_DEVICE_MMC1 == bootdev.boot_device) + { +struct mmc *mmc =NULL ; +int err =0 ; +fpga_fs_info fpga_fsinfo; +const char *part_str; +char *dup_str =NULL ; + +spl_mmc_find_device (&mmc, bootdev.boot_device); + + err =mmc_init (mmc); + +if (err) { +#ifdef CONFIG_SPL_LIBCOMMON_SUPPORT +printf ("spl: mmc init failed with error: %d\n" , err); +#endif + } + + fpga_fsinfo.filename = (char *)get_cff_filename (gd->fdt_blob, + &len, +PERIPH_RBF ); + + fpga_fsinfo.dev_part = (char *)get_cff_devpart (gd->fdt_blob, + &len); + + fpga_fsinfo.interface ="mmc" ; + + fpga_fsinfo.fstype =FS_TYPE_FAT ; + +/* Program peripheral RBF */ +if (fpga_fsinfo.filename && (len >0 )) { + +if (NULL == fpga_fsinfo.dev_part) { +/* FAT partition */ + fpga_fsinfo.dev_part ="0:1" ; + +printf ("No SD/MMC partition found in " ); +printf ("environment. Assuming device 0," ); +printf (" partition 1.\n" ); + } + +/* Separate device and partition ID specification */ + part_str =strchr (fpga_fsinfo.dev_part,':' ); + dup_str =strdup (fpga_fsinfo.dev_part); + dup_str[part_str - fpga_fsinfo.dev_part] =0 ; + part_str++; + +if (!isdigit (*part_str)) + { +printf ("Invalid device partition |%c|\n" , + *part_str ); +return ; + } + +/* we are looking at the FAT partition */ +if (fat_register_device (mmc_get_blk_desc (mmc), +simple_strtol (part_str,NULL ,10 ))) { +printf ("Failed to set partition |%c| to FAT.\n" , + *part_str); +return ; + } + + rval =fpga_fsload (0 , buffer,BSIZE , &fpga_fsinfo); + } + } + +if (rval >0 ) { +config_pins (gd->fdt_blob,"shared" ); + +ddr_calibration_sequence (); + } }void board_init_f (ulong dummy)
common/spl/spl_mmc.c +1 -1
@@ -113,7 +113,7 @@ static int spl_mmc_get_device_index(u32 boot_device)return -ENODEV ; } -static int spl_mmc_find_device (struct mmc **mmcp,u32 boot_device) +int spl_mmc_find_device (struct mmc **mmcp,u32 boot_device) {#ifdef CONFIG_DM_MMC struct udevice *dev;
configs/socfpga_arria10_defconfig +47 -2
79 lines not on this page · raw message
disk/part.c +2 -0
@@ -427,6 +427,7 @@ int blk_get_device_part_str(const char *ifname, const char *dev_part_str, }#endif +#ifndef CONFIG_SPL_BUILD #ifdef CONFIG_CMD_UBIFS /* * Special-case ubi, ubi goes through a mtd, rathen then through
@@ -448,6 +449,7 @@ int blk_get_device_part_str(const char *ifname, const char *dev_part_str,return 0 ; }#endif +#endif /* If no dev_part_str, use bootdevice environment variable */ if (!dev_part_str || !strlen(dev_part_str) ||
include/spl.h +2 -0
@@ -10,6 +10,7 @@/* Platform-specific defines */ #include <linux/compiler.h> #include <asm/spl.h> +#include <mmc.h> /* Value in r0 indicates we booted from U-Boot */ #define UBOOT_NOT_LOADED_FROM_SPL 0x13578642
@@ -68,6 +69,7 @@ int spl_load_simple_fit(struct spl_image_info *spl_image,void preloader_console_init (void );u32 spl_boot_device (void );u32 spl_boot_mode (const u32 boot_device); +int spl_mmc_find_device (struct mmc **mmcp,u32 boot_device);/** * spl_set_header_raw_uboot() - Set up a standard SPL image structure
Signature · 1 line
1.7.7.4