drm/i915: Add interface to reserve fence registers for vGPU

PATCH In review [email protected] 4 participants 6 messages Sep 4, 2017

Subsystems (3)

DRM drivers Intel i915 Intel GVT-g drivers (Intel GPU Virtualization)

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2017-09-04 08:01 UTC #0 lore raw

PATCH v3 1/1 drm/i915: Add interface to reserve fence registers for vGPU

From: Changbin Du <[email protected]>

In the past, vGPU alloc fence registers by walking through mm.fence_list to find fence which pin_count = 0 and vma is empty. vGPU may not find enough fence registers this way. Because a fence can be bind to vma even though it is not in using. We have found such failure many times these days.

An option to resolve this issue is that we can force-remove fence from vma in this case.

This patch added two new api to the fence management code:
- i915_reserve_fence() will try to find a free fence from fence_list and force-remove vma if need.
- i915_unreserve_fence() reclaim a reserved fence after vGPU has finished.

With this change, the fence management is more clear to work with vGPU. GVTg do not need remove fence from fence_list in private.

v3: (Chris)
- Add struct_mutex lock assertion.
- Only count for unpinned fence.

v2: (Chris)
- Rename the new api for symmetry.
- Add safeguard to ensure at least 1 fence remained for host display.

Signed-off-by Changbin Du <[email protected]>

Reviewed-by Chris Wilson <[email protected]>

---
 drivers/gpu/drm/i915/gvt/aperture_gm.c    | 26 +++++++---------
 drivers/gpu/drm/i915/i915_drv.h           |  3 ++
 drivers/gpu/drm/i915/i915_gem_fence_reg.c | 49 +++++++++++++++++++++++++++++++
 3 files changed, 63 insertions(+), 15 deletions(-)

drivers/gpu/drm/i915/gvt/aperture_gm.c +11 ~~-15~~

index ca3d192..7c9ec4f 100644
@@ -173,8 +173,8 @@ static void free_vgpu_fence(struct intel_vgpu *vgpu)
 	_clear_vgpu_fence(vgpu);
 	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
 		reg = vgpu->fence.regs[i];
-		list_add_tail(&reg->link,
-			      &dev_priv->mm.fence_list);
+		i915_unreserve_fence(reg);
+		vgpu->fence.regs[i] = NULL;
 	}
 	mutex_unlock(&dev_priv->drm.struct_mutex);

@@ -187,24 +187,19 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
 	struct drm_i915_private *dev_priv = gvt->dev_priv;
 	struct drm_i915_fence_reg *reg;
 	int i;
-	struct list_head *pos, *q;
 
 	intel_runtime_pm_get(dev_priv);
 
 	/* Request fences from host */
 	mutex_lock(&dev_priv->drm.struct_mutex);
-	i = 0;
-	list_for_each_safe(pos, q, &dev_priv->mm.fence_list) {
-		reg = list_entry(pos, struct drm_i915_fence_reg, link);
-		if (reg->pin_count || reg->vma)
-			continue;
-		list_del(pos);
+
+	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
+		reg = i915_reserve_fence(dev_priv);
+		if (IS_ERR(reg))
+			goto out_free_fence;
+
 		vgpu->fence.regs[i] = reg;
-		if (++i == vgpu_fence_sz(vgpu))
-			break;
 	}
-	if (i != vgpu_fence_sz(vgpu))
-		goto out_free_fence;
 
 	_clear_vgpu_fence(vgpu);

@@ -212,13 +207,14 @@ static int alloc_vgpu_fence(struct intel_vgpu *vgpu)
 	intel_runtime_pm_put(dev_priv);
 	return 0;
 out_free_fence:
+	gvt_vgpu_err("Failed to alloc fences\n");
 	/* Return fences to host, if fail */
 	for (i = 0; i < vgpu_fence_sz(vgpu); i++) {
 		reg = vgpu->fence.regs[i];
 		if (!reg)
 			continue;
-		list_add_tail(&reg->link,
-			      &dev_priv->mm.fence_list);
+		i915_unreserve_fence(reg);
+		vgpu->fence.regs[i] = NULL;
 	}
 	mutex_unlock(&dev_priv->drm.struct_mutex);
 	intel_runtime_pm_put(dev_priv);

drivers/gpu/drm/i915/i915_drv.h +3 -0

index 064bf0f..7c35d57 100644
@@ -3673,6 +3673,9 @@ i915_vm_to_ppgtt(struct i915_address_space *vm)
 /* i915_gem_fence_reg.c */
 int __must_check i915_vma_get_fence(struct i915_vma *vma);
 int __must_check i915_vma_put_fence(struct i915_vma *vma);
+struct drm_i915_fence_reg *
+i915_reserve_fence(struct drm_i915_private *dev_priv);
+void i915_unreserve_fence(struct drm_i915_fence_reg *fence);
 
 void i915_gem_revoke_fences(struct drm_i915_private *dev_priv);
 void i915_gem_restore_fences(struct drm_i915_private *dev_priv);

drivers/gpu/drm/i915/i915_gem_fence_reg.c +49 -0

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2.7.4

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Patchwork

2017-09-04 09:05 UTC #1 lore raw

✓ Fi.CI.BAT: success for drm/i915: Add interface to reserve fence registers for vGPU (rev3)

== Series Details ==

Series: drm/i915: Add interface to reserve fence registers for vGPU (rev3)
URL : https://patchwork.freedesktop.org/series/29523/
State : success

== Summary ==

Series 29523v3 drm/i915: Add interface to reserve fence registers for vGPU
https://patchwork.freedesktop.org/api/1.0/series/29523/revisions/3/mbox/

Test kms_cursor_legacy:

        Subgroup basic-busy-flip-before-cursor-atomic:
                fail       -> PASS       (fi-snb-2600) fdo#100215
Test kms_frontbuffer_tracking:
        Subgroup basic:
                pass       -> DMESG-WARN (fi-bdw-5557u) fdo#102473

fdo#100215 https://bugs.freedesktop.org/show_bug.cgi?id=100215
fdo#102473 https://bugs.freedesktop.org/show_bug.cgi?id=102473

fi-bdw-5557u     total:288  pass:267  dwarn:1   dfail:0   fail:0   skip:20  time:458s
fi-bdw-gvtdvm    total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:440s
fi-blb-e6850     total:288  pass:224  dwarn:1   dfail:0   fail:0   skip:63  time:358s
fi-bsw-n3050     total:288  pass:243  dwarn:0   dfail:0   fail:0   skip:45  time:556s
fi-bwr-2160      total:288  pass:184  dwarn:0   dfail:0   fail:0   skip:104 time:253s
fi-bxt-j4205     total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:520s
fi-byt-j1900     total:288  pass:254  dwarn:1   dfail:0   fail:0   skip:33  time:522s
fi-byt-n2820     total:288  pass:250  dwarn:1   dfail:0   fail:0   skip:37  time:515s
fi-cfl-s         total:285  pass:250  dwarn:1   dfail:0   fail:0   skip:33 
fi-elk-e7500     total:288  pass:230  dwarn:0   dfail:0   fail:0   skip:58  time:430s
fi-glk-2a        total:288  pass:260  dwarn:0   dfail:0   fail:0   skip:28  time:615s
fi-hsw-4770      total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  time:448s
fi-hsw-4770r     total:288  pass:263  dwarn:0   dfail:0   fail:0   skip:25  time:423s
fi-ilk-650       total:288  pass:229  dwarn:0   dfail:0   fail:0   skip:59  time:426s
fi-ivb-3520m     total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:514s
fi-ivb-3770      total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:472s
fi-kbl-7500u     total:288  pass:264  dwarn:1   dfail:0   fail:0   skip:23  time:518s
fi-kbl-7560u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:592s
fi-kbl-r         total:288  pass:261  dwarn:0   dfail:0   fail:0   skip:27  time:598s
fi-pnv-d510      total:288  pass:223  dwarn:1   dfail:0   fail:0   skip:64  time:536s
fi-skl-6260u     total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:468s
fi-skl-6700k     total:288  pass:265  dwarn:0   dfail:0   fail:0   skip:23  time:538s
fi-skl-6770hq    total:288  pass:269  dwarn:0   dfail:0   fail:0   skip:19  time:508s
fi-skl-gvtdvm    total:288  pass:266  dwarn:0   dfail:0   fail:0   skip:22  time:447s
fi-skl-x1585l    total:288  pass:268  dwarn:0   dfail:0   fail:0   skip:20  time:486s
fi-snb-2520m     total:288  pass:251  dwarn:0   dfail:0   fail:0   skip:37  time:550s
fi-snb-2600      total:288  pass:249  dwarn:0   dfail:0   fail:1   skip:38  time:405s

b80ab89c2d7542c89e087c35c0f9e33475007f8f drm-tip: 2017y-09m-04d-08h-27m-46s UTC integration manifest 8820101bd2df drm/i915: Add interface to reserve fence registers for vGPU

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5573/
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Chris Wilson

2017-09-04 10:01 UTC #2 lore raw

In reply to [email protected]

Quoting [email protected] (2017-09-04 09:01:01)

Quoted 24 lines

From: Changbin Du <[email protected]>
In the past, vGPU alloc fence registers by walking through mm.fence_list to find fence which pin_count = 0 and vma is empty. vGPU may not find enough fence registers this way. Because a fence can be bind to vma even though it is not in using. We have found such failure many times these days.
An option to resolve this issue is that we can force-remove fence from vma in this case.
This patch added two new api to the fence management code:
- i915_reserve_fence() will try to find a free fence from fence_list and force-remove vma if need.
- i915_unreserve_fence() reclaim a reserved fence after vGPU has finished.
With this change, the fence management is more clear to work with vGPU. GVTg do not need remove fence from fence_list in private.
v3: (Chris)
- Add struct_mutex lock assertion.
- Only count for unpinned fence.

Quoted 6 lines

v2: (Chris)
- Rename the new api for symmetry.
- Add safeguard to ensure at least 1 fence remained for host display.
Signed-off-by Changbin Du <[email protected]>
Reviewed-by Chris Wilson <[email protected]>

Anyone want to give an ack/review for the GVT side, and then I'll push. -Chris
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Zhenyu Wang

Acked-by

2017-09-04 15:04 UTC #3 lore raw

Quoted 25 lines · Chris Wilson

Quoting [email protected] (2017-09-04 09:01:01)
Quoted 24 lines
From: Changbin Du <[email protected]>
In the past, vGPU alloc fence registers by walking through mm.fence_list to find fence which pin_count = 0 and vma is empty. vGPU may not find enough fence registers this way. Because a fence can be bind to vma even though it is not in using. We have found such failure many times these days.
An option to resolve this issue is that we can force-remove fence from vma in this case.
This patch added two new api to the fence management code:
- i915_reserve_fence() will try to find a free fence from fence_list and force-remove vma if need.
- i915_unreserve_fence() reclaim a reserved fence after vGPU has finished.
With this change, the fence management is more clear to work with vGPU. GVTg do not need remove fence from fence_list in private.
v3: (Chris)
- Add struct_mutex lock assertion.
- Only count for unpinned fence.

Quoted 8 lines

Quoted 6 lines
v2: (Chris)
- Rename the new api for symmetry.
- Add safeguard to ensure at least 1 fence remained for host display.
Signed-off-by Changbin Du <[email protected]>
Reviewed-by Chris Wilson <[email protected]>
Anyone want to give an ack/review for the GVT side, and then I'll push.

Acked-by Zhenyu Wang <[email protected]>

thanks

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Chris Wilson

2017-09-04 15:40 UTC #4 lore raw

Quoting Zhenyu Wang (2017-09-04 16:04:03)

Quoted 30 lines · Chris Wilson

Quoted 29 lines
Quoting [email protected] (2017-09-04 09:01:01)
Quoted 28 lines
From: Changbin Du <[email protected]>
In the past, vGPU alloc fence registers by walking through mm.fence_list to find fence which pin_count = 0 and vma is empty. vGPU may not find enough fence registers this way. Because a fence can be bind to vma even though it is not in using. We have found such failure many times these days.
An option to resolve this issue is that we can force-remove fence from vma in this case.
This patch added two new api to the fence management code:
- i915_reserve_fence() will try to find a free fence from fence_list and force-remove vma if need.
- i915_unreserve_fence() reclaim a reserved fence after vGPU has finished.
With this change, the fence management is more clear to work with vGPU. GVTg do not need remove fence from fence_list in private.
v3: (Chris)
- Add struct_mutex lock assertion.
- Only count for unpinned fence.
v2: (Chris)
- Rename the new api for symmetry.
- Add safeguard to ensure at least 1 fence remained for host display.

Quoted 6 lines

Quoted 4 lines
Quoted 2 lines
Signed-off-by Changbin Du <[email protected]>
Reviewed-by Chris Wilson <[email protected]>
Anyone want to give an ack/review for the GVT side, and then I'll push.
Acked-by Zhenyu Wang <[email protected]>

And pushed.
-Chris
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Patchwork

2017-09-04 10:59 UTC #5 lore raw

✗ Fi.CI.IGT: warning for drm/i915: Add interface to reserve fence registers for vGPU (rev3)

In reply to [email protected]

== Series Details ==

Series: drm/i915: Add interface to reserve fence registers for vGPU (rev3)
URL : https://patchwork.freedesktop.org/series/29523/
State : warning

== Summary ==

Test kms_flip:

        Subgroup wf_vblank-vs-dpms-interruptible:
                pass       -> DMESG-WARN (shard-hsw)
Test kms_setmode:
        Subgroup basic:
                fail       -> PASS       (shard-hsw) fdo#99912
Test perf:
        Subgroup blocking:
                pass       -> FAIL       (shard-hsw) fdo#102252

fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-hsw total:2265 pass:1232 dwarn:1 dfail:0 fail:16 skip:1016 time:9570s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_5573/shards.html
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