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FAILED: patch "[PATCH] drm/i915: reintroduce VLV/CHV PFI programming power domain" failed to apply to 4.13-stable tree

PATCH [email protected] 1 participant 1 message Sep 20, 2017

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Stable branch DRM drivers Intel i915
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The patch below does not apply to the 4.13-stable tree.
If someone wants it applied there, or to any other stable or longterm tree, then please email the backport, including the original git commit id to <[email protected]>.

thanks,

greg k-h

------------------ original commit in Linus's tree ------------------

Quoted 1 line

From 886015a0ad43c7fc034b23ea4614ba39162f9ddd Mon Sep 17 00:00:00 2001

From: Gabriel Krisman Bertazi <[email protected]>
Date: Wed, 28 Jun 2017 18:06:05 -0300
Subject: [PATCH] drm/i915: reintroduce VLV/CHV PFI programming power domain
workaround
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There are still cases on these platforms where an attempt is made to configure the CDCLK while the power domain is off, like when coming back from a suspend. So the workaround below is still needed.

This effectively reverts commit 63ff30442519 ("drm/i915: Nuke the VLV/CHV PFI programming power domain workaround").

Cc: [email protected]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101517

Suggested-by Ville Syrjälä <[email protected]>
Signed-off-by Gabriel Krisman Bertazi <[email protected]>
Link http://patchwork.freedesktop.org/patch/msgid/[email protected]
Reviewed-by Ville Syrjälä <[email protected]>
Signed-off-by Ville Syrjälä <[email protected]>
drivers/gpu/drm/i915/intel_cdclk.c +20 -0
index b8914db7d2e1..1241e5891b29 100644
@@ -491,6 +491,14 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 	int cdclk = cdclk_state->cdclk;
 	u32 val, cmd;
 
+	/* There are cases where we can end up here with power domains
+	 * off and a CDCLK frequency other than the minimum, like when
+	 * issuing a modeset without actually changing any display after
+	 * a system suspend.  So grab the PIPE-A domain, which covers
+	 * the HW blocks needed for the following programming.
+	 */
+	intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+
 	if (cdclk >= 320000) /* jump to highest voltage for 400MHz too */
 		cmd = 2;
 	else if (cdclk == 266667)

@@ -549,6 +557,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
 	intel_update_cdclk(dev_priv);
 
 	vlv_program_pfi_credits(dev_priv);
+
+	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 }
 
 static void chv_set_cdclk(struct drm_i915_private *dev_priv,

@@ -568,6 +578,14 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 		return;
 	}
 
+	/* There are cases where we can end up here with power domains
+	 * off and a CDCLK frequency other than the minimum, like when
+	 * issuing a modeset without actually changing any display after
+	 * a system suspend.  So grab the PIPE-A domain, which covers
+	 * the HW blocks needed for the following programming.
+	 */
+	intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+
 	/*
 	 * Specs are full of misinformation, but testing on actual
 	 * hardware has shown that we just need to write the desired

@@ -590,6 +608,8 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
 	intel_update_cdclk(dev_priv);
 
 	vlv_program_pfi_credits(dev_priv);
+
+	intel_display_power_put(dev_priv, POWER_DOMAIN_PIPE_A);
 }
 
 static int bdw_calc_cdclk(int max_pixclk)