Enable Stratix10 SoC support

From: Chin Liang See <[email protected]>

Add the base address map for Statix10 SoC

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58 ++++++++++++++++++++++
 1 file changed, 58 insertions(+)
 create mode 100644 arch/arm/mach-socfpga/include/mach/base_addr_s10.h

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +58 -0

new file mode 100644
index 0000000..feb1881
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
+#define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_EMAC0_ADDRESS			0xff800000
+#define SOCFPGA_EMAC1_ADDRESS			0xff802000
+#define SOCFPGA_EMAC2_ADDRESS			0xff804000
+#define SOCFPGA_SDMMC_ADDRESS			0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS		0xff8d2000
+#define SOCFPGA_QSPIDATA_ADDRESS		0xff900000
+#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
+#define SOCFPGA_USB0_ADDRESS			0xffb00000
+#define SOCFPGA_USB1_ADDRESS			0xffb40000
+#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
+#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_I2C0_ADDRESS			0xffc02800
+#define SOCFPGA_I2C1_ADDRESS			0xffc02900
+#define SOCFPGA_I2C2_ADDRESS			0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS			0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS			0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS			0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS			0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER1_ADDRESS		0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS			0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS			0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS			0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS			0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+#define GICD_BASE				0xfffc1000
+#define GICC_BASE				0xfffc2000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

Quoted 6 lines · chin.liang.see at intel.com

From: Chin Liang See <[email protected]>

Add the base address map for Statix10 SoC

Signed-off-by Chin Liang See <[email protected]>

Add only the stuff which is not obtainable from DT please.

Quoted 74 lines

---
 arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 58
++++++++++++++++++++++

 1 file changed, 58 insertions(+)

 create mode 100644 arch/arm/mach-
socfpga/include/mach/base_addr_s10.h

arch/arm/mach-socfpga/include/mach/base_addr_s10.h new file +58 -0

new file mode 100644
index 0000000..feb1881
@@ -0,0 +1,58 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0
+ */
+
+#ifndef _SOCFPGA_S10_BASE_HARDWARE_H_
+#define _SOCFPGA_S10_BASE_HARDWARE_H_
+
+#define SOCFPGA_SDR_SCHEDULER_ADDRESS		0xf8000400
+#define SOCFPGA_HMC_MMR_IO48_ADDRESS		0xf8010000
+#define SOCFPGA_SDR_ADDRESS			0xf8011000
+#define SOCFPGA_SMMU_ADDRESS			0xfa000000
+#define SOCFPGA_EMAC0_ADDRESS			0xff800000
+#define SOCFPGA_EMAC1_ADDRESS			0xff802000
+#define SOCFPGA_EMAC2_ADDRESS			0xff804000
+#define SOCFPGA_SDMMC_ADDRESS			0xff808000
+#define SOCFPGA_QSPIREGS_ADDRESS		0xff8d2000
+#define SOCFPGA_QSPIDATA_ADDRESS		0xff900000
+#define SOCFPGA_MAILBOX_ADDRESS			0xffA30000
+#define SOCFPGA_USB0_ADDRESS			0xffb00000
+#define SOCFPGA_USB1_ADDRESS			0xffb40000
+#define SOCFPGA_NANDREGS_ADDRESS		0xffb80000
+#define SOCFPGA_NANDDATA_ADDRESS		0xffb90000
+#define SOCFPGA_UART0_ADDRESS			0xffc02000
+#define SOCFPGA_UART1_ADDRESS			0xffc02100
+#define SOCFPGA_I2C0_ADDRESS			0xffc02800
+#define SOCFPGA_I2C1_ADDRESS			0xffc02900
+#define SOCFPGA_I2C2_ADDRESS			0xffc02a00
+#define SOCFPGA_I2C3_ADDRESS			0xffc02b00
+#define SOCFPGA_I2C4_ADDRESS			0xffc02c00
+#define SOCFPGA_SPTIMER0_ADDRESS		0xffc03000
+#define SOCFPGA_SPTIMER1_ADDRESS		0xffc03100
+#define SOCFPGA_GPIO0_ADDRESS			0xffc03200
+#define SOCFPGA_GPIO1_ADDRESS			0xffc03300
+#define SOCFPGA_SYSTIMER0_ADDRESS		0xffd00000
+#define SOCFPGA_SYSTIMER1_ADDRESS		0xffd00100
+#define SOCFPGA_L4WD0_ADDRESS			0xffd00200
+#define SOCFPGA_L4WD1_ADDRESS			0xffd00300
+#define SOCFPGA_L4WD2_ADDRESS			0xffd00400
+#define SOCFPGA_L4WD3_ADDRESS			0xffd00500
+#define SOCFPGA_GTIMER_SEC_ADDRESS		0xffd01000
+#define SOCFPGA_GTIMER_NSEC_ADDRESS		0xffd02000
+#define SOCFPGA_CLKMGR_ADDRESS			0xffd10000
+#define SOCFPGA_RSTMGR_ADDRESS			0xffd11000
+#define SOCFPGA_SYSMGR_ADDRESS			0xffd12000
+#define SOCFPGA_PINMUX_DEDICATED_IO_ADDRESS	0xffd13000
+#define SOCFPGA_DMANONSECURE_ADDRESS		0xffda0000
+#define SOCFPGA_DMASECURE_ADDRESS		0xffda1000
+#define SOCFPGA_SPIS0_ADDRESS			0xffda2000
+#define SOCFPGA_SPIS1_ADDRESS			0xffda3000
+#define SOCFPGA_SPIM0_ADDRESS			0xffda4000
+#define SOCFPGA_SPIM1_ADDRESS			0xffda5000
+#define SOCFPGA_OCRAM_ADDRESS			0xffe00000
+#define GICD_BASE				0xfffc1000
+#define GICC_BASE				0xfffc2000
+
+#endif /* _SOCFPGA_S10_BASE_HARDWARE_H_ */

From: Chin Liang See <[email protected]>

Device tree for Stratix10 SoC

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/dts/Makefile                    |   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts | 141 +++++++++++++++++++++++++++++++
 2 files changed, 143 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

arch/arm/dts/Makefile +2 -1

index fee4680..4cf5fd0 100644
@@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=                               \
        socfpga_cyclone5_sockit.dtb                     \
        socfpga_cyclone5_socrates.dtb                   \
        socfpga_cyclone5_sr1500.dtb                     \
-       socfpga_cyclone5_vining_fpga.dtb
+       socfpga_cyclone5_vining_fpga.dtb                \
+       socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
        dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb

arch/arm/dts/socfpga_stratix10_socdk.dts new file +0 -0

new file mode 100644
index 0000000..484c630

arch/arm/dts/socfpga_stratix10_socdk.dts new file +58 -0

+
+/ {
+       model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
+       compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen {
+               bootargs = "console=ttyS0,115200";
+       };
+
+       aliases {
+               ethernet0 = &gmac0;
+               spi0 = &qspi;
+       };
+
+       memory {
+               name = "memory";
+               device_type = "memory";
+               reg = <0x0 0x80000000>; /* 2GB */
+       };
+
+       regulator_3_3v: 3-3-v-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               device_type = "soc";
+               ranges;
+               u-boot,dm-pre-reloc;
+
+               rst: rstmgr at ffd11000 {
+                       #reset-cells = <1>;
+                       compatible = "altr,rst-mgr";
+                       reg = <0xffd11000 0x100>;
+                       altr,modrst-offset = <0x20>;
+               };
+
+               gmac0: ethernet at ff800000 {
+                       compatible = "altr,socfpga-stmmac", "snps,dwmac-3.74a", "snps,dwmac";
+                       reg = <0xff800000 0x2000>;
+                       interrupts = <0 90 4>;
+                       interrupt-names = "macirq";
+                       mac-address = [00 00 00 00 00 00];
+                       resets = <&rst EMAC0_RESET>;
+                       reset-names = "stmmaceth";
+                       phy-mode = "rgmii";
+                       phy-addr = <0xffffffff>; /* probe for phy addr */
+                       max-speed = <1000>;
+                       txd0-skew-ps = <0>; /* -420ps */
+                       txd1-skew-ps = <0>; /* -420ps */

Quoted 41 lines · On Tue, Sep 19, 2017 at 4:22 AM,  <[email protected]> wrote:

From: Chin Liang See <[email protected]>

Device tree for Stratix10 SoC

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/dts/Makefile                    |   3 +- arch/arm/dts/socfpga_stratix10_socdk.dts | 141
+++++++++++++++++++++++++++++++

 2 files changed, 143 insertions(+), 1 deletion(-)

 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

arch/arm/dts/Makefile +3 -1

index fee4680..4cf5fd0 100644
@@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA)
+=                               \
         socfpga_cyclone5_sockit.dtb                     \
         socfpga_cyclone5_socrates.dtb                   \
         socfpga_cyclone5_sr1500.dtb                     \
-       socfpga_cyclone5_vining_fpga.dtb
+       socfpga_cyclone5_vining_fpga.dtb                \
+       socfpga_stratix10_socdk.dtb
 
  dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \

        dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb

arch/arm/dts/socfpga_stratix10_socdk.dts new file +6 -0

new file mode 100644
index 0000000..484c630
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+

arch/arm/dts/socfpga_stratix10_socdk.dts line 9

Quoted 3 lines

arch/arm/dts/socfpga_stratix10_socdk.dts new file +3 -0

+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>

You don't add the patch for this include file until patch 4/14, which means
the build will fail until patch 4 is applied. You need to move this patch
after 4/14.

Quoted 65 lines

arch/arm/dts/socfpga_stratix10_socdk.dts new file +47 -0

+
+/ {
+       model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
+       compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen {
+               bootargs = "console=ttyS0,115200";
+       };
+
+       aliases {
+               ethernet0 = &gmac0;
+               spi0 = &qspi;
+       };
+
+       memory {
+               name = "memory";
+               device_type = "memory";
+               reg = <0x0 0x80000000>; /* 2GB */
+       };
+
+       regulator_3_3v: 3-3-v-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               device_type = "soc";
+               ranges;
+               u-boot,dm-pre-reloc;
+
+               rst: rstmgr at ffd11000 {
+                       #reset-cells = <1>;
+                       compatible = "altr,rst-mgr";
+                       reg = <0xffd11000 0x100>;
+                       altr,modrst-offset = <0x20>;
+               };
+
+               gmac0: ethernet at ff800000 {
+                       compatible = "altr,socfpga-stmmac",

"snps,dwmac-3.74a", "snps,dwmac";
+                       reg = <0xff800000 0x2000>;
+                       interrupts = <0 90 4>;
+                       interrupt-names = "macirq";
+                       mac-address = [00 00 00 00 00 00]; +                       resets = <&rst EMAC0_RESET>;
+                       reset-names = "stmmaceth";
+                       phy-mode = "rgmii";
+                       phy-addr = <0xffffffff>; /* probe for phy addr */
+                       max-speed = <1000>;
+                       txd0-skew-ps = <0>; /* -420ps */ +                       txd1-skew-ps = <0>; /* -420ps */ +                       txd2-skew-ps = <0>; /* -420ps */ +                       txd3-skew-ps = <0>; /* -420ps */ +                       rxd0-skew-ps = <420>; /* 0ps */

Quoted 7 lines

+                       rxd1-skew-ps = <420>; /* 0ps */ +                       rxd2-skew-ps = <420>; /* 0ps */ +                       rxd3-skew-ps = <420>; /* 0ps */ +                       txen-skew-ps = <0>; /* -420ps */ +                       txc-skew-ps = <1860>; /* 960ps */ +                       rxdv-skew-ps = <420>; /* 0ps */ +                       rxc-skew-ps = <1680>; /* 780ps */

These are PHY properties, which should be in a separate PHY node.

Dinh

From: Chin Liang See <[email protected]>

Device tree for Stratix10 SoC

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/dts/Makefile                    |   3 +-
 arch/arm/dts/socfpga_stratix10_socdk.dts | 141 +++++++++++++++++++++++++++++++
 2 files changed, 143 insertions(+), 1 deletion(-)
 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

arch/arm/dts/Makefile +2 -1

index fee4680..4cf5fd0 100644
@@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA) +=                               \
        socfpga_cyclone5_sockit.dtb                     \
        socfpga_cyclone5_socrates.dtb                   \
        socfpga_cyclone5_sr1500.dtb                     \
-       socfpga_cyclone5_vining_fpga.dtb
+       socfpga_cyclone5_vining_fpga.dtb                \
+       socfpga_stratix10_socdk.dtb
 
 dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \
        dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb

arch/arm/dts/socfpga_stratix10_socdk.dts new file +43 -0

new file mode 100644
index 0000000..484c630
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+/ {
+       model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
+       compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen {
+               bootargs = "console=ttyS0,115200";
+       };
+
+       aliases {
+               ethernet0 = &gmac0;
+               spi0 = &qspi;
+       };
+
+       memory {
+               name = "memory";
+               device_type = "memory";
+               reg = <0x0 0x80000000>; /* 2GB */
+       };
+
+       regulator_3_3v: 3-3-v-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";

Quoted 81 lines · On Tue, Sep 19, 2017 at 4:22 AM,  <[email protected]> wrote:

From: Chin Liang See <[email protected]>

Device tree for Stratix10 SoC

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/dts/Makefile                    |   3 +- arch/arm/dts/socfpga_stratix10_socdk.dts | 141
+++++++++++++++++++++++++++++++

 2 files changed, 143 insertions(+), 1 deletion(-)

 create mode 100644 arch/arm/dts/socfpga_stratix10_socdk.dts

arch/arm/dts/Makefile +3 -1

index fee4680..4cf5fd0 100644
@@ -171,7 +171,8 @@ dtb-$(CONFIG_ARCH_SOCFPGA)
+=                               \
         socfpga_cyclone5_sockit.dtb                     \
         socfpga_cyclone5_socrates.dtb                   \
         socfpga_cyclone5_sr1500.dtb                     \
-       socfpga_cyclone5_vining_fpga.dtb
+       socfpga_cyclone5_vining_fpga.dtb                \
+       socfpga_stratix10_socdk.dtb
 
  dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb  \

        dra72-evm-revc.dtb dra71-evm.dtb dra76-evm.dtb

arch/arm/dts/socfpga_stratix10_socdk.dts new file +46 -0

new file mode 100644
index 0000000..484c630
@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+/dts-v1/;
+#include "skeleton.dtsi"
+#include <dt-bindings/reset/altr,rst-mgr-s10.h>
+
+/ {
+       model = "Intel SOCFPGA Stratix 10 SoC Development Kit";
+       compatible = "altr,socfpga-stratix10", "altr,socfpga";
+
+       #address-cells = <1>;
+       #size-cells = <1>;
+
+       chosen {
+               bootargs = "console=ttyS0,115200";
+       };
+
+       aliases {
+               ethernet0 = &gmac0;
+               spi0 = &qspi;
+       };
+
+       memory {
+               name = "memory";
+               device_type = "memory";
+               reg = <0x0 0x80000000>; /* 2GB */
+       };
+
+       regulator_3_3v: 3-3-v-regulator {
+               compatible = "regulator-fixed";
+               regulator-name = "3.3V";
+               regulator-min-microvolt = <3300000>;
+               regulator-max-microvolt = <3300000>;
+       };
+
+       soc {
+               #address-cells = <1>;
+               #size-cells = <1>;
+               compatible = "simple-bus";
+               device_type = "soc";
+               ranges;
+               u-boot,dm-pre-reloc;

arch/arm/dts/socfpga_stratix10_socdk.dts line 53

Quoted 7 lines

arch/arm/dts/socfpga_stratix10_socdk.dts new file +7 -0

+
+               rst: rstmgr at ffd11000 {
+                       #reset-cells = <1>;
+                       compatible = "altr,rst-mgr";
+                       reg = <0xffd11000 0x100>;
+                       altr,modrst-offset = <0x20>;
+               };

Where are the cpu nodes?

Dinh

From: Chin Liang See <[email protected]>

Add Clock Manager driver support for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/mach-socfpga/Makefile                     |   4 +
 arch/arm/mach-socfpga/clock_manager.c              |   4 +-
 arch/arm/mach-socfpga/clock_manager_s10.c          | 359 +++++++++++++++++++++
 arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 +
 .../mach-socfpga/include/mach/clock_manager_s10.h  | 202 ++++++++++++
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++
 arch/arm/mach-socfpga/wrap_pll_config_s10.c        |  46 +++
 7 files changed, 644 insertions(+), 2 deletions(-)
 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c
 create mode 100644 arch/arm/mach-socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach-socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c

arch/arm/mach-socfpga/Makefile +4 -0

index 286bfef..e5f9dd7 100644
@@ -30,6 +30,10 @@ obj-y        += pinmux_arria10.o
 obj-y  += reset_manager_arria10.o
 endif
 
+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += clock_manager_s10.o
+obj-y  += wrap_pll_config_s10.o
+endif
 ifdef CONFIG_SPL_BUILD
 obj-y  += spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5

arch/arm/mach-socfpga/clock_manager.c +2 -2

index cb6ae03..f9450a4 100644
@@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)
        do {
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
                inter_val = readl(&clock_manager_base->inter) & mask;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
                inter_val = readl(&clock_manager_base->stat) & mask;
 #endif
                /* Wait for stable lock */

@@ -52,7 +52,7 @@ int set_cpu_clk_info(void)
 
 #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
        gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
        gd->bd->bi_ddr_freq = 0;
 #endif
 

arch/arm/mach-socfpga/clock_manager_s10.c new file +15 -0

new file mode 100644
index 0000000..a9f9b07
@@ -0,0 +1,359 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/handoff_s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_clock_manager *clock_manager_base =
+       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;

arch/arm/mach-socfpga/clock_manager_s10.c new file +6 -0

+static void cm_write_bypass_perpll(uint32_t val)
+{
+       writel(val, &clock_manager_base->per_pll.bypass);
+       cm_wait_for_fsm();
+}
+

arch/arm/mach-socfpga/clock_manager_s10.c new file +4 -0

+ */
+void cm_basic_init(const struct cm_config * const cfg)
+{
+       uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;

arch/arm/mach-socfpga/clock_manager_s10.c new file +14 -0

+       vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) |
+                  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) <<
+                  CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+       writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+               ~CLKMGR_PLLGLOB_RST_MASK),
+               &clock_manager_base->main_pll.pllglob);
+       writel(cfg->main_pll_fdbck, &clock_manager_base->main_pll.fdbck);
+       writel(vcocalib, &clock_manager_base->main_pll.vcocalib);
+       writel(cfg->main_pll_pllc0, &clock_manager_base->main_pll.pllc0);
+       writel(cfg->main_pll_pllc1, &clock_manager_base->main_pll.pllc1);
+       writel(cfg->main_pll_nocdiv, &clock_manager_base->main_pll.nocdiv);
+
+       /* setup peripheral PLL dividers */

arch/arm/mach-socfpga/clock_manager_s10.c new file +16 -0

+
+       writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK &
+               ~CLKMGR_PLLGLOB_RST_MASK),
+               &clock_manager_base->per_pll.pllglob);
+       writel(cfg->per_pll_fdbck, &clock_manager_base->per_pll.fdbck);
+       writel(vcocalib, &clock_manager_base->per_pll.vcocalib);
+       writel(cfg->per_pll_pllc0, &clock_manager_base->per_pll.pllc0);
+       writel(cfg->per_pll_pllc1, &clock_manager_base->per_pll.pllc1);
+       writel(cfg->per_pll_emacctl, &clock_manager_base->per_pll.emacctl);
+       writel(cfg->per_pll_gpiodiv, &clock_manager_base->per_pll.gpiodiv);
+
+       /* Take both PLL out of reset and power up */
+       setbits_le32(&clock_manager_base->main_pll.pllglob,
+                    CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+       setbits_le32(&clock_manager_base->per_pll.pllglob,
+                    CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);

arch/arm/mach-socfpga/clock_manager_s10.c new file +53 -0

+        */
+       writel(0xff, &clock_manager_base->main_pll.mpuclk);
+       writel(0xff, &clock_manager_base->main_pll.nocclk);
+       writel(0xff, &clock_manager_base->main_pll.cntr2clk);
+       writel(0xff, &clock_manager_base->main_pll.cntr3clk);
+       writel(0xff, &clock_manager_base->main_pll.cntr4clk);
+       writel(0xff, &clock_manager_base->main_pll.cntr5clk);
+       writel(0xff, &clock_manager_base->main_pll.cntr6clk);
+       writel(0xff, &clock_manager_base->main_pll.cntr7clk);
+       writel(0xff, &clock_manager_base->main_pll.cntr8clk);
+       writel(0xff, &clock_manager_base->main_pll.cntr9clk);
+       writel(0xff, &clock_manager_base->per_pll.cntr2clk);
+       writel(0xff, &clock_manager_base->per_pll.cntr3clk);
+       writel(0xff, &clock_manager_base->per_pll.cntr4clk);
+       writel(0xff, &clock_manager_base->per_pll.cntr5clk);
+       writel(0xff, &clock_manager_base->per_pll.cntr6clk);
+       writel(0xff, &clock_manager_base->per_pll.cntr7clk);
+       writel(0xff, &clock_manager_base->per_pll.cntr8clk);
+       writel(0xff, &clock_manager_base->per_pll.cntr9clk);
+
+       writel(cfg->main_pll_mpuclk, &clock_manager_base->main_pll.mpuclk);
+       writel(cfg->main_pll_nocclk, &clock_manager_base->main_pll.nocclk);
+       writel(cfg->main_pll_cntr2clk, &clock_manager_base->main_pll.cntr2clk);
+       writel(cfg->main_pll_cntr3clk, &clock_manager_base->main_pll.cntr3clk);
+       writel(cfg->main_pll_cntr4clk, &clock_manager_base->main_pll.cntr4clk);
+       writel(cfg->main_pll_cntr5clk, &clock_manager_base->main_pll.cntr5clk);
+       writel(cfg->main_pll_cntr6clk, &clock_manager_base->main_pll.cntr6clk);
+       writel(cfg->main_pll_cntr7clk, &clock_manager_base->main_pll.cntr7clk);
+       writel(cfg->main_pll_cntr8clk, &clock_manager_base->main_pll.cntr8clk);
+       writel(cfg->main_pll_cntr9clk, &clock_manager_base->main_pll.cntr9clk);
+       writel(cfg->per_pll_cntr2clk, &clock_manager_base->per_pll.cntr2clk);
+       writel(cfg->per_pll_cntr3clk, &clock_manager_base->per_pll.cntr3clk);
+       writel(cfg->per_pll_cntr4clk, &clock_manager_base->per_pll.cntr4clk);
+       writel(cfg->per_pll_cntr5clk, &clock_manager_base->per_pll.cntr5clk);
+       writel(cfg->per_pll_cntr6clk, &clock_manager_base->per_pll.cntr6clk);
+       writel(cfg->per_pll_cntr7clk, &clock_manager_base->per_pll.cntr7clk);
+       writel(cfg->per_pll_cntr8clk, &clock_manager_base->per_pll.cntr8clk);
+       writel(cfg->per_pll_cntr9clk, &clock_manager_base->per_pll.cntr9clk);
+
+       /* Take all PLLs out of bypass */
+       cm_write_bypass_mainpll(0);
+       cm_write_bypass_perpll(0);
+
+       /* clear safe mode / out of boot mode */
+       cm_write_ctrl(readl(&clock_manager_base->ctrl)
+                       & ~(CLKMGR_CTRL_SAFEMODE));
+
+       /* Now ungate non-hw-managed clocks */
+       writel(~0, &clock_manager_base->main_pll.en);
+       writel(~0, &clock_manager_base->per_pll.en);
+
+       /* Clear the loss of lock bits (write 1 to clear) */
+       writel(CLKMGR_INTER_PERPLLLOST_MASK | CLKMGR_INTER_MAINPLLLOST_MASK,

arch/arm/mach-socfpga/clock_manager_s10.c new file +5 -0

+       fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+               CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+       switch (fref) {
+       case CLKMGR_VCO_PSRC_EOSC1:
+               fref = cm_get_osc_clk_hz(0);

arch/arm/mach-socfpga/clock_manager_s10.c new file +130 -0

+       return vco;
+}
+
+static unsigned long cm_get_per_vco_clk_hz(void)
+{
+       unsigned long fref, refdiv, mdiv, reg, vco;
+
+       reg = readl(&clock_manager_base->per_pll.pllglob);
+
+       /* get the fref */
+       fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+               CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+       switch (fref) {
+       case CLKMGR_VCO_PSRC_EOSC1:
+               fref = cm_get_osc_clk_hz(0);
+               break;
+       case CLKMGR_VCO_PSRC_INTOSC:
+               fref = cm_get_intosc_clk_hz();
+               break;
+       case CLKMGR_VCO_PSRC_F2S:
+               fref = cm_get_fpga_clk_hz();
+               break;
+       }
+
+       /* get the refdiv */
+       refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+                 CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+       /* get the mdiv */
+       reg = readl(&clock_manager_base->per_pll.fdbck);
+       mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+       vco = fref / refdiv;
+       vco = vco * (6 + mdiv);
+       return vco;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+       unsigned long clock = readl(&clock_manager_base->main_pll.mpuclk);
+       clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+       switch (clock) {
+       case CLKMGR_CLKSRC_MAIN:
+               clock = cm_get_main_vco_clk_hz();
+               clock /= (readl(&clock_manager_base->main_pll.pllc0) &
+                         CLKMGR_PLLC0_DIV_MASK);
+               break;
+
+       case CLKMGR_CLKSRC_PER:
+               clock = cm_get_per_vco_clk_hz();
+               clock /= (readl(&clock_manager_base->per_pll.pllc0) &
+                         CLKMGR_CLKCNT_MSK);
+               break;
+
+       case CLKMGR_CLKSRC_OSC1:
+               clock = cm_get_osc_clk_hz(0);
+               break;
+
+       case CLKMGR_CLKSRC_INTOSC:
+               clock = cm_get_intosc_clk_hz();
+               break;
+
+       case CLKMGR_CLKSRC_FPGA:
+               clock = cm_get_fpga_clk_hz();
+               break;
+       }
+
+       clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
+               CLKMGR_CLKCNT_MSK);
+       return clock;
+}
+
+unsigned int cm_get_l3_main_clk_hz(void)
+{
+       uint32_t clock = readl(&clock_manager_base->main_pll.nocclk);
+       clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+       switch (clock) {
+       case CLKMGR_CLKSRC_MAIN:
+               clock = cm_get_main_vco_clk_hz();
+               clock /= (readl(&clock_manager_base->main_pll.pllc1) &
+                         CLKMGR_PLLC0_DIV_MASK);
+               break;
+
+       case CLKMGR_CLKSRC_PER:
+               clock = cm_get_per_vco_clk_hz();
+               clock /= (readl(&clock_manager_base->per_pll.pllc1) &
+                         CLKMGR_CLKCNT_MSK);
+               break;
+
+       case CLKMGR_CLKSRC_OSC1:
+               clock = cm_get_osc_clk_hz(0);
+               break;
+
+       case CLKMGR_CLKSRC_INTOSC:
+               clock = cm_get_intosc_clk_hz();
+               break;
+
+       case CLKMGR_CLKSRC_FPGA:
+               clock = cm_get_fpga_clk_hz();
+               break;
+       }
+
+       clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
+               CLKMGR_CLKCNT_MSK);
+       return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+       uint32_t clock = readl(&clock_manager_base->per_pll.cntr6clk);
+       clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+       switch (clock) {
+       case CLKMGR_CLKSRC_MAIN:
+               clock = cm_get_l3_main_clk_hz();
+               clock /= 1 + (readl(&clock_manager_base->main_pll.cntr6clk) &
+                       CLKMGR_CLKCNT_MSK);
+               break;
+
+       case CLKMGR_CLKSRC_PER:
+               clock = cm_get_l3_main_clk_hz();
+               clock /= 1 + (readl(&clock_manager_base->per_pll.cntr6clk) &
+                       CLKMGR_CLKCNT_MSK);
+               break;
+
+       case CLKMGR_CLKSRC_OSC1:
+               clock = cm_get_osc_clk_hz(0);
+               break;

arch/arm/mach-socfpga/clock_manager_s10.c new file +21 -0

+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+       uint32_t clock = cm_get_l3_main_clk_hz();
+
+       clock /= (1 << ((readl(&clock_manager_base->main_pll.nocdiv) >>
+                 CLKMGR_NOCDIV_L4SPCLK_OFFSET) & CLKMGR_CLKCNT_MSK));
+       return clock;
+}
+
+void cm_print_clock_quick_summary(void)
+{
+       printf("MPU         %d kHz\n", (u32)(cm_get_mpu_clk_hz() / 1000));
+       printf("L3 main     %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
+       printf("Main VCO    %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000));
+       printf("Per VCO     %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000));
+       printf("EOSC1       %d kHz\n", cm_get_osc_clk_hz(0) / 1000);
+       printf("HPS MMC     %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+       printf("UART        %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);
+}

arch/arm/mach-socfpga/include/mach/clock_manager.h +2 -0

index 4c6b1f8..ddf814f 100644
@@ -17,6 +17,8 @@ void cm_print_clock_quick_summary(void);
 #include <asm/arch/clock_manager_gen5.h>
 #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
 #include <asm/arch/clock_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/clock_manager_s10.h>
 #endif
 
 #endif /* _CLOCK_MANAGER_H_ */

arch/arm/mach-socfpga/include/mach/clock_manager_s10.h new file +202 -0

new file mode 100644
index 0000000..c99ad97
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef        _CLOCK_MANAGER_S10_
+#define        _CLOCK_MANAGER_S10_
+
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(const int osc);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+struct cm_config {
+       /* main group */
+       uint32_t main_pll_mpuclk;
+       uint32_t main_pll_nocclk;
+       uint32_t main_pll_cntr2clk;
+       uint32_t main_pll_cntr3clk;
+       uint32_t main_pll_cntr4clk;
+       uint32_t main_pll_cntr5clk;
+       uint32_t main_pll_cntr6clk;
+       uint32_t main_pll_cntr7clk;
+       uint32_t main_pll_cntr8clk;
+       uint32_t main_pll_cntr9clk;
+       uint32_t main_pll_nocdiv;
+       uint32_t main_pll_pllglob;
+       uint32_t main_pll_fdbck;
+       uint32_t main_pll_pllc0;
+       uint32_t main_pll_pllc1;
+       uint32_t spare;
+
+       /* peripheral group */
+       uint32_t per_pll_cntr2clk;
+       uint32_t per_pll_cntr3clk;
+       uint32_t per_pll_cntr4clk;
+       uint32_t per_pll_cntr5clk;
+       uint32_t per_pll_cntr6clk;
+       uint32_t per_pll_cntr7clk;
+       uint32_t per_pll_cntr8clk;
+       uint32_t per_pll_cntr9clk;
+       uint32_t per_pll_emacctl;
+       uint32_t per_pll_gpiodiv;
+       uint32_t per_pll_pllglob;
+       uint32_t per_pll_fdbck;
+       uint32_t per_pll_pllc0;
+       uint32_t per_pll_pllc1;
+
+       /* incoming clock */
+       uint32_t hps_osc_clk_hz;
+       uint32_t fpga_clk_hz;
+};
+
+void cm_basic_init(const struct cm_config * const cfg);
+
+struct socfpga_clock_manager_main_pll {
+       u32     en;
+       u32     ens;
+       u32     enr;
+       u32     bypass;
+       u32     bypasss;
+       u32     bypassr;
+       u32     mpuclk;
+       u32     nocclk;
+       u32     cntr2clk;
+       u32     cntr3clk;
+       u32     cntr4clk;
+       u32     cntr5clk;
+       u32     cntr6clk;
+       u32     cntr7clk;
+       u32     cntr8clk;
+       u32     cntr9clk;
+       u32     nocdiv;
+       u32     pllglob;
+       u32     fdbck;
+       u32     mem;
+       u32     memstat;
+       u32     pllc0;
+       u32     pllc1;
+       u32     vcocalib;
+       u32     _pad_0x90_0xA0[5];
+};
+
+struct socfpga_clock_manager_per_pll {
+       u32     en;
+       u32     ens;
+       u32     enr;
+       u32     bypass;
+       u32     bypasss;
+       u32     bypassr;
+       u32     cntr2clk;
+       u32     cntr3clk;
+       u32     cntr4clk;
+       u32     cntr5clk;
+       u32     cntr6clk;
+       u32     cntr7clk;
+       u32     cntr8clk;
+       u32     cntr9clk;
+       u32     emacctl;
+       u32     gpiodiv;
+       u32     pllglob;
+       u32     fdbck;
+       u32     mem;
+       u32     memstat;
+       u32     pllc0;
+       u32     pllc1;
+       u32     vcocalib;
+       u32     _pad_0x100_0x124[10];
+};
+
+struct socfpga_clock_manager {
+       u32     ctrl;
+       u32     stat;
+       u32     testioctrl;
+       u32     intrgen;
+       u32     intrmsk;
+       u32     intrclr;
+       u32     intrsts;
+       u32     intrstk;
+       u32     intrraw;
+       u32     _pad_0x24_0x2c[3];
+       struct socfpga_clock_manager_main_pll main_pll;
+       struct socfpga_clock_manager_per_pll per_pll;
+};
+
+#define CLKMGR_CTRL_SAFEMODE                           (1 << 0)
+#define CLKMGR_BYPASS_MAINPLL_ALL                      0x00000007
+#define CLKMGR_BYPASS_PERPLL_ALL                       0x0000007f
+
+#define CLKMGR_INTER_MAINPLLLOCKED_MASK                        0x00000001
+#define CLKMGR_INTER_PERPLLLOCKED_MASK                 0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK                  0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK                   0x00000008
+#define CLKMGR_STAT_BUSY                               (1 << 0)
+#define CLKMGR_STAT_MAINPLL_LOCKED                     (1 << 8)
+#define CLKMGR_STAT_PERPLL_LOCKED                      (1 << 9)
+
+#define CLKMGR_PLLGLOB_PD_MASK                         0x00000001
+#define CLKMGR_PLLGLOB_RST_MASK                                0x00000002
+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK                   0X3
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET                 16
+#define CLKMGR_VCO_PSRC_EOSC1                          0
+#define CLKMGR_VCO_PSRC_INTOSC                         1
+#define CLKMGR_VCO_PSRC_F2S                            2
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK                  0X3f
+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET                        8
+
+#define CLKMGR_CLKSRC_MASK                             0x7
+#define CLKMGR_CLKSRC_OFFSET                           16
+#define CLKMGR_CLKSRC_MAIN                             0
+#define CLKMGR_CLKSRC_PER                              1
+#define CLKMGR_CLKSRC_OSC1                             2
+#define CLKMGR_CLKSRC_INTOSC                           3
+#define CLKMGR_CLKSRC_FPGA                             4
+#define CLKMGR_CLKCNT_MSK                              0x7ff
+
+#define CLKMGR_FDBCK_MDIV_MASK                         0xff
+#define CLKMGR_FDBCK_MDIV_OFFSET                       24
+
+#define CLKMGR_PLLC0_DIV_MASK                          0xff
+#define CLKMGR_PLLC1_DIV_MASK                          0xff
+#define CLKMGR_PLLC0_EN_OFFSET                         27
+#define CLKMGR_PLLC1_EN_OFFSET                         24
+
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET                    0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET                   8
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET                   16
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET                   24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET                        26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET                 28
+
+#define CLKMGR_NOCDIV_L4SPCLK_MASK                     0X3
+#define CLKMGR_NOCDIV_DIV1                             0
+#define CLKMGR_NOCDIV_DIV2                             1
+#define CLKMGR_NOCDIV_DIV4                             2
+#define CLKMGR_NOCDIV_DIV8                             3
+#define CLKMGR_CSPDBGCLK_DIV1                          0
+#define CLKMGR_CSPDBGCLK_DIV4                          1
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK                     0xff
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET                   9
+#define CLKMGR_VCOCALIB_HSCNT_MASK                     0xff
+
+#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET                 26
+#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET                 27
+#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET                 28
+
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK              0x00000020
+
+#endif /* _CLOCK_MANAGER_S10_ */

arch/arm/mach-socfpga/include/mach/handoff_s10.h new file +29 -0

new file mode 100644
index 0000000..d4b89ac
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef _HANDOFF_S10_H_
+#define _HANDOFF_S10_H_
+
+/*
+ * Offset for HW handoff from Quartus tools
+ */
+#define CONFIG_HANDOFF_BASE            0xFFE3F000
+#define CONFIG_HANDOFF_MUX             (CONFIG_HANDOFF_BASE + 0x10)
+#define CONFIG_HANDOFF_IOCTL           (CONFIG_HANDOFF_BASE + 0x1A0)
+#define CONFIG_HANDOFF_FPGA            (CONFIG_HANDOFF_BASE + 0x330)
+#define CONFIG_HANODFF_DELAY           (CONFIG_HANDOFF_BASE + 0x3F0)
+#define CONFIG_HANDOFF_CLOCK           (CONFIG_HANDOFF_BASE + 0x580)
+#define CONFIG_HANDOFF_MISC            (CONFIG_HANDOFF_BASE + 0x610)
+#define CONFIG_HANDOFF_MAGIC_MUX       0x504D5558
+#define CONFIG_HANDOFF_MAGIC_IOCTL     0x494F4354
+#define CONFIG_HANDOFF_MAGIC_FPGA      0x46504741
+#define CONFIG_HANDOFF_MAGIC_DELAY     0x444C4159
+#define CONFIG_HANDOFF_MAGIC_CLOCK     0x434C4B53
+#define CONFIG_HANDOFF_MAGIC_MISC      0x4D495343
+#define CONFIG_HANDOFF_OFFSET_LENGTH   0x4
+#define CONFIG_HANDOFF_OFFSET_DATA     0x10
+
+#endif /* _HANDOFF_S10_H_ */

arch/arm/mach-socfpga/wrap_pll_config_s10.c new file +23 -0

new file mode 100644
index 0000000..2a624d5
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/io.h>
+#include <asm/arch/handoff_s10.h>
+
+const struct cm_config * const cm_get_default_config(void)
+{
+       struct cm_config *cm_handoff_cfg = (struct cm_config *)
+               (CONFIG_HANDOFF_CLOCK + CONFIG_HANDOFF_OFFSET_DATA);
+       u32 *conversion = (u32 *)cm_handoff_cfg;
+       u32 i;
+
+       if (swab32(readl(CONFIG_HANDOFF_CLOCK)) == CONFIG_HANDOFF_MAGIC_CLOCK) {
+               writel(swab32(readl(CONFIG_HANDOFF_CLOCK)),
+                       CONFIG_HANDOFF_CLOCK);
+               for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
+                       conversion[i] = swab32(conversion[i]);

Quoted 93 lines · On Tue, Sep 19, 2017 at 4:22 AM,  <[email protected]> wrote:

From: Chin Liang See <[email protected]>

Add Clock Manager driver support for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/mach-socfpga/Makefile                     |   4 + arch/arm/mach-socfpga/clock_manager.c              |   4 +- arch/arm/mach-socfpga/clock_manager_s10.c          | 359
+++++++++++++++++++++
 arch/arm/mach-socfpga/include/mach/clock_manager.h |   2 + .../mach-socfpga/include/mach/clock_manager_s10.h  | 202
++++++++++++
 arch/arm/mach-socfpga/include/mach/handoff_s10.h   |  29 ++ arch/arm/mach-socfpga/wrap_pll_config_s10.c        |  46 +++

 7 files changed, 644 insertions(+), 2 deletions(-)

 create mode 100644 arch/arm/mach-socfpga/clock_manager_s10.c create mode 100644 arch/arm/mach- socfpga/include/mach/clock_manager_s10.h
 create mode 100644 arch/arm/mach- socfpga/include/mach/handoff_s10.h
 create mode 100644 arch/arm/mach-socfpga/wrap_pll_config_s10.c

arch/arm/mach- renamed from arch/arm/mach-socfpga/Makefile +0 -0

socfpga/Makefile
index 286bfef..e5f9dd7 100644

arch/arm/mach-socfpga/Makefile +0 -0

@@ -30,6 +30,10 @@ obj-y        += pinmux_arria10.o

 obj-y  += reset_manager_arria10.o
 endif

arch/arm/mach-socfpga/Makefile +4 -0

+ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
+obj-y  += clock_manager_s10.o
+obj-y  += wrap_pll_config_s10.o
+endif

 ifdef CONFIG_SPL_BUILD
 obj-y  += spl.o
 ifdef CONFIG_TARGET_SOCFPGA_GEN5

arch/arm/mach- renamed from arch/arm/mach-socfpga/clock_manager.c +0 -0

socfpga/clock_manager.c
index cb6ae03..f9450a4 100644

arch/arm/mach-socfpga/clock_manager.c +0 -0

@@ -21,7 +21,7 @@ void cm_wait_for_lock(u32 mask)
         do {
  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)

                inter_val = readl(&clock_manager_base->inter) & mask;

arch/arm/mach-socfpga/clock_manager.c +1 -1

-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else

                inter_val = readl(&clock_manager_base->stat) & mask;
 #endif
                /* Wait for stable lock */

arch/arm/mach-socfpga/clock_manager.c +1 -1

@@ -52,7 +52,7 @@ int set_cpu_clk_info(void)
 
  #if defined(CONFIG_TARGET_SOCFPGA_GEN5)
         gd->bd->bi_ddr_freq = cm_get_sdram_clk_hz() / 1000000;
-#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
+#else
         gd->bd->bi_ddr_freq = 0;
  #endif
 

arch/arm/mach-socfpga/clock_manager_s10.c new file +18 -0

new file mode 100644
index 0000000..a9f9b07
@@ -0,0 +1,359 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/arch/handoff_s10.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+static const struct socfpga_clock_manager *clock_manager_base =
+       (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS;
+
+/*
+ * function to write the bypass register which requires a poll of

the
+ * busy bit
+ */

arch/arm/mach-socfpga/clock_manager_s10.c line 25

Quoted 5 lines

arch/arm/mach-socfpga/clock_manager_s10.c new file +5 -0

+static void cm_write_bypass_mainpll(uint32_t val)
+{
+       writel(val, &clock_manager_base->main_pll.bypass);
+       cm_wait_for_fsm();
+}

Add a new line..

Quoted 17 lines

arch/arm/mach-socfpga/clock_manager_s10.c new file +7 -0

+static void cm_write_bypass_perpll(uint32_t val)
+{
+       writel(val, &clock_manager_base->per_pll.bypass);
+       cm_wait_for_fsm();
+}
+
+/* function to write the ctrl register which requires a poll of

the busy bit */

arch/arm/mach-socfpga/clock_manager_s10.c new file +8 -0

+static void cm_write_ctrl(uint32_t val)
+{
+       writel(val, &clock_manager_base->ctrl);
+       cm_wait_for_fsm();
+}
+
+/*
+ * Setup clocks while making no assumptions about previous state

Quoted 2 lines

of the clocks.
+ *

Remove extra line

Quoted 5 lines

+ */

arch/arm/mach-socfpga/clock_manager_s10.c new file +3 -0

+void cm_basic_init(const struct cm_config * const cfg)
+{
+       uint32_t mdiv, refclkdiv, mscnt, hscnt, vcocalib;

arch/arm/mach-socfpga/clock_manager_s10.c line 55

Quoted 10 lines

arch/arm/mach-socfpga/clock_manager_s10.c new file +10 -0

+
+       if (cfg == 0)
+               return;
+
+       /* Put all plls in bypass */
+       cm_write_bypass_mainpll(CLKMGR_BYPASS_MAINPLL_ALL);
+       cm_write_bypass_perpll(CLKMGR_BYPASS_PERPLL_ALL);
+
+       /* setup main PLL dividers */
+       /* calculate the vcocalib value */

Move the above comment to where vcocalib is getting calculated, or remove.

Quoted 1 line

Quoted 6 lines

+       mdiv = (cfg->main_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & +               CLKMGR_FDBCK_MDIV_MASK;
+       refclkdiv = (cfg->main_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+                    CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+       mscnt = 200 / (6 + mdiv) / refclkdiv;

Where are these values, 200 and 6 coming from? Should they be a #define?

Quoted 2 lines

+       hscnt = (mdiv + 6) * mscnt / refclkdiv - 9;

Same for 6 and 9 here...

Quoted 17 lines

+       vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | +                  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) << +                  CLKMGR_VCOCALIB_MSCNT_OFFSET);
+
+       writel((cfg->main_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & +               ~CLKMGR_PLLGLOB_RST_MASK),
+               &clock_manager_base->main_pll.pllglob); +       writel(cfg->main_pll_fdbck, &clock_manager_base-

Quoted 1 line

main_pll.fdbck);

+       writel(vcocalib, &clock_manager_base->main_pll.vcocalib); +       writel(cfg->main_pll_pllc0, &clock_manager_base-

Quoted 1 line

main_pll.pllc0);

+       writel(cfg->main_pll_pllc1, &clock_manager_base-

Quoted 1 line

main_pll.pllc1);

+       writel(cfg->main_pll_nocdiv, &clock_manager_base-

Quoted 1 line

main_pll.nocdiv);

Quoted 13 lines

+
+       /* setup peripheral PLL dividers */
+       /* calculate the vcocalib value */
+       mdiv = (cfg->per_pll_fdbck >> CLKMGR_FDBCK_MDIV_OFFSET) & +               CLKMGR_FDBCK_MDIV_MASK;
+       refclkdiv = (cfg->per_pll_pllglob >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+                    CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+       mscnt = 200 / (6 + mdiv) / refclkdiv;
+       hscnt = (mdiv + 6) * mscnt / refclkdiv - 9;
+       vcocalib = (hscnt & CLKMGR_VCOCALIB_HSCNT_MASK) | +                  ((mscnt & CLKMGR_VCOCALIB_MSCNT_MASK) << +                  CLKMGR_VCOCALIB_MSCNT_OFFSET);

Same comments as above...

Quoted 30 lines

+
+       writel((cfg->per_pll_pllglob & ~CLKMGR_PLLGLOB_PD_MASK & +               ~CLKMGR_PLLGLOB_RST_MASK),
+               &clock_manager_base->per_pll.pllglob); +       writel(cfg->per_pll_fdbck, &clock_manager_base-

Quoted 1 line

per_pll.fdbck);

+       writel(vcocalib, &clock_manager_base->per_pll.vcocalib); +       writel(cfg->per_pll_pllc0, &clock_manager_base-

Quoted 1 line

per_pll.pllc0);

+       writel(cfg->per_pll_pllc1, &clock_manager_base-

Quoted 1 line

per_pll.pllc1);

+       writel(cfg->per_pll_emacctl, &clock_manager_base-

Quoted 1 line

per_pll.emacctl);

+       writel(cfg->per_pll_gpiodiv, &clock_manager_base-

Quoted 1 line

per_pll.gpiodiv);

+
+       /* Take both PLL out of reset and power up */ +       setbits_le32(&clock_manager_base->main_pll.pllglob, +                    CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);
+       setbits_le32(&clock_manager_base->per_pll.pllglob, +                    CLKMGR_PLLGLOB_PD_MASK | CLKMGR_PLLGLOB_RST_MASK);

arch/arm/mach-socfpga/clock_manager_s10.c new file +6 -0

+
+#define LOCKED_MASK \
+       (CLKMGR_STAT_MAINPLL_LOCKED | \
+       CLKMGR_STAT_PERPLL_LOCKED)
+
+       cm_wait_for_lock(LOCKED_MASK);

Quoted 6 lines

+
+       /*
+        * Dividers for C2 to C9 only init after PLLs are lock. We will a large
+        * dividers value then final value as requested by hardware behaviour

Can you update this comment? I don't understand what "We will a large" means.

Quoted 75 lines

+        */
+       writel(0xff, &clock_manager_base->main_pll.mpuclk); +       writel(0xff, &clock_manager_base->main_pll.nocclk); +       writel(0xff, &clock_manager_base->main_pll.cntr2clk); +       writel(0xff, &clock_manager_base->main_pll.cntr3clk); +       writel(0xff, &clock_manager_base->main_pll.cntr4clk); +       writel(0xff, &clock_manager_base->main_pll.cntr5clk); +       writel(0xff, &clock_manager_base->main_pll.cntr6clk); +       writel(0xff, &clock_manager_base->main_pll.cntr7clk); +       writel(0xff, &clock_manager_base->main_pll.cntr8clk); +       writel(0xff, &clock_manager_base->main_pll.cntr9clk); +       writel(0xff, &clock_manager_base->per_pll.cntr2clk); +       writel(0xff, &clock_manager_base->per_pll.cntr3clk); +       writel(0xff, &clock_manager_base->per_pll.cntr4clk); +       writel(0xff, &clock_manager_base->per_pll.cntr5clk); +       writel(0xff, &clock_manager_base->per_pll.cntr6clk); +       writel(0xff, &clock_manager_base->per_pll.cntr7clk); +       writel(0xff, &clock_manager_base->per_pll.cntr8clk); +       writel(0xff, &clock_manager_base->per_pll.cntr9clk); +
+       writel(cfg->main_pll_mpuclk, &clock_manager_base-

Quoted 1 line

main_pll.mpuclk);

+       writel(cfg->main_pll_nocclk, &clock_manager_base-

Quoted 1 line

main_pll.nocclk);

+       writel(cfg->main_pll_cntr2clk, &clock_manager_base-

Quoted 1 line

main_pll.cntr2clk);

+       writel(cfg->main_pll_cntr3clk, &clock_manager_base-

Quoted 1 line

main_pll.cntr3clk);

+       writel(cfg->main_pll_cntr4clk, &clock_manager_base-

Quoted 1 line

main_pll.cntr4clk);

+       writel(cfg->main_pll_cntr5clk, &clock_manager_base-

Quoted 1 line

main_pll.cntr5clk);

+       writel(cfg->main_pll_cntr6clk, &clock_manager_base-

Quoted 1 line

main_pll.cntr6clk);

+       writel(cfg->main_pll_cntr7clk, &clock_manager_base-

Quoted 1 line

main_pll.cntr7clk);

+       writel(cfg->main_pll_cntr8clk, &clock_manager_base-

Quoted 1 line

main_pll.cntr8clk);

+       writel(cfg->main_pll_cntr9clk, &clock_manager_base-

Quoted 1 line

main_pll.cntr9clk);

+       writel(cfg->per_pll_cntr2clk, &clock_manager_base-

Quoted 1 line

per_pll.cntr2clk);

+       writel(cfg->per_pll_cntr3clk, &clock_manager_base-

Quoted 1 line

per_pll.cntr3clk);

+       writel(cfg->per_pll_cntr4clk, &clock_manager_base-

Quoted 1 line

per_pll.cntr4clk);

+       writel(cfg->per_pll_cntr5clk, &clock_manager_base-

Quoted 1 line

per_pll.cntr5clk);

+       writel(cfg->per_pll_cntr6clk, &clock_manager_base-

Quoted 1 line

per_pll.cntr6clk);

+       writel(cfg->per_pll_cntr7clk, &clock_manager_base-

Quoted 1 line

per_pll.cntr7clk);

+       writel(cfg->per_pll_cntr8clk, &clock_manager_base-

Quoted 1 line

per_pll.cntr8clk);

+       writel(cfg->per_pll_cntr9clk, &clock_manager_base-

Quoted 1 line

per_pll.cntr9clk);

arch/arm/mach-socfpga/clock_manager_s10.c new file +15 -0

+
+       /* Take all PLLs out of bypass */
+       cm_write_bypass_mainpll(0);
+       cm_write_bypass_perpll(0);
+
+       /* clear safe mode / out of boot mode */
+       cm_write_ctrl(readl(&clock_manager_base->ctrl)
+                       & ~(CLKMGR_CTRL_SAFEMODE));
+
+       /* Now ungate non-hw-managed clocks */
+       writel(~0, &clock_manager_base->main_pll.en);
+       writel(~0, &clock_manager_base->per_pll.en);
+
+       /* Clear the loss of lock bits (write 1 to clear) */
+       writel(CLKMGR_INTER_PERPLLLOST_MASK |

CLKMGR_INTER_MAINPLLLOST_MASK,
+              &clock_manager_base->intrclr);

arch/arm/mach-socfpga/clock_manager_s10.c line 174

Quoted 9 lines

arch/arm/mach-socfpga/clock_manager_s10.c new file +9 -0

+}
+
+static unsigned long cm_get_main_vco_clk_hz(void)
+{
+        unsigned long fref, refdiv, mdiv, reg, vco;
+
+       reg = readl(&clock_manager_base->main_pll.pllglob);
+
+       /* get the fref */

Useless comment...

Quoted 16 lines

+       fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) & +               CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+       switch (fref) {
+       case CLKMGR_VCO_PSRC_EOSC1:
+               fref = cm_get_osc_clk_hz(0);
+               break;
+       case CLKMGR_VCO_PSRC_INTOSC:
+               fref = cm_get_intosc_clk_hz(); +               break;
+       case CLKMGR_VCO_PSRC_F2S:
+               fref = cm_get_fpga_clk_hz();
+               break;
+       }
+
+       /* get the refdiv */

same..

Quoted 5 lines

+       refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) & +                 CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+       /* get the mdiv */

same...

Quoted 7 lines

+       reg = readl(&clock_manager_base->main_pll.fdbck); +       mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) & CLKMGR_FDBCK_MDIV_MASK;
+
+       vco = fref / refdiv;
+       vco = vco * (6 + mdiv);

Why 6? Define?

Quoted 144 lines

+       return vco;

arch/arm/mach-socfpga/clock_manager_s10.c new file +30 -0

+}
+
+static unsigned long cm_get_per_vco_clk_hz(void)
+{
+       unsigned long fref, refdiv, mdiv, reg, vco;
+
+       reg = readl(&clock_manager_base->per_pll.pllglob);
+
+       /* get the fref */
+       fref = (reg >> CLKMGR_PLLGLOB_VCO_PSRC_OFFSET) &
+               CLKMGR_PLLGLOB_VCO_PSRC_MASK;
+       switch (fref) {
+       case CLKMGR_VCO_PSRC_EOSC1:
+               fref = cm_get_osc_clk_hz(0);
+               break;
+       case CLKMGR_VCO_PSRC_INTOSC:
+               fref = cm_get_intosc_clk_hz();
+               break;
+       case CLKMGR_VCO_PSRC_F2S:
+               fref = cm_get_fpga_clk_hz();
+               break;
+       }
+
+       /* get the refdiv */
+       refdiv = (reg >> CLKMGR_PLLGLOB_REFCLKDIV_OFFSET) &
+                 CLKMGR_PLLGLOB_REFCLKDIV_MASK;
+
+       /* get the mdiv */
+       reg = readl(&clock_manager_base->per_pll.fdbck);
+       mdiv = (reg >> CLKMGR_FDBCK_MDIV_OFFSET) &

CLKMGR_FDBCK_MDIV_MASK;

arch/arm/mach-socfpga/clock_manager_s10.c new file +9 -0

+
+       vco = fref / refdiv;
+       vco = vco * (6 + mdiv);
+       return vco;
+}
+
+unsigned long cm_get_mpu_clk_hz(void)
+{
+       unsigned long clock = readl(&clock_manager_base-

Quoted 1 line

main_pll.mpuclk);

+       clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+       switch (clock) {
+       case CLKMGR_CLKSRC_MAIN:
+               clock = cm_get_main_vco_clk_hz(); +               clock /= (readl(&clock_manager_base-

Quoted 1 line

main_pll.pllc0) &

+                         CLKMGR_PLLC0_DIV_MASK);
+               break;
+
+       case CLKMGR_CLKSRC_PER:
+               clock = cm_get_per_vco_clk_hz();
+               clock /= (readl(&clock_manager_base->per_pll.pllc0) &
+                         CLKMGR_CLKCNT_MSK);
+               break;

arch/arm/mach-socfpga/clock_manager_s10.c new file +22 -0

+
+       case CLKMGR_CLKSRC_OSC1:
+               clock = cm_get_osc_clk_hz(0);
+               break;
+
+       case CLKMGR_CLKSRC_INTOSC:
+               clock = cm_get_intosc_clk_hz();
+               break;
+
+       case CLKMGR_CLKSRC_FPGA:
+               clock = cm_get_fpga_clk_hz();
+               break;
+       }
+
+       clock /= 1 + (readl(&clock_manager_base->main_pll.mpuclk) &
+               CLKMGR_CLKCNT_MSK);
+       return clock;
+}
+
+unsigned int cm_get_l3_main_clk_hz(void)
+{
+       uint32_t clock = readl(&clock_manager_base-

Quoted 1 line

main_pll.nocclk);

+       clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+       switch (clock) {
+       case CLKMGR_CLKSRC_MAIN:
+               clock = cm_get_main_vco_clk_hz(); +               clock /= (readl(&clock_manager_base-

Quoted 1 line

main_pll.pllc1) &

+                         CLKMGR_PLLC0_DIV_MASK);
+               break;
+
+       case CLKMGR_CLKSRC_PER:
+               clock = cm_get_per_vco_clk_hz();
+               clock /= (readl(&clock_manager_base->per_pll.pllc1) &
+                         CLKMGR_CLKCNT_MSK);
+               break;

arch/arm/mach-socfpga/clock_manager_s10.c new file +22 -0

+
+       case CLKMGR_CLKSRC_OSC1:
+               clock = cm_get_osc_clk_hz(0);
+               break;
+
+       case CLKMGR_CLKSRC_INTOSC:
+               clock = cm_get_intosc_clk_hz();
+               break;
+
+       case CLKMGR_CLKSRC_FPGA:
+               clock = cm_get_fpga_clk_hz();
+               break;
+       }
+
+       clock /= 1 + (readl(&clock_manager_base->main_pll.nocclk) &
+               CLKMGR_CLKCNT_MSK);
+       return clock;
+}
+
+unsigned int cm_get_mmc_controller_clk_hz(void)
+{
+       uint32_t clock = readl(&clock_manager_base-

Quoted 1 line

per_pll.cntr6clk);

+       clock = (clock >> CLKMGR_CLKSRC_OFFSET) & CLKMGR_CLKSRC_MASK;
+
+       switch (clock) {
+       case CLKMGR_CLKSRC_MAIN:
+               clock = cm_get_l3_main_clk_hz(); +               clock /= 1 + (readl(&clock_manager_base-

Quoted 1 line

main_pll.cntr6clk) &

+                       CLKMGR_CLKCNT_MSK);
+               break;
+
+       case CLKMGR_CLKSRC_PER:
+               clock = cm_get_l3_main_clk_hz(); +               clock /= 1 + (readl(&clock_manager_base-

Quoted 1 line

per_pll.cntr6clk) &

+                       CLKMGR_CLKCNT_MSK);
+               break;

arch/arm/mach-socfpga/clock_manager_s10.c new file +4 -0

+
+       case CLKMGR_CLKSRC_OSC1:
+               clock = cm_get_osc_clk_hz(0);
+               break;

arch/arm/mach-socfpga/clock_manager_s10.c line 338

Quoted 10 lines

arch/arm/mach-socfpga/clock_manager_s10.c new file +10 -0

+
+       case CLKMGR_CLKSRC_INTOSC:
+               clock = cm_get_intosc_clk_hz();
+               break;
+
+       case CLKMGR_CLKSRC_FPGA:
+               clock = cm_get_fpga_clk_hz();
+               break;
+       }
+       return clock/4;

Need space between '/'.

Quoted 337 lines

arch/arm/mach-socfpga/clock_manager_s10.c new file +7 -0

+}
+
+unsigned int cm_get_l4_sp_clk_hz(void)
+{
+       uint32_t clock = cm_get_l3_main_clk_hz();
+
+       clock /= (1 << ((readl(&clock_manager_base-

Quoted 1 line

main_pll.nocdiv) >>

+                 CLKMGR_NOCDIV_L4SPCLK_OFFSET) &
CLKMGR_CLKCNT_MSK));
+       return clock;

arch/arm/mach-socfpga/clock_manager_s10.c new file +5 -0

+}
+
+void cm_print_clock_quick_summary(void)
+{
+       printf("MPU         %d kHz\n", (u32)(cm_get_mpu_clk_hz() /

1000));
+       printf("L3 main     %d kHz\n", cm_get_l3_main_clk_hz() / 1000);
+       printf("Main VCO    %d kHz\n", (u32)(cm_get_main_vco_clk_hz() / 1000));
+       printf("Per VCO     %d kHz\n", (u32)(cm_get_per_vco_clk_hz() / 1000));
+       printf("EOSC1       %d kHz\n", cm_get_osc_clk_hz(0) / 1000);
+       printf("HPS MMC     %d kHz\n", cm_get_mmc_controller_clk_hz() / 1000);
+       printf("UART        %d kHz\n", cm_get_l4_sp_clk_hz() / 1000);

arch/arm/mach-socfpga/clock_manager_s10.c new file +1 -0

+}

arch/arm/mach-socfpga/include/mach/clock_manager.h +2 -0

index 4c6b1f8..ddf814f 100644
@@ -17,6 +17,8 @@ void cm_print_clock_quick_summary(void);
  #include <asm/arch/clock_manager_gen5.h>
  #elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
  #include <asm/arch/clock_manager_arria10.h>
+#elif defined(CONFIG_TARGET_SOCFPGA_STRATIX10)
+#include <asm/arch/clock_manager_s10.h>
  #endif
 
  #endif /* _CLOCK_MANAGER_H_ */

arch/arm/mach-socfpga/include/mach/clock_manager_s10.h new file +142 -0

new file mode 100644
index 0000000..c99ad97
@@ -0,0 +1,202 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef        _CLOCK_MANAGER_S10_
+#define        _CLOCK_MANAGER_S10_
+
+/* Clock speed accessors */
+unsigned long cm_get_mpu_clk_hz(void);
+unsigned long cm_get_sdram_clk_hz(void);
+unsigned int cm_get_l4_sp_clk_hz(void);
+unsigned int cm_get_mmc_controller_clk_hz(void);
+unsigned int cm_get_qspi_controller_clk_hz(void);
+unsigned int cm_get_spi_controller_clk_hz(void);
+const unsigned int cm_get_osc_clk_hz(const int osc);
+const unsigned int cm_get_f2s_per_ref_clk_hz(void);
+const unsigned int cm_get_f2s_sdr_ref_clk_hz(void);
+const unsigned int cm_get_intosc_clk_hz(void);
+const unsigned int cm_get_fpga_clk_hz(void);
+
+/* Clock configuration accessors */
+const struct cm_config * const cm_get_default_config(void);
+
+struct cm_config {
+       /* main group */
+       uint32_t main_pll_mpuclk;
+       uint32_t main_pll_nocclk;
+       uint32_t main_pll_cntr2clk;
+       uint32_t main_pll_cntr3clk;
+       uint32_t main_pll_cntr4clk;
+       uint32_t main_pll_cntr5clk;
+       uint32_t main_pll_cntr6clk;
+       uint32_t main_pll_cntr7clk;
+       uint32_t main_pll_cntr8clk;
+       uint32_t main_pll_cntr9clk;
+       uint32_t main_pll_nocdiv;
+       uint32_t main_pll_pllglob;
+       uint32_t main_pll_fdbck;
+       uint32_t main_pll_pllc0;
+       uint32_t main_pll_pllc1;
+       uint32_t spare;
+
+       /* peripheral group */
+       uint32_t per_pll_cntr2clk;
+       uint32_t per_pll_cntr3clk;
+       uint32_t per_pll_cntr4clk;
+       uint32_t per_pll_cntr5clk;
+       uint32_t per_pll_cntr6clk;
+       uint32_t per_pll_cntr7clk;
+       uint32_t per_pll_cntr8clk;
+       uint32_t per_pll_cntr9clk;
+       uint32_t per_pll_emacctl;
+       uint32_t per_pll_gpiodiv;
+       uint32_t per_pll_pllglob;
+       uint32_t per_pll_fdbck;
+       uint32_t per_pll_pllc0;
+       uint32_t per_pll_pllc1;
+
+       /* incoming clock */
+       uint32_t hps_osc_clk_hz;
+       uint32_t fpga_clk_hz;
+};
+
+void cm_basic_init(const struct cm_config * const cfg);
+
+struct socfpga_clock_manager_main_pll {
+       u32     en;
+       u32     ens;
+       u32     enr;
+       u32     bypass;
+       u32     bypasss;
+       u32     bypassr;
+       u32     mpuclk;
+       u32     nocclk;
+       u32     cntr2clk;
+       u32     cntr3clk;
+       u32     cntr4clk;
+       u32     cntr5clk;
+       u32     cntr6clk;
+       u32     cntr7clk;
+       u32     cntr8clk;
+       u32     cntr9clk;
+       u32     nocdiv;
+       u32     pllglob;
+       u32     fdbck;
+       u32     mem;
+       u32     memstat;
+       u32     pllc0;
+       u32     pllc1;
+       u32     vcocalib;
+       u32     _pad_0x90_0xA0[5];
+};
+
+struct socfpga_clock_manager_per_pll {
+       u32     en;
+       u32     ens;
+       u32     enr;
+       u32     bypass;
+       u32     bypasss;
+       u32     bypassr;
+       u32     cntr2clk;
+       u32     cntr3clk;
+       u32     cntr4clk;
+       u32     cntr5clk;
+       u32     cntr6clk;
+       u32     cntr7clk;
+       u32     cntr8clk;
+       u32     cntr9clk;
+       u32     emacctl;
+       u32     gpiodiv;
+       u32     pllglob;
+       u32     fdbck;
+       u32     mem;
+       u32     memstat;
+       u32     pllc0;
+       u32     pllc1;
+       u32     vcocalib;
+       u32     _pad_0x100_0x124[10];
+};
+
+struct socfpga_clock_manager {
+       u32     ctrl;
+       u32     stat;
+       u32     testioctrl;
+       u32     intrgen;
+       u32     intrmsk;
+       u32     intrclr;
+       u32     intrsts;
+       u32     intrstk;
+       u32     intrraw;
+       u32     _pad_0x24_0x2c[3];
+       struct socfpga_clock_manager_main_pll main_pll;
+       struct socfpga_clock_manager_per_pll per_pll;
+};
+
+#define CLKMGR_CTRL_SAFEMODE                           (1 << 0)
+#define CLKMGR_BYPASS_MAINPLL_ALL                      0x00000007
+#define CLKMGR_BYPASS_PERPLL_ALL                       0x0000007f
+
+#define

CLKMGR_INTER_MAINPLLLOCKED_MASK                        0x00000001

arch/arm/mach-socfpga/include/mach/clock_manager_s10.h new file +9 -0

+#define CLKMGR_INTER_PERPLLLOCKED_MASK                 0x00000002
+#define CLKMGR_INTER_MAINPLLLOST_MASK                  0x00000004
+#define CLKMGR_INTER_PERPLLLOST_MASK                   0x00000008
+#define CLKMGR_STAT_BUSY                               (1 << 0)
+#define CLKMGR_STAT_MAINPLL_LOCKED                     (1 << 8)
+#define CLKMGR_STAT_PERPLL_LOCKED                      (1 << 9)
+
+#define CLKMGR_PLLGLOB_PD_MASK                         0x00000001
+#define

CLKMGR_PLLGLOB_RST_MASK                                0x00000002

arch/arm/mach-socfpga/include/mach/clock_manager_s10.h new file +51 -0

+#define CLKMGR_PLLGLOB_VCO_PSRC_MASK                   0X3
+#define CLKMGR_PLLGLOB_VCO_PSRC_OFFSET                 16
+#define CLKMGR_VCO_PSRC_EOSC1                          0
+#define CLKMGR_VCO_PSRC_INTOSC                         1
+#define CLKMGR_VCO_PSRC_F2S                            2
+#define CLKMGR_PLLGLOB_REFCLKDIV_MASK                  0X3f
+#define CLKMGR_PLLGLOB_REFCLKDIV_OFFSET                        8
+
+#define CLKMGR_CLKSRC_MASK                             0x7
+#define CLKMGR_CLKSRC_OFFSET                           16
+#define CLKMGR_CLKSRC_MAIN                             0
+#define CLKMGR_CLKSRC_PER                              1
+#define CLKMGR_CLKSRC_OSC1                             2
+#define CLKMGR_CLKSRC_INTOSC                           3
+#define CLKMGR_CLKSRC_FPGA                             4
+#define CLKMGR_CLKCNT_MSK                              0x7ff
+
+#define CLKMGR_FDBCK_MDIV_MASK                         0xff
+#define CLKMGR_FDBCK_MDIV_OFFSET                       24
+
+#define CLKMGR_PLLC0_DIV_MASK                          0xff
+#define CLKMGR_PLLC1_DIV_MASK                          0xff
+#define CLKMGR_PLLC0_EN_OFFSET                         27
+#define CLKMGR_PLLC1_EN_OFFSET                         24
+
+#define CLKMGR_NOCDIV_L4MAIN_OFFSET                    0
+#define CLKMGR_NOCDIV_L4MPCLK_OFFSET                   8
+#define CLKMGR_NOCDIV_L4SPCLK_OFFSET                   16
+#define CLKMGR_NOCDIV_CSATCLK_OFFSET                   24
+#define CLKMGR_NOCDIV_CSTRACECLK_OFFSET                        26
+#define CLKMGR_NOCDIV_CSPDBGCLK_OFFSET                 28
+
+#define CLKMGR_NOCDIV_L4SPCLK_MASK                     0X3
+#define CLKMGR_NOCDIV_DIV1                             0
+#define CLKMGR_NOCDIV_DIV2                             1
+#define CLKMGR_NOCDIV_DIV4                             2
+#define CLKMGR_NOCDIV_DIV8                             3
+#define CLKMGR_CSPDBGCLK_DIV1                          0
+#define CLKMGR_CSPDBGCLK_DIV4                          1
+
+#define CLKMGR_VCOCALIB_MSCNT_MASK                     0xff
+#define CLKMGR_VCOCALIB_MSCNT_OFFSET                   9
+#define CLKMGR_VCOCALIB_HSCNT_MASK                     0xff
+
+#define CLKMGR_EMACCTL_EMAC0SEL_OFFSET                 26
+#define CLKMGR_EMACCTL_EMAC1SEL_OFFSET                 27
+#define CLKMGR_EMACCTL_EMAC2SEL_OFFSET                 28
+
+#define CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK              0x00000020
+
+#endif /* _CLOCK_MANAGER_S10_ */

arch/arm/mach-socfpga/include/mach/handoff_s10.h new file +14 -0

new file mode 100644
index 0000000..d4b89ac
@@ -0,0 +1,29 @@
+/*
+ *  Copyright (C) 2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#ifndef _HANDOFF_S10_H_
+#define _HANDOFF_S10_H_
+
+/*
+ * Offset for HW handoff from Quartus tools
+ */
+#define CONFIG_HANDOFF_BASE            0xFFE3F000
+#define CONFIG_HANDOFF_MUX             (CONFIG_HANDOFF_BASE +

0x10)
+#define CONFIG_HANDOFF_IOCTL           (CONFIG_HANDOFF_BASE + 0x1A0)
+#define CONFIG_HANDOFF_FPGA            (CONFIG_HANDOFF_BASE + 0x330)
+#define CONFIG_HANODFF_DELAY           (CONFIG_HANDOFF_BASE + 0x3F0)
+#define CONFIG_HANDOFF_CLOCK           (CONFIG_HANDOFF_BASE + 0x580)
+#define CONFIG_HANDOFF_MISC            (CONFIG_HANDOFF_BASE + 0x610)

arch/arm/mach-socfpga/include/mach/handoff_s10.h new file +10 -0

+#define CONFIG_HANDOFF_MAGIC_MUX       0x504D5558
+#define CONFIG_HANDOFF_MAGIC_IOCTL     0x494F4354
+#define CONFIG_HANDOFF_MAGIC_FPGA      0x46504741
+#define CONFIG_HANDOFF_MAGIC_DELAY     0x444C4159
+#define CONFIG_HANDOFF_MAGIC_CLOCK     0x434C4B53
+#define CONFIG_HANDOFF_MAGIC_MISC      0x4D495343
+#define CONFIG_HANDOFF_OFFSET_LENGTH   0x4
+#define CONFIG_HANDOFF_OFFSET_DATA     0x10
+
+#endif /* _HANDOFF_S10_H_ */

arch/arm/mach-socfpga/wrap_pll_config_s10.c new file +15 -0

new file mode 100644
index 0000000..2a624d5
@@ -0,0 +1,46 @@
+/*
+ * Copyright (C) 2016-2017 Intel Corporation <www.intel.com>
+ *
+ * SPDX-License-Identifier:    GPL-2.0
+ */
+
+#include <common.h>
+#include <asm/arch/clock_manager.h>
+#include <asm/io.h>
+#include <asm/arch/handoff_s10.h>
+
+const struct cm_config * const cm_get_default_config(void)
+{
+       struct cm_config *cm_handoff_cfg = (struct cm_config *)
+               (CONFIG_HANDOFF_CLOCK +

CONFIG_HANDOFF_OFFSET_DATA);
+       u32 *conversion = (u32 *)cm_handoff_cfg;
+       u32 i;
+
+       if (swab32(readl(CONFIG_HANDOFF_CLOCK)) == CONFIG_HANDOFF_MAGIC_CLOCK) {
+               writel(swab32(readl(CONFIG_HANDOFF_CLOCK)), +                       CONFIG_HANDOFF_CLOCK);
+               for (i = 0; i < (sizeof(*cm_handoff_cfg) / sizeof(u32)); i++)
+                       conversion[i] = swab32(conversion[i]); +               return cm_handoff_cfg;
+       } else if (readl(CONFIG_HANDOFF_CLOCK) == CONFIG_HANDOFF_MAGIC_CLOCK) {
+               return cm_handoff_cfg;
+       } else
+               return 0;

arch/arm/mach-socfpga/wrap_pll_config_s10.c line 33

Quoted 5 lines

arch/arm/mach-socfpga/wrap_pll_config_s10.c new file +5 -0

+}
+
+const unsigned int cm_get_osc_clk_hz(const int osc)
+{
+       return 25000000;

Needs to be a #define

arch/arm/mach-socfpga/wrap_pll_config_s10.c line 39

Quoted 7 lines

arch/arm/mach-socfpga/wrap_pll_config_s10.c new file +6 -0

+}
+
+const unsigned int cm_get_intosc_clk_hz(void)
+{
+       /* theory maximum internal osc clock */
+       return 460000000;

Same...

arch/arm/mach-socfpga/wrap_pll_config_s10.c line 45

Quoted 7 lines

arch/arm/mach-socfpga/wrap_pll_config_s10.c new file +6 -0

+}
+
+const unsigned int cm_get_fpga_clk_hz(void)
+{
+       /* assuming 50MHz */
+       return 50000000;

Same..

Dinh

From: Chin Liang See <[email protected]>

Add Reset Manager driver support for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/mach-socfpga/Makefile                     |   1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116 +++++++++++++++++
 arch/arm/mach-socfpga/reset_manager.c              |   5 +
 arch/arm/mach-socfpga/reset_manager_s10.c          | 140 +++++++++++++++++++++

Quoted 6 lines · On Tue, Sep 19, 2017 at 4:22 AM,  <[email protected]> wrote:

From: Chin Liang See <[email protected]>

Add Reset Manager driver support for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

Quoted 8 lines

---
 arch/arm/mach-socfpga/Makefile                     |   1 + arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 + .../mach-socfpga/include/mach/reset_manager_s10.h  | 116
+++++++++++++++++
 arch/arm/mach-socfpga/reset_manager.c              |   5 + arch/arm/mach-socfpga/reset_manager_s10.c          | 140
+++++++++++++++++++++

I don't see why you need to add a new file for S10? The functionality between
Gen 5 and Stratix10 is identical for the reset manager.

Dinh

Quoted 15 lines · Dinh Nguyen

Quoted 14 lines · On Tue, Sep 19, 2017 at 4:22 AM, <[email protected]> wrote:

From: Chin Liang See <[email protected]>

Add Reset Manager driver support for Stratix SoC

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/mach-socfpga/Makefile                     |   1 +
 arch/arm/mach-socfpga/include/mach/reset_manager.h |   2 +
 .../mach-socfpga/include/mach/reset_manager_s10.h  | 116
+++++++++++++++++
 arch/arm/mach-socfpga/reset_manager.c              |   5 +
 arch/arm/mach-socfpga/reset_manager_s10.c          | 140

+++++++++++++++++++++

Quoted 3 lines

I don't see why you need to add a new file for S10? The functionality between
Gen 5 and Stratix10 is identical for the reset manager.

Not really, they have same functions name but sequences are difference due to diff interconnect technology. Hence, try to avoid too much #if #else

From: Chin Liang See <[email protected]>

Add misc support for Stratix SoC

Quoted 4 lines · On Tue, Sep 19, 2017 at 4:22 AM,  <[email protected]> wrote:

From: Chin Liang See <[email protected]>

Add misc support for Stratix SoC

Just because the file is call misc.c doesn't mean you can just keep the commit
message that simple. Can you add what functions are you adding?

Quoted 54 lines

Signed-off-by Chin Liang See <[email protected]>

---
 arch/arm/mach-socfpga/Makefile   |   1 +
 arch/arm/mach-socfpga/misc.c     |   4 +
 arch/arm/mach-socfpga/misc_s10.c | 165
+++++++++++++++++++++++++++++++++++++++

 3 files changed, 170 insertions(+)

 create mode 100644 arch/arm/mach-socfpga/misc_s10.c

arch/arm/mach- renamed from arch/arm/mach-socfpga/Makefile +0 -0

socfpga/Makefile
index 910eb6f..b253914 100644

arch/arm/mach-socfpga/Makefile +0 -0

@@ -32,6 +32,7 @@ endif
 

 ifdef CONFIG_TARGET_SOCFPGA_STRATIX10
 obj-y  += clock_manager_s10.o
+obj-y  += misc_s10.o
 obj-y  += reset_manager_s10.o
 obj-y  += system_manager_s10.o
 obj-y  += wrap_pinmux_config_s10.o

arch/arm/mach- renamed from arch/arm/mach-socfpga/misc.c +0 -0

socfpga/misc.c
index 00eff90..2ea94bc 100644

arch/arm/mach-socfpga/misc.c +1 -0

@@ -23,8 +23,10 @@
 
  DECLARE_GLOBAL_DATA_PTR;
 
+#ifdef CONFIG_SYS_L2_PL310

 static const struct pl310_regs *const pl310 = (struct pl310_regs *)CONFIG_SYS_PL310_BASE; +#endif

 struct bsel bsel_str[] = {
        { "rsvd", "Reserved", },

arch/arm/mach-socfpga/misc.c +2 -0

@@ -53,6 +55,7 @@ void enable_caches(void)
  #endif
  }
 
+#ifdef CONFIG_SYS_L2_PL310
  void v7_outer_cache_enable(void)
  {
         /* Disable the L2 cache */

@@ -73,6 +76,7 @@ void v7_outer_cache_disable(void)
         /* Disable the L2 cache */
         clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN);
  }
+#endif
 

arch/arm/mach-socfpga/misc_s10.c

Quoted 8 lines

arch/arm/mach-socfpga/misc.c +0 -0

  #if defined(CONFIG_SYS_CONSOLE_IS_IN_ENV) && \
  defined(CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE)

arch/arm/mach- renamed from arch/arm/mach-socfpga/misc_s10.c +0 -0

socfpga/misc_s10.c
new file mode 100644
index 0000000..b84f055

arch/arm/mach-socfpga/misc_s10.c new file +0 -0

This misc_s10.c look very similar to the Gen5 stuff, can you re-use it?

Dinh