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Patch "KVM: PPC: Book3S HV: Don't access XIVE PIPR register using byte accesses" has been added to the 4.13-stable tree

PATCH [email protected] 1 participant 1 message Oct 2, 2017

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This is a note to let you know that I've just added the patch titled

KVM: PPC: Book3S HV: Don't access XIVE PIPR register using byte accesses

to the 4.13-stable tree which can be found at:
http://www.kernel.org/git/?p=linux/kernel/git/stable/stable-queue.git;a=summary

The filename of the patch is:
kvm-ppc-book3s-hv-don-t-access-xive-pipr-register-using-byte-accesses.patch
and it can be found in the queue-4.13 subdirectory.

If you, or anyone else, feels it should not be added to the stable tree, please let <[email protected]> know about it.

Quoted 1 line

From d222af072380c4470295c07d84ecb15f4937e365 Mon Sep 17 00:00:00 2001

From: Benjamin Herrenschmidt <[email protected]>
Date: Wed, 6 Sep 2017 15:20:55 +1000
Subject: KVM: PPC: Book3S HV: Don't access XIVE PIPR register using byte accesses

From: Benjamin Herrenschmidt <[email protected]>

commit d222af072380c4470295c07d84ecb15f4937e365 upstream.

The XIVE interrupt controller on POWER9 machines doesn't support byte accesses to any register in the thread management area other than the CPPR (current processor priority register). In particular, when reading the PIPR (pending interrupt priority register), we need to do a 32-bit or 64-bit load.

Fixes 2c4fb78f78b6 ("KVM: PPC: Book3S HV: Workaround POWER9 DD1.0 bug causing IPB bit loss")
Signed-off-by Benjamin Herrenschmidt <[email protected]>
Signed-off-by Paul Mackerras <[email protected]>
Signed-off-by Greg Kroah-Hartman <[email protected]>
---
 arch/powerpc/kvm/book3s_hv_rm_xive.c    |    1 -
 arch/powerpc/kvm/book3s_xive.c          |    1 -
 arch/powerpc/kvm/book3s_xive_template.c |    7 ++++---
 3 files changed, 4 insertions(+), 5 deletions(-)
arch/powerpc/kvm/book3s_hv_rm_xive.c +0 -1
@@ -38,7 +38,6 @@ static inline void __iomem *get_tima_phy
 #define __x_tima		get_tima_phys()
 #define __x_eoi_page(xd)	((void __iomem *)((xd)->eoi_page))
 #define __x_trig_page(xd)	((void __iomem *)((xd)->trig_page))
-#define __x_readb	__raw_rm_readb
 #define __x_writeb	__raw_rm_writeb
 #define __x_readw	__raw_rm_readw
 #define __x_readq	__raw_rm_readq
arch/powerpc/kvm/book3s_xive.c +0 -1
@@ -48,7 +48,6 @@
 #define __x_tima		xive_tima
 #define __x_eoi_page(xd)	((void __iomem *)((xd)->eoi_mmio))
 #define __x_trig_page(xd)	((void __iomem *)((xd)->trig_mmio))
-#define __x_readb	__raw_readb
 #define __x_writeb	__raw_writeb
 #define __x_readw	__raw_readw
 #define __x_readq	__raw_readq
arch/powerpc/kvm/book3s_xive_template.c +4 -3
@@ -28,7 +28,8 @@ static void GLUE(X_PFX,ack_pending)(stru
 	 * bit.
 	 */
 	if (cpu_has_feature(CPU_FTR_POWER9_DD1)) {
-		u8 pipr = __x_readb(__x_tima + TM_QW1_OS + TM_PIPR);
+		__be64 qw1 = __x_readq(__x_tima + TM_QW1_OS);
+		u8 pipr = be64_to_cpu(qw1) & 0xff;
 		if (pipr >= xc->hw_cppr)
 			return;
 	}

@@ -336,7 +337,6 @@ X_STATIC unsigned long GLUE(X_PFX,h_ipol
 	struct kvmppc_xive_vcpu *xc = vcpu->arch.xive_vcpu;
 	u8 pending = xc->pending;
 	u32 hirq;
-	u8 pipr;
 
 	pr_devel("H_IPOLL(server=%ld)\n", server);
 

@@ -353,7 +353,8 @@ X_STATIC unsigned long GLUE(X_PFX,h_ipol
 		pending = 0xff;
 	} else {
 		/* Grab pending interrupt if any */
-		pipr = __x_readb(__x_tima + TM_QW1_OS + TM_PIPR);
+		__be64 qw1 = __x_readq(__x_tima + TM_QW1_OS);
+		u8 pipr = be64_to_cpu(qw1) & 0xff;
 		if (pipr < 8)
 			pending |= 1 << pipr;
 	}

Patches currently in stable-queue which might be from [email protected] are

queue-4.13/kvm-ppc-book3s-hv-don-t-access-xive-pipr-register-using-byte-accesses.patch